1 /* $Id: fore200e.h,v 1.4 2000/04/14 10:10:34 davem Exp $ */
2 #ifndef _FORE200E_H
3 #define _FORE200E_H
4
5 #ifdef __KERNEL__
6 #include <linux/config.h>
7
8 /* rx buffer sizes */
9
10 #define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
11 #define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
12
13
14 #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */
15
16
17 #define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */
18
19
20 #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */
21 #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */
22
23 #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */
24 #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */
25
26 #define BUFFER_S1_NBR (RBD_BLK_SIZE * 2)
27 #define BUFFER_L1_NBR (RBD_BLK_SIZE * 2)
28
29 #define BUFFER_S2_NBR (RBD_BLK_SIZE * 2)
30 #define BUFFER_L2_NBR (RBD_BLK_SIZE * 2)
31
32
33 #define QUEUE_SIZE_CMD 16 /* command queue capacity */
34 #define QUEUE_SIZE_RX 64 /* receive queue capacity */
35 #define QUEUE_SIZE_TX 256 /* transmit queue capacity */
36 #define QUEUE_SIZE_BS 16 /* buffer supply queue capacity */
37
38 #define NBR_CONNECT 1024 /* number of ATM connections */
39
40
41 #define TSD_FIXED 2
42 #define TSD_EXTENSION 0
43 #define TSD_NBR (TSD_FIXED + TSD_EXTENSION)
44
45
46 /* the cp starts putting a received PDU into one *small* buffer,
47 then it uses a number of *large* buffers for the trailing data.
48 we compute here the total number of receive segment descriptors
49 required to hold the largest possible PDU */
50
51 #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)
52
53 #define RSD_FIXED 3
54
55 /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
56 but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
57 so we add one extra RSD to RSD_EXTENSION
58 (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */
59
60 #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1)
61 #define RSD_NBR (RSD_FIXED + RSD_EXTENSION)
62
63
64 #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data))
65 #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data))
66
67 /* bitfields endian games */
68
69 #if defined(__LITTLE_ENDIAN_BITFIELD)
70 #define BITFIELD2(b1, b2) b1; b2;
71 #define BITFIELD3(b1, b2, b3) b1; b2; b3;
72 #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4;
73 #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5;
74 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6;
75 #elif defined(__BIG_ENDIAN_BITFIELD)
76 #define BITFIELD2(b1, b2) b2; b1;
77 #define BITFIELD3(b1, b2, b3) b3; b2; b1;
78 #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1;
79 #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1;
80 #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1;
81 #else
82 #error unknown bitfield endianess
83 #endif
84
85
86 /* ATM cell header (minus HEC byte) */
87
88 typedef struct atm_header {
89 BITFIELD5(
90 u32 clp : 1, /* cell loss priority */
91 u32 plt : 3, /* payload type */
92 u32 vci : 16, /* virtual channel identifier */
93 u32 vpi : 8, /* virtual path identifier */
94 u32 gfc : 4 /* generic flow control */
95 )
96 } atm_header_t;
97
98
99 /* ATM adaptation layer id */
100
101 typedef enum fore200e_aal {
102 FORE200E_AAL0 = 0,
103 FORE200E_AAL34 = 4,
104 FORE200E_AAL5 = 5,
105 } fore200e_aal_t;
106
107
108 /* transmit PDU descriptor specification */
109
110 typedef struct tpd_spec {
111 BITFIELD4(
112 u32 length : 16, /* total PDU length */
113 u32 nseg : 8, /* number of transmit segments */
114 enum fore200e_aal aal : 4, /* adaptation layer */
115 u32 intr : 4 /* interrupt requested */
116 )
117 } tpd_spec_t;
118
119
120 /* transmit PDU rate control */
121
122 typedef struct tpd_rate
123 {
124 BITFIELD2(
125 u32 idle_cells : 16, /* number of idle cells to insert */
126 u32 data_cells : 16 /* number of data cells to transmit */
127 )
128 } tpd_rate_t;
129
130
131 /* transmit segment descriptor */
132
133 typedef struct tsd {
134 u32 buffer; /* transmit buffer DMA address */
135 u32 length; /* number of bytes in buffer */
136 } tsd_t;
137
138
139 /* transmit PDU descriptor */
140
141 typedef struct tpd {
142 struct atm_header atm_header; /* ATM header minus HEC byte */
143 struct tpd_spec spec; /* tpd specification */
144 struct tpd_rate rate; /* tpd rate control */
145 u32 pad; /* reserved */
146 struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */
147 } tpd_t;
148
149
150 /* receive segment descriptor */
151
152 typedef struct rsd {
153 u32 handle; /* host supplied receive buffer handle */
154 u32 length; /* number of bytes in buffer */
155 } rsd_t;
156
157
158 /* receive PDU descriptor */
159
160 typedef struct rpd {
161 struct atm_header atm_header; /* ATM header minus HEC byte */
162 u32 nseg; /* number of receive segments */
163 struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */
164 } rpd_t;
165
166
167 /* buffer scheme */
168
169 typedef enum buffer_scheme {
170 BUFFER_SCHEME_ONE,
171 BUFFER_SCHEME_TWO,
172 BUFFER_SCHEME_NBR /* always last */
173 } buffer_scheme_t;
174
175
176 /* buffer magnitude */
177
178 typedef enum buffer_magn {
179 BUFFER_MAGN_SMALL,
180 BUFFER_MAGN_LARGE,
181 BUFFER_MAGN_NBR /* always last */
182 } buffer_magn_t;
183
184
185 /* receive buffer descriptor */
186
187 typedef struct rbd {
188 u32 handle; /* host supplied handle */
189 u32 buffer_haddr; /* host DMA address of host buffer */
190 } rbd_t;
191
192
193 /* receive buffer descriptor block */
194
195 typedef struct rbd_block {
196 struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */
197 } rbd_block_t;
198
199
200 /* tpd DMA address */
201
202 typedef struct tpd_haddr {
203 BITFIELD3(
204 u32 size : 4, /* tpd size expressed in 32 byte blocks */
205 u32 pad : 1, /* reserved */
206 u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */
207 )
208 } tpd_haddr_t;
209
210
211 /* cp resident transmit queue entry */
212
213 typedef struct cp_txq_entry {
214 struct tpd_haddr tpd_haddr; /* host DMA address of tpd */
215 u32 status_haddr; /* host DMA address of completion status */
216 } cp_txq_entry_t;
217
218
219 /* cp resident receive queue entry */
220
221 typedef struct cp_rxq_entry {
222 u32 rpd_haddr; /* host DMA address of rpd */
223 u32 status_haddr; /* host DMA address of completion status */
224 } cp_rxq_entry_t;
225
226
227 /* cp resident buffer supply queue entry */
228
229 typedef struct cp_bsq_entry {
230 u32 rbd_block_haddr; /* host DMA address of rbd block */
231 u32 status_haddr; /* host DMA address of completion status */
232 } cp_bsq_entry_t;
233
234
235 /* completion status */
236
237 typedef volatile enum status {
238 STATUS_PENDING = (1<<0), /* initial status (written by host) */
239 STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */
240 STATUS_FREE = (1<<2), /* initial status (written by host) */
241 STATUS_ERROR = (1<<3) /* completion status (written by cp) */
242 } status_t;
243
244
245 /* cp operation code */
246
247 typedef enum opcode {
248 OPCODE_INITIALIZE = 1, /* initialize board */
249 OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */
250 OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */
251 OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */
252 OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */
253 OPCODE_GET_STATS, /* get board statistics */
254 OPCODE_SET_OC3, /* set OC-3 registers */
255 OPCODE_GET_OC3, /* get OC-3 registers */
256 OPCODE_RESET_STATS, /* reset board statistics */
257 OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */
258 OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the
259 firmware to be low order bits from
260 the VPI field of the ATM cell header */
261 OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */
262 } opcode_t;
263
264
265 /* virtual path / virtual channel identifers */
266
267 typedef struct vpvc {
268 BITFIELD3(
269 u32 vci : 16, /* virtual channel identifier */
270 u32 vpi : 8, /* virtual path identifier */
271 u32 pad : 8 /* reserved */
272 )
273 } vpvc_t;
274
275
276 /* activate VC command opcode */
277
278 typedef struct activate_opcode {
279 BITFIELD4(
280 enum opcode opcode : 8, /* cp opcode */
281 enum fore200e_aal aal : 8, /* adaptation layer */
282 enum buffer_scheme scheme : 8, /* buffer scheme */
283 u32 pad : 8 /* reserved */
284 )
285 } activate_opcode_t;
286
287
288 /* activate VC command block */
289
290 typedef struct activate_block {
291 struct activate_opcode opcode; /* activate VC command opcode */
292 struct vpvc vpvc; /* VPI/VCI */
293 u32 mtu; /* for AAL0 only */
294
295 } activate_block_t;
296
297
298 /* deactivate VC command opcode */
299
300 typedef struct deactivate_opcode {
301 BITFIELD2(
302 enum opcode opcode : 8, /* cp opcode */
303 u32 pad : 24 /* reserved */
304 )
305 } deactivate_opcode_t;
306
307
308 /* deactivate VC command block */
309
310 typedef struct deactivate_block {
311 struct deactivate_opcode opcode; /* deactivate VC command opcode */
312 struct vpvc vpvc; /* VPI/VCI */
313 } deactivate_block_t;
314
315
316 /* OC-3 registers */
317
318 typedef struct oc3_regs {
319 u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite
320 Saturn User Network Interface documentation
321 for a description of the OC-3 chip registers */
322 } oc3_regs_t;
323
324
325 /* set/get OC-3 regs command opcode */
326
327 typedef struct oc3_opcode {
328 BITFIELD4(
329 enum opcode opcode : 8, /* cp opcode */
330 u32 reg : 8, /* register index */
331 u32 value : 8, /* register value */
332 u32 mask : 8 /* register mask that specifies which
333 bits of the register value field
334 are significant */
335 )
336 } oc3_opcode_t;
337
338
339 /* set/get OC-3 regs command block */
340
341 typedef struct oc3_block {
342 struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */
343 u32 regs_haddr; /* host DMA address of OC-3 regs buffer */
344 } oc3_block_t;
345
346
347 /* physical encoding statistics */
348
349 typedef struct stats_phy {
350 u32 crc_header_errors; /* cells received with bad header CRC */
351 u32 framing_errors; /* cells received with bad framing */
352 u32 pad[ 2 ]; /* i960 padding */
353 } stats_phy_t;
354
355
356 /* OC-3 statistics */
357
358 typedef struct stats_oc3 {
359 u32 section_bip8_errors; /* section 8 bit interleaved parity */
360 u32 path_bip8_errors; /* path 8 bit interleaved parity */
361 u32 line_bip24_errors; /* line 24 bit interleaved parity */
362 u32 line_febe_errors; /* line far end block errors */
363 u32 path_febe_errors; /* path far end block errors */
364 u32 corr_hcs_errors; /* correctable header check sequence */
365 u32 ucorr_hcs_errors; /* uncorrectable header check sequence */
366 u32 pad[ 1 ]; /* i960 padding */
367 } stats_oc3_t;
368
369
370 /* ATM statistics */
371
372 typedef struct stats_atm {
373 u32 cells_transmitted; /* cells transmitted */
374 u32 cells_received; /* cells received */
375 u32 vpi_bad_range; /* cell drops: VPI out of range */
376 u32 vpi_no_conn; /* cell drops: no connection for VPI */
377 u32 vci_bad_range; /* cell drops: VCI out of range */
378 u32 vci_no_conn; /* cell drops: no connection for VCI */
379 u32 pad[ 2 ]; /* i960 padding */
380 } stats_atm_t;
381
382 /* AAL0 statistics */
383
384 typedef struct stats_aal0 {
385 u32 cells_transmitted; /* cells transmitted */
386 u32 cells_received; /* cells received */
387 u32 cells_dropped; /* cells dropped */
388 u32 pad[ 1 ]; /* i960 padding */
389 } stats_aal0_t;
390
391
392 /* AAL3/4 statistics */
393
394 typedef struct stats_aal34 {
395 u32 cells_transmitted; /* cells transmitted from segmented PDUs */
396 u32 cells_received; /* cells reassembled into PDUs */
397 u32 cells_crc_errors; /* payload CRC error count */
398 u32 cells_protocol_errors; /* SAR or CS layer protocol errors */
399 u32 cells_dropped; /* cells dropped: partial reassembly */
400 u32 cspdus_transmitted; /* CS PDUs transmitted */
401 u32 cspdus_received; /* CS PDUs received */
402 u32 cspdus_protocol_errors; /* CS layer protocol errors */
403 u32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */
404 u32 pad[ 3 ]; /* i960 padding */
405 } stats_aal34_t;
406
407
408 /* AAL5 statistics */
409
410 typedef struct stats_aal5 {
411 u32 cells_transmitted; /* cells transmitted from segmented SDUs */
412 u32 cells_received; /* cells reassembled into SDUs */
413 u32 cells_dropped; /* reassembled PDUs dropped (in cells) */
414 u32 congestion_experienced; /* CRC error and length wrong */
415 u32 cspdus_transmitted; /* CS PDUs transmitted */
416 u32 cspdus_received; /* CS PDUs received */
417 u32 cspdus_crc_errors; /* CS PDUs CRC errors */
418 u32 cspdus_protocol_errors; /* CS layer protocol errors */
419 u32 cspdus_dropped; /* reassembled PDUs dropped */
420 u32 pad[ 3 ]; /* i960 padding */
421 } stats_aal5_t;
422
423
424 /* auxiliary statistics */
425
426 typedef struct stats_aux {
427 u32 small_b1_failed; /* receive BD allocation failures */
428 u32 large_b1_failed; /* receive BD allocation failures */
429 u32 small_b2_failed; /* receive BD allocation failures */
430 u32 large_b2_failed; /* receive BD allocation failures */
431 u32 rpd_alloc_failed; /* receive PDU allocation failures */
432 u32 receive_carrier; /* no carrier = 0, carrier = 1 */
433 u32 pad[ 2 ]; /* i960 padding */
434 } stats_aux_t;
435
436
437 /* whole statistics buffer */
438
439 typedef struct stats {
440 struct stats_phy phy; /* physical encoding statistics */
441 struct stats_oc3 oc3; /* OC-3 statistics */
442 struct stats_atm atm; /* ATM statistics */
443 struct stats_aal0 aal0; /* AAL0 statistics */
444 struct stats_aal34 aal34; /* AAL3/4 statistics */
445 struct stats_aal5 aal5; /* AAL5 statistics */
446 struct stats_aux aux; /* auxiliary statistics */
447 } stats_t;
448
449
450 /* get statistics command opcode */
451
452 typedef struct stats_opcode {
453 BITFIELD2(
454 enum opcode opcode : 8, /* cp opcode */
455 u32 pad : 24 /* reserved */
456 )
457 } stats_opcode_t;
458
459
460 /* get statistics command block */
461
462 typedef struct stats_block {
463 struct stats_opcode opcode; /* get statistics command opcode */
464 u32 stats_haddr; /* host DMA address of stats buffer */
465 } stats_block_t;
466
467
468 /* expansion PROM data (PCI specific) */
469
470 typedef struct prom_data {
471 u32 hw_revision; /* hardware revision */
472 u32 serial_number; /* board serial number */
473 u8 mac_addr[ 8 ]; /* board MAC address */
474 } prom_data_t;
475
476
477 /* get expansion PROM data command opcode */
478
479 typedef struct prom_opcode {
480 BITFIELD2(
481 enum opcode opcode : 8, /* cp opcode */
482 u32 pad : 24 /* reserved */
483 )
484 } prom_opcode_t;
485
486
487 /* get expansion PROM data command block */
488
489 typedef struct prom_block {
490 struct prom_opcode opcode; /* get PROM data command opcode */
491 u32 prom_haddr; /* host DMA address of PROM buffer */
492 } prom_block_t;
493
494
495 /* cp command */
496
497 typedef union cmd {
498 enum opcode opcode; /* operation code */
499 struct activate_block activate_block; /* activate VC */
500 struct deactivate_block deactivate_block; /* deactivate VC */
501 struct stats_block stats_block; /* get statistics */
502 struct prom_block prom_block; /* get expansion PROM data */
503 struct oc3_block oc3_block; /* get/set OC-3 registers */
504 u32 pad[ 4 ]; /* i960 padding */
505 } cmd_t;
506
507
508 /* cp resident command queue */
509
510 typedef struct cp_cmdq_entry {
511 union cmd cmd; /* command */
512 u32 status_haddr; /* host DMA address of completion status */
513 u32 pad[ 3 ]; /* i960 padding */
514 } cp_cmdq_entry_t;
515
516
517 /* host resident transmit queue entry */
518
519 typedef struct host_txq_entry {
520 struct cp_txq_entry* cp_entry; /* addr of cp resident tx queue entry */
521 enum status* status; /* addr of host resident status */
522 struct tpd* tpd; /* addr of transmit PDU descriptor */
523 u32 tpd_dma; /* DMA address of tpd */
524 struct sk_buff* skb; /* related skb */
525 struct atm_vcc* vcc; /* related vcc */
526 void* data; /* copy of misaligned data */
527 } host_txq_entry_t;
528
529
530 /* host resident receive queue entry */
531
532 typedef struct host_rxq_entry {
533 struct cp_rxq_entry* cp_entry; /* addr of cp resident rx queue entry */
534 enum status* status; /* addr of host resident status */
535 struct rpd* rpd; /* addr of receive PDU descriptor */
536 u32 rpd_dma; /* DMA address of rpd */
537 } host_rxq_entry_t;
538
539
540 /* host resident buffer supply queue entry */
541
542 typedef struct host_bsq_entry {
543 struct cp_bsq_entry* cp_entry; /* addr of cp resident buffer supply queue entry */
544 enum status* status; /* addr of host resident status */
545 struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */
546 u32 rbd_block_dma; /* DMA address od rdb */
547 } host_bsq_entry_t;
548
549
550 /* host resident command queue entry */
551
552 typedef struct host_cmdq_entry {
553 struct cp_cmdq_entry* cp_entry; /* addr of cp resident cmd queue entry */
554 enum status* status; /* addr of host resident status */
555 } host_cmdq_entry_t;
556
557
558 /* chunk of memory */
559
560 typedef struct chunk {
561 void* alloc_addr; /* base address of allocated chunk */
562 void* align_addr; /* base address of aligned chunk */
563 u32 dma_addr; /* DMA address of aligned chunk */
564 int direction; /* direction of DMA mapping */
565 u32 alloc_size; /* length of allocated chunk */
566 u32 align_size; /* length of aligned chunk */
567 } chunk_t;
568
569 #define dma_size align_size /* DMA useable size */
570
571
572 /* host resident receive buffer */
573
574 typedef struct buffer {
575 struct buffer* next; /* next receive buffer */
576 enum buffer_scheme scheme; /* buffer scheme */
577 enum buffer_magn magn; /* buffer magnitude */
578 struct chunk data; /* data buffer */
579 } buffer_t;
580
581
582 #if (BITS_PER_LONG == 32)
583 #define FORE200E_BUF2HDL(buffer) ((u32)(buffer))
584 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle))
585 #else /* deal with 64 bit pointers */
586 #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer)))
587 #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET))
588 #endif
589
590
591 /* host resident command queue */
592
593 typedef struct host_cmdq {
594 struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */
595 int head; /* head of cmd queue */
596 struct chunk status; /* array of completion status */
597 } host_cmdq_t;
598
599
600 /* host resident transmit queue */
601
602 typedef struct host_txq {
603 struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */
604 int head; /* head of tx queue */
605 struct chunk tpd; /* array of tpds */
606 struct chunk status; /* arry of completion status */
607 int txing; /* number of pending PDUs in tx queue */
608 } host_txq_t;
609
610
611 /* host resident receive queue */
612
613 typedef struct host_rxq {
614 struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */
615 int head; /* head of rx queue */
616 struct chunk rpd; /* array of rpds */
617 struct chunk status; /* array of completion status */
618 } host_rxq_t;
619
620
621 /* host resident buffer supply queues */
622
623 typedef struct host_bsq {
624 struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */
625 int head; /* head of buffer supply queue */
626 struct chunk rbd_block; /* array of rbds */
627 struct chunk status; /* array of completion status */
628 struct buffer* buffer; /* array of rx buffers */
629 int free; /* index of first free rx buffer */
630 volatile int count; /* count of supplied rx buffers */
631 } host_bsq_t;
632
633
634 /* header of the firmware image */
635
636 typedef struct fw_header {
637 u32 magic; /* magic number */
638 u32 version; /* firware version id */
639 u32 load_offset; /* fw load offset in board memory */
640 u32 start_offset; /* fw execution start address in board memory */
641 } fw_header_t;
642
643 #define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */
644
645
646 /* receive buffer supply queues scheme specification */
647
648 typedef struct bs_spec {
649 u32 queue_length; /* queue capacity */
650 u32 buffer_size; /* host buffer size */
651 u32 pool_size; /* number of rbds */
652 u32 supply_blksize; /* num of rbds in I/O block (multiple
653 of 4 between 4 and 124 inclusive) */
654 } bs_spec_t;
655
656
657 /* initialization command block (one-time command, not in cmd queue) */
658
659 typedef struct init_block {
660 enum opcode opcode; /* initialize command */
661 enum status status; /* related status word */
662 u32 receive_threshold; /* not used */
663 u32 num_connect; /* ATM connections */
664 u32 cmd_queue_len; /* length of command queue */
665 u32 tx_queue_len; /* length of transmit queue */
666 u32 rx_queue_len; /* length of receive queue */
667 u32 rsd_extension; /* number of extra 32 byte blocks */
668 u32 tsd_extension; /* number of extra 32 byte blocks */
669 u32 conless_vpvc; /* not used */
670 u32 pad[ 2 ]; /* force quad alignment */
671 struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */
672 } init_block_t;
673
674
675 typedef enum media_type {
676 MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */
677 MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */
678 MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */
679 MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */
680 MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */
681 } media_type_t;
682
683 #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4)
684
685
686 /* cp resident queues */
687
688 typedef struct cp_queues {
689 u32 cp_cmdq; /* command queue */
690 u32 cp_txq; /* transmit queue */
691 u32 cp_rxq; /* receive queue */
692 u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */
693 u32 imask; /* 1 enables cp to host interrupts */
694 u32 istat; /* 1 for interrupt posted */
695 u32 heap_base; /* offset form beginning of ram */
696 u32 heap_size; /* space available for queues */
697 u32 hlogger; /* non zero for host logging */
698 u32 heartbeat; /* cp heartbeat */
699 u32 fw_release; /* firmware version */
700 u32 mon960_release; /* i960 monitor version */
701 u32 tq_plen; /* transmit throughput measurements */
702 /* make sure the init block remains on a quad word boundary */
703 struct init_block init; /* one time cmd, not in cmd queue */
704 enum media_type media_type; /* media type id */
705 u32 oc3_revision; /* OC-3 revision number */
706 } cp_queues_t;
707
708
709 /* boot status */
710
711 typedef enum boot_status {
712 BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */
713 BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */
714 BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */
715 BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */
716 BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */
717 } boot_status_t;
718
719
720 /* software UART */
721
722 typedef struct soft_uart {
723 u32 send; /* write register */
724 u32 recv; /* read register */
725 } soft_uart_t;
726
727 #define FORE200E_CP_MONITOR_UART_FREE 0x00000000
728 #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000
729
730
731 /* i960 monitor */
732
733 typedef struct cp_monitor {
734 struct soft_uart soft_uart; /* software UART */
735 enum boot_status bstat; /* boot status */
736 u32 app_base; /* application base offset */
737 u32 mon_version; /* i960 monitor version */
738 } cp_monitor_t;
739
740
741 /* device state */
742
743 typedef enum fore200e_state {
744 FORE200E_STATE_BLANK, /* initial state */
745 FORE200E_STATE_REGISTER, /* device registered */
746 FORE200E_STATE_CONFIGURE, /* bus interface configured */
747 FORE200E_STATE_MAP, /* board space mapped in host memory */
748 FORE200E_STATE_RESET, /* board resetted */
749 FORE200E_STATE_LOAD_FW, /* firmware loaded */
750 FORE200E_STATE_START_FW, /* firmware started */
751 FORE200E_STATE_INITIALIZE, /* initialize command successful */
752 FORE200E_STATE_INIT_CMDQ, /* command queue initialized */
753 FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */
754 FORE200E_STATE_INIT_RXQ, /* receive queue initialized */
755 FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */
756 FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */
757 FORE200E_STATE_IRQ, /* host interrupt requested */
758 FORE200E_STATE_COMPLETE /* initialization completed */
759 } fore200e_state;
760
761
762 /* PCA-200E registers */
763
764 typedef struct fore200e_pca_regs {
765 volatile u32* hcr; /* address of host control register */
766 volatile u32* imr; /* address of host interrupt mask register */
767 volatile u32* psr; /* address of PCI specific register */
768 } fore200e_pca_regs_t;
769
770
771 /* SBA-200E registers */
772
773 typedef struct fore200e_sba_regs {
774 volatile u32* hcr; /* address of host control register */
775 volatile u32* bsr; /* address of burst transfer size register */
776 volatile u32* isr; /* address of interrupt level selection register */
777 } fore200e_sba_regs_t;
778
779
780 /* model-specific registers */
781
782 typedef union fore200e_regs {
783 struct fore200e_pca_regs pca; /* PCA-200E registers */
784 struct fore200e_sba_regs sba; /* SBA-200E registers */
785 } fore200e_regs;
786
787
788 struct fore200e;
789
790 /* bus-dependent data */
791
792 typedef struct fore200e_bus {
793 char* model_name; /* board model name */
794 char* proc_name; /* board name under /proc/atm */
795 int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */
796 int buffer_alignment; /* rx buffers DMA alignment requirement */
797 int status_alignment; /* status words DMA alignment requirement */
798 const unsigned char* fw_data; /* address of firmware data start */
799 const unsigned int* fw_size; /* address of firmware data size */
800 u32 (*read)(volatile u32*);
801 void (*write)(u32, volatile u32*);
802 u32 (*dma_map)(struct fore200e*, void*, int, int);
803 void (*dma_unmap)(struct fore200e*, u32, int, int);
804 void (*dma_sync)(struct fore200e*, u32, int, int);
805 int (*dma_chunk_alloc)(struct fore200e*, struct chunk*, int, int, int);
806 void (*dma_chunk_free)(struct fore200e*, struct chunk*);
807 struct fore200e* (*detect)(const struct fore200e_bus*, int);
808 int (*configure)(struct fore200e*);
809 int (*map)(struct fore200e*);
810 void (*reset)(struct fore200e*);
811 int (*prom_read)(struct fore200e*, struct prom_data*);
812 void (*unmap)(struct fore200e*);
813 void (*irq_enable)(struct fore200e*);
814 int (*irq_check)(struct fore200e*);
815 void (*irq_ack)(struct fore200e*);
816 int (*proc_read)(struct fore200e*, char*);
817 } fore200e_bus_t;
818
819
820 #if defined(CONFIG_ATM_FORE200E_SBA)
821 # if defined(CONFIG_ATM_FORE200E_PCA)
822 # if (PCI_DMA_BIDIRECTIONAL == SBUS_DMA_BIDIRECTIONAL) && \
823 (PCI_DMA_TODEVICE == SBUS_DMA_TODEVICE) && \
824 (PCI_DMA_FROMDEVICE == SBUS_DMA_FROMDEVICE)
825 # define FORE200E_DMA_BIDIRECTIONAL PCI_DMA_BIDIRECTIONAL
826 # define FORE200E_DMA_TODEVICE PCI_DMA_TODEVICE
827 # define FORE200E_DMA_FROMDEVICE PCI_DMA_FROMDEVICE
828 # else
829 /* in that case, we'll need to add an extra indirection, e.g.
830 fore200e->bus->dma_direction[ fore200e_dma_direction ] */
831 # error PCI and SBUS DMA direction flags have different values!
832 # endif
833 # else
834 # define FORE200E_DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
835 # define FORE200E_DMA_TODEVICE SBUS_DMA_TODEVICE
836 # define FORE200E_DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
837 # endif
838 #else
839 # ifndef CONFIG_ATM_FORE200E_PCA
840 # warning compiling the fore200e driver without any hardware support enabled!
841 # include <linux/pci.h>
842 # endif
843 # define FORE200E_DMA_BIDIRECTIONAL PCI_DMA_BIDIRECTIONAL
844 # define FORE200E_DMA_TODEVICE PCI_DMA_TODEVICE
845 # define FORE200E_DMA_FROMDEVICE PCI_DMA_FROMDEVICE
846 #endif
847
848
849 /* per-device data */
850
851 typedef struct fore200e {
852 struct fore200e* next; /* next device */
853 const struct fore200e_bus* bus; /* bus-dependent code and data */
854 union fore200e_regs regs; /* bus-dependent registers */
855 struct atm_dev* atm_dev; /* ATM device */
856
857 enum fore200e_state state; /* device state */
858
859 char name[16]; /* device name */
860 void* bus_dev; /* bus-specific kernel data */
861 int irq; /* irq number */
862 unsigned long phys_base; /* physical base address */
863 void* virt_base; /* virtual base address */
864
865 unsigned char esi[ ESI_LEN ]; /* end system identifier */
866
867 struct cp_monitor* cp_monitor; /* i960 monitor address */
868 struct cp_queues* cp_queues; /* cp resident queues */
869 struct host_cmdq host_cmdq; /* host resident cmd queue */
870 struct host_txq host_txq; /* host resident tx queue */
871 struct host_rxq host_rxq; /* host resident rx queue */
872 /* host resident buffer supply queues */
873 struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ];
874
875 u32 available_cell_rate; /* remaining pseudo-CBR bw on link */
876
877 int loop_mode; /* S/UNI loopback mode */
878
879 struct stats* stats; /* last snapshot of the stats */
880
881 struct semaphore rate_sf; /* protects rate reservation ops */
882 struct tasklet_struct tasklet; /* performs interrupt work */
883
884 } fore200e_t;
885
886
887 /* per-vcc data */
888
889 typedef struct fore200e_vcc {
890 enum buffer_scheme scheme; /* rx buffer scheme */
891 struct tpd_rate rate; /* tx rate control data */
892 int rx_min_pdu; /* size of smallest PDU received */
893 int rx_max_pdu; /* size of largest PDU received */
894 int tx_min_pdu; /* size of smallest PDU transmitted */
895 int tx_max_pdu; /* size of largest PDU transmitted */
896 } fore200e_vcc_t;
897
898
899
900 /* 200E-series common memory layout */
901
902 #define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */
903 #define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */
904
905
906 /* PCA-200E memory layout */
907
908 #define PCA200E_IOSPACE_LENGTH 0x00200000
909
910 #define PCA200E_HCR_OFFSET 0x00100000 /* board control register */
911 #define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */
912 #define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */
913
914
915 /* PCA-200E host control register */
916
917 #define PCA200E_HCR_RESET (1<<0) /* read / write */
918 #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */
919 #define PCA200E_HCR_I960FAIL (1<<2) /* read */
920 #define PCA200E_HCR_INTRB (1<<2) /* write */
921 #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */
922 #define PCA200E_HCR_INTRA (1<<3) /* write */
923 #define PCA200E_HCR_OUTFULL (1<<4) /* read */
924 #define PCA200E_HCR_CLRINTR (1<<4) /* write */
925 #define PCA200E_HCR_ESPHOLD (1<<5) /* read */
926 #define PCA200E_HCR_INFULL (1<<6) /* read */
927 #define PCA200E_HCR_TESTMODE (1<<7) /* read */
928
929
930 /* PCA-200E PCI bus interface regs (offsets in PCI config space) */
931
932 #define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */
933 #define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */
934 #define PCA200E_PCI_THRESHOLD 0x42 /* burst / continous req threshold */
935
936 /* PBI master control register */
937
938 #define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */
939 #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */
940 #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */
941 #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */
942 #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */
943 #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */
944 #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */
945
946
947
948 #define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */
949
950
951 /* size of SBA-200E registers */
952
953 #define SBA200E_HCR_LENGTH 4
954 #define SBA200E_BSR_LENGTH 4
955 #define SBA200E_ISR_LENGTH 4
956 #define SBA200E_RAM_LENGTH 0x40000
957
958
959 /* SBA-200E SBUS burst transfer size register */
960
961 #define SBA200E_BSR_BURST4 0x04
962 #define SBA200E_BSR_BURST8 0x08
963 #define SBA200E_BSR_BURST16 0x10
964
965
966 /* SBA-200E host control register */
967
968 #define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */
969 #define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */
970 #define SBA200E_HCR_I960FAIL (1<<2) /* read */
971 #define SBA200E_HCR_I960SETINTR (1<<2) /* write */
972 #define SBA200E_HCR_OUTFULL (1<<3) /* read */
973 #define SBA200E_HCR_INTR_CLR (1<<3) /* write */
974 #define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */
975 #define SBA200E_HCR_ESPHOLD (1<<5) /* read */
976 #define SBA200E_HCR_INFULL (1<<6) /* read */
977 #define SBA200E_HCR_TESTMODE (1<<7) /* read */
978 #define SBA200E_HCR_INTR_REQ (1<<8) /* read */
979
980 #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA)
981
982
983 #endif /* __KERNEL__ */
984 #endif /* _FORE200E_H */
985
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