1 #ifndef CCISS_H
2 #define CCISS_H
3
4 #include <linux/genhd.h>
5
6 #include "cciss_cmd.h"
7
8
9 #define NWD 16
10 #define NWD_SHIFT 4
11 #define MAX_PART 16
12
13 #define IO_OK 0
14 #define IO_ERROR 1
15
16 #define MAJOR_NR COMPAQ_CISS_MAJOR
17
18 struct ctlr_info;
19 typedef struct ctlr_info ctlr_info_t;
20
21 struct access_method {
22 void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
23 void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
24 unsigned long (*fifo_full)(ctlr_info_t *h);
25 unsigned long (*intr_pending)(ctlr_info_t *h);
26 unsigned long (*command_completed)(ctlr_info_t *h);
27 };
28 typedef struct _drive_info_struct
29 {
30 __u32 LunID;
31 int usage_count;
32 int nr_blocks;
33 int block_size;
34 int heads;
35 int sectors;
36 int cylinders;
37 } drive_info_struct;
38
39 struct ctlr_info
40 {
41 int ctlr;
42 char devname[8];
43 char *product_name;
44 char firm_ver[4]; // Firmware version
45 unchar pci_bus;
46 unchar pci_dev_fn;
47 __u32 board_id;
48 ulong vaddr;
49 __u32 paddr;
50 CfgTable_struct *cfgtable;
51 int intr;
52
53 int max_commands;
54 int commands_outstanding;
55 int max_outstanding; /* Debug */
56 int num_luns;
57 int usage_count; /* number of opens all all minor devices */
58
59 // information about each logical volume
60 drive_info_struct drv[CISS_MAX_LUN];
61
62 struct access_method access;
63
64 /* queue and queue Info */
65 CommandList_struct *reqQ;
66 CommandList_struct *cmpQ;
67 unsigned int Qdepth;
68 unsigned int maxQsinceinit;
69 unsigned int maxSG;
70
71 //* pointers to command and error info pool */
72 CommandList_struct *cmd_pool;
73 ErrorInfo_struct *errinfo_pool;
74 __u32 *cmd_pool_bits;
75 int nr_allocs;
76 int nr_frees;
77
78 // Disk structures we need to pass back
79 struct gendisk gendisk;
80 // indexed by minor numbers
81 struct hd_struct hd[256];
82 int sizes[256];
83 int blocksizes[256];
84 int hardsizes[256];
85 };
86
87 /* Defining the diffent access_menthods */
88 /*
89 * Memory mapped FIFO interface (SMART 53xx cards)
90 */
91 #define SA5_DOORBELL 0x20
92 #define SA5_REQUEST_PORT_OFFSET 0x40
93 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
94 #define SA5_REPLY_PORT_OFFSET 0x44
95 #define SA5_INTR_STATUS 0x30
96
97 #define SA5_INTR_OFF 0x08
98 #define SA5_INTR_PENDING 0x08
99 #define FIFO_EMPTY 0xffffffff
100
101 #define CISS_ERROR_BIT 0x02
102
103 #define CCISS_INTR_ON 1
104 #define CCISS_INTR_OFF 0
105 /*
106 Send the command to the hardware
107 */
108 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
109 {
110 #ifdef CCISS_DEBUG
111 printk("Sending %x - down to controller\n", c->busaddr );
112 #endif /* CCISS_DEBUG */
113 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
114 h->commands_outstanding++;
115 if ( h->commands_outstanding > h->max_outstanding)
116 h->max_outstanding = h->commands_outstanding;
117 }
118
119 /*
120 * This card is the oposite of the other cards.
121 * 0 turns interrupts on...
122 * 0x08 turns them off...
123 */
124 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
125 {
126 if (val)
127 { /* Turn interrupts on */
128 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
129 } else /* Turn them off */
130 {
131 writel( SA5_INTR_OFF,
132 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
133 }
134 }
135 /*
136 * Returns true if fifo is full.
137 *
138 */
139 static unsigned long SA5_fifo_full(ctlr_info_t *h)
140 {
141 if( h->commands_outstanding >= h->max_commands)
142 return(1);
143 else
144 return(0);
145
146 }
147 /*
148 * returns value read from hardware.
149 * returns FIFO_EMPTY if there is nothing to read
150 */
151 static unsigned long SA5_completed(ctlr_info_t *h)
152 {
153 unsigned long register_value
154 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
155 if(register_value != FIFO_EMPTY)
156 {
157 h->commands_outstanding--;
158 #ifdef CCISS_DEBUG
159 printk("cciss: Read %lx back from board\n", register_value);
160 #endif /* CCISS_DEBUG */
161 }
162 #ifdef CCISS_DEBUG
163 else
164 {
165 printk("cciss: FIFO Empty read\n");
166 }
167 #endif
168 return ( register_value);
169
170 }
171 /*
172 * Returns true if an interrupt is pending..
173 */
174 static unsigned long SA5_intr_pending(ctlr_info_t *h)
175 {
176 unsigned long register_value =
177 readl(h->vaddr + SA5_INTR_STATUS);
178 #ifdef CCISS_DEBUG
179 printk("cciss: intr_pending %lx\n", register_value);
180 #endif /* CCISS_DEBUG */
181 if( register_value & SA5_INTR_PENDING)
182 return 1;
183 return 0 ;
184 }
185
186
187 static struct access_method SA5_access = {
188 SA5_submit_command,
189 SA5_intr_mask,
190 SA5_fifo_full,
191 SA5_intr_pending,
192 SA5_completed,
193 };
194
195 struct board_type {
196 __u32 board_id;
197 char *product_name;
198 struct access_method *access;
199 };
200 #endif /* CCISS_H */
201
202
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.