1 /* $Id: sh-sci.h,v 1.8 2000/03/08 15:19:39 gniibe Exp $
2 *
3 * linux/drivers/char/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
9 *
10 */
11 #include <linux/config.h>
12
13 /* Values for sci_port->type */
14 #define PORT_SCI 0
15 #define PORT_SCIF 1
16 #define PORT_IRDA 1 /* XXX: temporary assignment */
17
18 /* Offsets into the sci_port->irqs array */
19 #define SCIx_ERI_IRQ 0
20 #define SCIx_RXI_IRQ 1
21 #define SCIx_TXI_IRQ 2
22
23 /* ERI, RXI, TXI, BRI */
24 #define SCI_IRQS { 23, 24, 25, 0 }
25 #define SH3_SCIF_IRQS { 56, 57, 59, 58 }
26 #define SH3_IRDA_IRQS { 52, 53, 55, 54 }
27 #define SH4_SCIF_IRQS { 40, 41, 43, 42 }
28
29 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
30 # define SCI_NPORTS 1
31 # define SCI_INIT { \
32 { {}, PORT_SCI, 0xfffffe80, SCI_IRQS, sci_init_pins_sci } \
33 }
34 # define SCSPTR 0xffffff7c /* 8 bit */
35 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
36 # define SCI_ONLY
37 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
38 # define SCI_NPORTS 3
39 # define SCI_INIT { \
40 { {}, PORT_SCI, 0xfffffe80, SCI_IRQS, sci_init_pins_sci }, \
41 { {}, PORT_SCIF, 0xA4000150, SH3_SCIF_IRQS, sci_init_pins_scif }, \
42 { {}, PORT_SCIF, 0xA4000140, SH3_IRDA_IRQS, sci_init_pins_irda } \
43 }
44 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
45 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
46 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
47 # define SCI_AND_SCIF
48 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
49 # define SCI_NPORTS 2
50 # define SCI_INIT { \
51 { {}, PORT_SCI, 0xffe00000, SCI_IRQS, sci_init_pins_sci }, \
52 { {}, PORT_SCIF, 0xFFE80000, SH4_SCIF_IRQS, sci_init_pins_scif } \
53 }
54 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56 # define SCLSR2 0xFFE80024 /* 16 bit SCIF */
57 # define SCIF_ORER 0x0001 /* overrun error bit */
58 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
59 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
60 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
61 # define SCI_AND_SCIF
62 #else
63 # error CPU subtype not defined
64 #endif
65
66 /* SCSCR */
67 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
68 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
69 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
70 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
71 /* SCI_CTRL_FLAGS_REIE 0x08 * 7750 SCIF */
72 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
73 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
74 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
75 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
76
77 /* SCxSR SCI */
78 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
79 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
80 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
81 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
82 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
83 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
84 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
85 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
86
87 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
88
89 /* SCxSR SCIF */
90 #define SCIF_ER 0x0080 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
91 #define SCIF_TEND 0x0040 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
92 #define SCIF_TDFE 0x0020 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
93 #define SCIF_BRK 0x0010 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
94 #define SCIF_FER 0x0008 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
95 #define SCIF_PER 0x0004 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
96 #define SCIF_RDF 0x0002 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
97 #define SCIF_DR 0x0001 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
98
99 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
100
101 #if defined(SCI_ONLY)
102 # define SCxSR_TEND(port) SCI_TEND
103 # define SCxSR_ERRORS(port) SCI_ERRORS
104 # define SCxSR_RDxF(port) SCI_RDRF
105 # define SCxSR_TDxE(port) SCI_TDRE
106 # define SCxSR_ORER(port) SCI_ORER
107 # define SCxSR_FER(port) SCI_FER
108 # define SCxSR_PER(port) SCI_PER
109 # define SCxSR_BRK(port) 0x00
110 # define SCxSR_RDxF_CLEAR(port) 0xbc
111 # define SCxSR_ERROR_CLEAR(port) 0xc4
112 # define SCxSR_TDxE_CLEAR(port) 0x78
113 # define SCxSR_BREAK_CLEAR(port) 0xc4
114 #elif defined(SCIF_ONLY)
115 # define SCxSR_TEND(port) SCIF_TEND
116 # define SCxSR_ERRORS(port) SCIF_ERRORS
117 # define SCxSR_RDxF(port) SCIF_RDF
118 # define SCxSR_TDxE(port) SCIF_TDFE
119 # define SCxSR_ORER(port) 0x0000
120 # define SCxSR_FER(port) SCIF_FER
121 # define SCxSR_PER(port) SCIF_PER
122 # define SCxSR_BRK(port) SCIF_BRK
123 # define SCxSR_RDxF_CLEAR(port) 0x00fc
124 # define SCxSR_ERROR_CLEAR(port) 0x0073
125 # define SCxSR_TDxE_CLEAR(port) 0x00df
126 # define SCxSR_BREAK_CLEAR(port) 0x00e3
127 #else
128 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
129 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
130 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
131 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
132 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
133 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
134 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
135 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
136 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
137 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
138 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
139 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
140 #endif
141
142 /* SCFCR */
143 #define SCFCR_RFRST 0x0002
144 #define SCFCR_TFRST 0x0004
145 #define SCFCR_MCE 0x0008
146
147 #define SCI_MAJOR 204
148 #define SCI_MINOR_START 8
149
150 /* Generic serial flags */
151 #define SCI_RX_THROTTLE 0x0000001
152
153 /* generic serial tty */
154 #define O_OTHER(tty) \
155 ((O_OLCUC(tty)) ||\
156 (O_ONLCR(tty)) ||\
157 (O_OCRNL(tty)) ||\
158 (O_ONOCR(tty)) ||\
159 (O_ONLRET(tty)) ||\
160 (O_OFILL(tty)) ||\
161 (O_OFDEL(tty)) ||\
162 (O_NLDLY(tty)) ||\
163 (O_CRDLY(tty)) ||\
164 (O_TABDLY(tty)) ||\
165 (O_BSDLY(tty)) ||\
166 (O_VTDLY(tty)) ||\
167 (O_FFDLY(tty)))
168
169 #define I_OTHER(tty) \
170 ((I_INLCR(tty)) ||\
171 (I_IGNCR(tty)) ||\
172 (I_ICRNL(tty)) ||\
173 (I_IUCLC(tty)) ||\
174 (L_ISIG(tty)))
175
176 #define SCI_MAGIC 0xbabeface
177
178 /*
179 * Events are used to schedule things to happen at timer-interrupt
180 * time, instead of at rs interrupt time.
181 */
182 #define SCI_EVENT_WRITE_WAKEUP 0
183
184 struct sci_port {
185 struct gs_port gs;
186 int type;
187 unsigned int base;
188 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
189 void (*init_pins)(struct sci_port* port, unsigned int cflag);
190 unsigned int old_cflag;
191 struct async_icount icount;
192 struct tq_struct tqueue;
193 unsigned long event;
194 };
195
196 #define SCI_IN(size, offset) \
197 unsigned int addr = port->base + (offset); \
198 if ((size) == 8) { \
199 return ctrl_inb(addr); \
200 } else { \
201 return ctrl_inw(addr); \
202 }
203 #define SCI_OUT(size, offset, value) \
204 unsigned int addr = port->base + (offset); \
205 if ((size) == 8) { \
206 ctrl_outb(value, addr); \
207 } else { \
208 ctrl_outw(value, addr); \
209 }
210
211 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
212 static inline unsigned int sci_##name##_in(struct sci_port* port) \
213 { \
214 if (port->type == PORT_SCI) { \
215 SCI_IN(sci_size, sci_offset) \
216 } else { \
217 SCI_IN(scif_size, scif_offset); \
218 } \
219 } \
220 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
221 { \
222 if (port->type == PORT_SCI) { \
223 SCI_OUT(sci_size, sci_offset, value) \
224 } else { \
225 SCI_OUT(scif_size, scif_offset, value); \
226 } \
227 }
228
229 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
230 static inline unsigned int sci_##name##_in(struct sci_port* port) \
231 { \
232 SCI_IN(scif_size, scif_offset); \
233 } \
234 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
235 { \
236 SCI_OUT(scif_size, scif_offset, value); \
237 }
238
239 #ifdef __sh3__
240 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
241 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
242 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
243 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
244 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
245 #else
246 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
247 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
248 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
249 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
250 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
251 #endif
252
253 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 */
254 /* name off sz off sz off sz off sz */
255 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16)
256 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8)
257 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16)
258 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8)
259 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16)
260 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8)
261 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
262 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
263
264 #define sci_in(port, reg) sci_##reg##_in(port)
265 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
266
267 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
268 static inline int sci_rxd_in(struct sci_port *port)
269 {
270 if (port->base == 0xfffffe80)
271 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
272 return 1;
273 }
274 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
275 static inline int sci_rxd_in(struct sci_port *port)
276 {
277 if (port->base == 0xfffffe80)
278 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
279 if (port->base == 0xa4000150)
280 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
281 if (port->base == 0xa4000140)
282 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
283 return 1;
284 }
285 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
286 static inline int sci_rxd_in(struct sci_port *port)
287 {
288 if (port->base == 0xffe00000)
289 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
290 if (port->base == 0xffe80000)
291 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
292 return 1;
293 }
294 #endif
295
296 /*
297 * Values for the BitRate Register (SCBRR)
298 *
299 * The values are actually divisors for a frequency which can
300 * be internal to the SH3 (14.7456MHz) or derived from an external
301 * clock source. This driver assumes the internal clock is used;
302 * to support using an external clock source, config options or
303 * possibly command-line options would need to be added.
304 *
305 * Also, to support speeds below 2400 (why?) the lower 2 bits of
306 * the SCSMR register would also need to be set to non-zero values.
307 *
308 * -- Greg Banks 27Feb2000
309 *
310 * Answer: The SCBRR register is only eight bits, and the value in
311 * it gets larger with lower baud rates. At around 2400 (depending on
312 * the peripherial module clock) you run out of bits. However the
313 * lower two bits of SCSMR allow the module clock to be divided down,
314 * scaling the value which is needed in SCBRR.
315 *
316 * -- Stuart Menefy - 23 May 2000
317 *
318 * I meant, why would anyone bother with bitrates below 2400.
319 *
320 * -- Greg Banks - 7Jul2000
321 *
322 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
323 * tape reader as a console!
324 *
325 * -- Mitch Davis - 15 Jul 2000
326 */
327
328 #define PCLK (current_cpu_data.module_clock)
329
330 #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
331 #define BPS_2400 SCBRR_VALUE(2400)
332 #define BPS_4800 SCBRR_VALUE(4800)
333 #define BPS_9600 SCBRR_VALUE(9600)
334 #define BPS_19200 SCBRR_VALUE(19200)
335 #define BPS_38400 SCBRR_VALUE(38400)
336 #define BPS_57600 SCBRR_VALUE(57600)
337 #define BPS_115200 SCBRR_VALUE(115200)
338
339
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