1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 3.2 2000/11/06 22:34:38 paul Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
57 #define BREAKPOINT() asm(" int $3");
58
59 #define MAX_ISA_DEVICES 10
60 #define MAX_PCI_DEVICES 10
61 #define MAX_TOTAL_DEVICES 20
62
63 #include <linux/config.h>
64 #include <linux/module.h>
65 #include <linux/version.h>
66 #include <linux/errno.h>
67 #include <linux/signal.h>
68 #include <linux/sched.h>
69 #include <linux/timer.h>
70 #include <linux/interrupt.h>
71 #include <linux/pci.h>
72 #include <linux/tty.h>
73 #include <linux/tty_flip.h>
74 #include <linux/serial.h>
75 #include <linux/major.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/ioport.h>
80 #include <linux/mm.h>
81 #include <linux/malloc.h>
82
83 #include <linux/netdevice.h>
84
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <asm/serial.h>
88
89 #include <linux/delay.h>
90 #include <linux/ioctl.h>
91
92 #include <asm/system.h>
93 #include <asm/io.h>
94 #include <asm/irq.h>
95 #include <asm/dma.h>
96 #include <asm/bitops.h>
97 #include <asm/types.h>
98 #include <linux/termios.h>
99 #include <linux/tqueue.h>
100
101 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
102 #define CONFIG_SYNCLINK_SYNCPPP 1
103 #endif
104
105 #ifdef CONFIG_SYNCLINK_SYNCPPP
106 #include "../net/wan/syncppp.h"
107 #endif
108
109 #include <asm/segment.h>
110 #define GET_USER(error,value,addr) error = get_user(value,addr)
111 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
112 #define PUT_USER(error,value,addr) error = put_user(value,addr)
113 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
114
115 #include <asm/uaccess.h>
116
117 #include "linux/synclink.h"
118
119 #define RCLRVALUE 0xffff
120
121 MGSL_PARAMS default_params = {
122 MGSL_MODE_HDLC, /* unsigned long mode */
123 0, /* unsigned char loopback; */
124 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
125 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
126 0, /* unsigned long clock_speed; */
127 0xff, /* unsigned char addr_filter; */
128 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
129 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
130 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
131 9600, /* unsigned long data_rate; */
132 8, /* unsigned char data_bits; */
133 1, /* unsigned char stop_bits; */
134 ASYNC_PARITY_NONE /* unsigned char parity; */
135 };
136
137 #define SHARED_MEM_ADDRESS_SIZE 0x40000
138 #define BUFFERLISTSIZE (PAGE_SIZE)
139 #define DMABUFFERSIZE (PAGE_SIZE)
140 #define MAXRXFRAMES 7
141
142 typedef struct _DMABUFFERENTRY
143 {
144 u32 phys_addr; /* 32-bit flat physical address of data buffer */
145 u16 count; /* buffer size/data count */
146 u16 status; /* Control/status field */
147 u16 rcc; /* character count field */
148 u16 reserved; /* padding required by 16C32 */
149 u32 link; /* 32-bit flat link to next buffer entry */
150 char *virt_addr; /* virtual address of data buffer */
151 u32 phys_entry; /* physical address of this buffer entry */
152 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
153
154 /* The queue of BH actions to be performed */
155
156 #define BH_RECEIVE 1
157 #define BH_TRANSMIT 2
158 #define BH_STATUS 4
159
160 #define IO_PIN_SHUTDOWN_LIMIT 100
161
162 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
163
164 struct _input_signal_events {
165 int ri_up;
166 int ri_down;
167 int dsr_up;
168 int dsr_down;
169 int dcd_up;
170 int dcd_down;
171 int cts_up;
172 int cts_down;
173 };
174
175 /*
176 * Device instance data structure
177 */
178
179 struct mgsl_struct {
180 void *if_ptr; /* General purpose pointer (used by SPPP) */
181 int magic;
182 int flags;
183 int count; /* count of opens */
184 int line;
185 unsigned short close_delay;
186 unsigned short closing_wait; /* time to wait before closing */
187
188 struct mgsl_icount icount;
189
190 struct termios normal_termios;
191 struct termios callout_termios;
192
193 struct tty_struct *tty;
194 int timeout;
195 int x_char; /* xon/xoff character */
196 int blocked_open; /* # of blocked opens */
197 long session; /* Session of opening process */
198 long pgrp; /* pgrp of opening process */
199 u16 read_status_mask;
200 u16 ignore_status_mask;
201 unsigned char *xmit_buf;
202 int xmit_head;
203 int xmit_tail;
204 int xmit_cnt;
205
206 wait_queue_head_t open_wait;
207 wait_queue_head_t close_wait;
208
209 wait_queue_head_t status_event_wait_q;
210 wait_queue_head_t event_wait_q;
211 struct timer_list tx_timer; /* HDLC transmit timeout timer */
212 struct mgsl_struct *next_device; /* device list link */
213
214 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
215 struct tq_struct task; /* task structure for scheduling bh */
216
217 u32 EventMask; /* event trigger mask */
218 u32 RecordedEvents; /* pending events */
219
220 u32 max_frame_size; /* as set by device config */
221
222 u32 pending_bh;
223
224 int bh_running; /* Protection from multiple */
225 int isr_overflow;
226 int bh_requested;
227
228 int dcd_chkcount; /* check counts to prevent */
229 int cts_chkcount; /* too many IRQs if a signal */
230 int dsr_chkcount; /* is floating */
231 int ri_chkcount;
232
233 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
234 unsigned long buffer_list_phys;
235
236 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
237 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
238 unsigned int current_rx_buffer;
239
240 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
241 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
242
243 unsigned char *intermediate_rxbuffer;
244
245 int rx_enabled;
246 int rx_overflow;
247
248 int tx_enabled;
249 int tx_active;
250 u32 idle_mode;
251
252 u16 cmr_value;
253 u16 tcsr_value;
254
255 char device_name[25]; /* device instance name */
256
257 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
258 unsigned char bus; /* expansion bus number (zero based) */
259 unsigned char function; /* PCI device number */
260
261 unsigned int io_base; /* base I/O address of adapter */
262 unsigned int io_addr_size; /* size of the I/O address range */
263 int io_addr_requested; /* nonzero if I/O address requested */
264
265 unsigned int irq_level; /* interrupt level */
266 unsigned long irq_flags;
267 int irq_requested; /* nonzero if IRQ requested */
268
269 unsigned int dma_level; /* DMA channel */
270 int dma_requested; /* nonzero if dma channel requested */
271
272 u16 mbre_bit;
273 u16 loopback_bits;
274 u16 usc_idle_mode;
275
276 MGSL_PARAMS params; /* communications parameters */
277
278 unsigned char serial_signals; /* current serial signal states */
279
280 int irq_occurred; /* for diagnostics use */
281 unsigned int init_error; /* Initialization startup error (DIAGS) */
282 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
283
284 u32 last_mem_alloc;
285 unsigned char* memory_base; /* shared memory address (PCI only) */
286 u32 phys_memory_base;
287 int shared_mem_requested;
288
289 unsigned char* lcr_base; /* local config registers (PCI only) */
290 u32 phys_lcr_base;
291 u32 lcr_offset;
292 int lcr_mem_requested;
293
294 u32 misc_ctrl_value;
295 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
296 char char_buf[MAX_ASYNC_BUFFER_SIZE];
297 BOOLEAN drop_rts_on_tx_done;
298
299 BOOLEAN loopmode_insert_requested;
300 BOOLEAN loopmode_send_done_requested;
301
302 struct _input_signal_events input_signal_events;
303
304 /* SPPP/Cisco HDLC device parts */
305 int netcount;
306 int dosyncppp;
307 spinlock_t netlock;
308 #ifdef CONFIG_SYNCLINK_SYNCPPP
309 struct ppp_device pppdev;
310 char netname[10];
311 struct net_device *netdev;
312 struct net_device_stats netstats;
313 struct net_device netdevice;
314 #endif
315 };
316
317 #define MGSL_MAGIC 0x5401
318
319 /*
320 * The size of the serial xmit buffer is 1 page, or 4096 bytes
321 */
322 #ifndef SERIAL_XMIT_SIZE
323 #define SERIAL_XMIT_SIZE 4096
324 #endif
325
326 /*
327 * These macros define the offsets used in calculating the
328 * I/O address of the specified USC registers.
329 */
330
331
332 #define DCPIN 2 /* Bit 1 of I/O address */
333 #define SDPIN 4 /* Bit 2 of I/O address */
334
335 #define DCAR 0 /* DMA command/address register */
336 #define CCAR SDPIN /* channel command/address register */
337 #define DATAREG DCPIN + SDPIN /* serial data register */
338 #define MSBONLY 0x41
339 #define LSBONLY 0x40
340
341 /*
342 * These macros define the register address (ordinal number)
343 * used for writing address/value pairs to the USC.
344 */
345
346 #define CMR 0x02 /* Channel mode Register */
347 #define CCSR 0x04 /* Channel Command/status Register */
348 #define CCR 0x06 /* Channel Control Register */
349 #define PSR 0x08 /* Port status Register */
350 #define PCR 0x0a /* Port Control Register */
351 #define TMDR 0x0c /* Test mode Data Register */
352 #define TMCR 0x0e /* Test mode Control Register */
353 #define CMCR 0x10 /* Clock mode Control Register */
354 #define HCR 0x12 /* Hardware Configuration Register */
355 #define IVR 0x14 /* Interrupt Vector Register */
356 #define IOCR 0x16 /* Input/Output Control Register */
357 #define ICR 0x18 /* Interrupt Control Register */
358 #define DCCR 0x1a /* Daisy Chain Control Register */
359 #define MISR 0x1c /* Misc Interrupt status Register */
360 #define SICR 0x1e /* status Interrupt Control Register */
361 #define RDR 0x20 /* Receive Data Register */
362 #define RMR 0x22 /* Receive mode Register */
363 #define RCSR 0x24 /* Receive Command/status Register */
364 #define RICR 0x26 /* Receive Interrupt Control Register */
365 #define RSR 0x28 /* Receive Sync Register */
366 #define RCLR 0x2a /* Receive count Limit Register */
367 #define RCCR 0x2c /* Receive Character count Register */
368 #define TC0R 0x2e /* Time Constant 0 Register */
369 #define TDR 0x30 /* Transmit Data Register */
370 #define TMR 0x32 /* Transmit mode Register */
371 #define TCSR 0x34 /* Transmit Command/status Register */
372 #define TICR 0x36 /* Transmit Interrupt Control Register */
373 #define TSR 0x38 /* Transmit Sync Register */
374 #define TCLR 0x3a /* Transmit count Limit Register */
375 #define TCCR 0x3c /* Transmit Character count Register */
376 #define TC1R 0x3e /* Time Constant 1 Register */
377
378
379 /*
380 * MACRO DEFINITIONS FOR DMA REGISTERS
381 */
382
383 #define DCR 0x06 /* DMA Control Register (shared) */
384 #define DACR 0x08 /* DMA Array count Register (shared) */
385 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
386 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
387 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
388 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
389 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
390
391 #define TDMR 0x02 /* Transmit DMA mode Register */
392 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
393 #define TBCR 0x2a /* Transmit Byte count Register */
394 #define TARL 0x2c /* Transmit Address Register (low) */
395 #define TARU 0x2e /* Transmit Address Register (high) */
396 #define NTBCR 0x3a /* Next Transmit Byte count Register */
397 #define NTARL 0x3c /* Next Transmit Address Register (low) */
398 #define NTARU 0x3e /* Next Transmit Address Register (high) */
399
400 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
401 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
402 #define RBCR 0xaa /* Receive Byte count Register */
403 #define RARL 0xac /* Receive Address Register (low) */
404 #define RARU 0xae /* Receive Address Register (high) */
405 #define NRBCR 0xba /* Next Receive Byte count Register */
406 #define NRARL 0xbc /* Next Receive Address Register (low) */
407 #define NRARU 0xbe /* Next Receive Address Register (high) */
408
409
410 /*
411 * MACRO DEFINITIONS FOR MODEM STATUS BITS
412 */
413
414 #define MODEMSTATUS_DTR 0x80
415 #define MODEMSTATUS_DSR 0x40
416 #define MODEMSTATUS_RTS 0x20
417 #define MODEMSTATUS_CTS 0x10
418 #define MODEMSTATUS_RI 0x04
419 #define MODEMSTATUS_DCD 0x01
420
421
422 /*
423 * Channel Command/Address Register (CCAR) Command Codes
424 */
425
426 #define RTCmd_Null 0x0000
427 #define RTCmd_ResetHighestIus 0x1000
428 #define RTCmd_TriggerChannelLoadDma 0x2000
429 #define RTCmd_TriggerRxDma 0x2800
430 #define RTCmd_TriggerTxDma 0x3000
431 #define RTCmd_TriggerRxAndTxDma 0x3800
432 #define RTCmd_PurgeRxFifo 0x4800
433 #define RTCmd_PurgeTxFifo 0x5000
434 #define RTCmd_PurgeRxAndTxFifo 0x5800
435 #define RTCmd_LoadRcc 0x6800
436 #define RTCmd_LoadTcc 0x7000
437 #define RTCmd_LoadRccAndTcc 0x7800
438 #define RTCmd_LoadTC0 0x8800
439 #define RTCmd_LoadTC1 0x9000
440 #define RTCmd_LoadTC0AndTC1 0x9800
441 #define RTCmd_SerialDataLSBFirst 0xa000
442 #define RTCmd_SerialDataMSBFirst 0xa800
443 #define RTCmd_SelectBigEndian 0xb000
444 #define RTCmd_SelectLittleEndian 0xb800
445
446
447 /*
448 * DMA Command/Address Register (DCAR) Command Codes
449 */
450
451 #define DmaCmd_Null 0x0000
452 #define DmaCmd_ResetTxChannel 0x1000
453 #define DmaCmd_ResetRxChannel 0x1200
454 #define DmaCmd_StartTxChannel 0x2000
455 #define DmaCmd_StartRxChannel 0x2200
456 #define DmaCmd_ContinueTxChannel 0x3000
457 #define DmaCmd_ContinueRxChannel 0x3200
458 #define DmaCmd_PauseTxChannel 0x4000
459 #define DmaCmd_PauseRxChannel 0x4200
460 #define DmaCmd_AbortTxChannel 0x5000
461 #define DmaCmd_AbortRxChannel 0x5200
462 #define DmaCmd_InitTxChannel 0x7000
463 #define DmaCmd_InitRxChannel 0x7200
464 #define DmaCmd_ResetHighestDmaIus 0x8000
465 #define DmaCmd_ResetAllChannels 0x9000
466 #define DmaCmd_StartAllChannels 0xa000
467 #define DmaCmd_ContinueAllChannels 0xb000
468 #define DmaCmd_PauseAllChannels 0xc000
469 #define DmaCmd_AbortAllChannels 0xd000
470 #define DmaCmd_InitAllChannels 0xf000
471
472 #define TCmd_Null 0x0000
473 #define TCmd_ClearTxCRC 0x2000
474 #define TCmd_SelectTicrTtsaData 0x4000
475 #define TCmd_SelectTicrTxFifostatus 0x5000
476 #define TCmd_SelectTicrIntLevel 0x6000
477 #define TCmd_SelectTicrdma_level 0x7000
478 #define TCmd_SendFrame 0x8000
479 #define TCmd_SendAbort 0x9000
480 #define TCmd_EnableDleInsertion 0xc000
481 #define TCmd_DisableDleInsertion 0xd000
482 #define TCmd_ClearEofEom 0xe000
483 #define TCmd_SetEofEom 0xf000
484
485 #define RCmd_Null 0x0000
486 #define RCmd_ClearRxCRC 0x2000
487 #define RCmd_EnterHuntmode 0x3000
488 #define RCmd_SelectRicrRtsaData 0x4000
489 #define RCmd_SelectRicrRxFifostatus 0x5000
490 #define RCmd_SelectRicrIntLevel 0x6000
491 #define RCmd_SelectRicrdma_level 0x7000
492
493 /*
494 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
495 */
496
497 #define RECEIVE_STATUS BIT5
498 #define RECEIVE_DATA BIT4
499 #define TRANSMIT_STATUS BIT3
500 #define TRANSMIT_DATA BIT2
501 #define IO_PIN BIT1
502 #define MISC BIT0
503
504
505 /*
506 * Receive status Bits in Receive Command/status Register RCSR
507 */
508
509 #define RXSTATUS_SHORT_FRAME BIT8
510 #define RXSTATUS_CODE_VIOLATION BIT8
511 #define RXSTATUS_EXITED_HUNT BIT7
512 #define RXSTATUS_IDLE_RECEIVED BIT6
513 #define RXSTATUS_BREAK_RECEIVED BIT5
514 #define RXSTATUS_ABORT_RECEIVED BIT5
515 #define RXSTATUS_RXBOUND BIT4
516 #define RXSTATUS_CRC_ERROR BIT3
517 #define RXSTATUS_FRAMING_ERROR BIT3
518 #define RXSTATUS_ABORT BIT2
519 #define RXSTATUS_PARITY_ERROR BIT2
520 #define RXSTATUS_OVERRUN BIT1
521 #define RXSTATUS_DATA_AVAILABLE BIT0
522 #define RXSTATUS_ALL 0x01f6
523 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
524
525 /*
526 * Values for setting transmit idle mode in
527 * Transmit Control/status Register (TCSR)
528 */
529 #define IDLEMODE_FLAGS 0x0000
530 #define IDLEMODE_ALT_ONE_ZERO 0x0100
531 #define IDLEMODE_ZERO 0x0200
532 #define IDLEMODE_ONE 0x0300
533 #define IDLEMODE_ALT_MARK_SPACE 0x0500
534 #define IDLEMODE_SPACE 0x0600
535 #define IDLEMODE_MARK 0x0700
536 #define IDLEMODE_MASK 0x0700
537
538 /*
539 * IUSC revision identifiers
540 */
541 #define IUSC_SL1660 0x4d44
542 #define IUSC_PRE_SL1660 0x4553
543
544 /*
545 * Transmit status Bits in Transmit Command/status Register (TCSR)
546 */
547
548 #define TCSR_PRESERVE 0x0F00
549
550 #define TCSR_UNDERWAIT BIT11
551 #define TXSTATUS_PREAMBLE_SENT BIT7
552 #define TXSTATUS_IDLE_SENT BIT6
553 #define TXSTATUS_ABORT_SENT BIT5
554 #define TXSTATUS_EOF_SENT BIT4
555 #define TXSTATUS_EOM_SENT BIT4
556 #define TXSTATUS_CRC_SENT BIT3
557 #define TXSTATUS_ALL_SENT BIT2
558 #define TXSTATUS_UNDERRUN BIT1
559 #define TXSTATUS_FIFO_EMPTY BIT0
560 #define TXSTATUS_ALL 0x00fa
561 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
562
563
564 #define MISCSTATUS_RXC_LATCHED BIT15
565 #define MISCSTATUS_RXC BIT14
566 #define MISCSTATUS_TXC_LATCHED BIT13
567 #define MISCSTATUS_TXC BIT12
568 #define MISCSTATUS_RI_LATCHED BIT11
569 #define MISCSTATUS_RI BIT10
570 #define MISCSTATUS_DSR_LATCHED BIT9
571 #define MISCSTATUS_DSR BIT8
572 #define MISCSTATUS_DCD_LATCHED BIT7
573 #define MISCSTATUS_DCD BIT6
574 #define MISCSTATUS_CTS_LATCHED BIT5
575 #define MISCSTATUS_CTS BIT4
576 #define MISCSTATUS_RCC_UNDERRUN BIT3
577 #define MISCSTATUS_DPLL_NO_SYNC BIT2
578 #define MISCSTATUS_BRG1_ZERO BIT1
579 #define MISCSTATUS_BRG0_ZERO BIT0
580
581 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
582 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
583
584 #define SICR_RXC_ACTIVE BIT15
585 #define SICR_RXC_INACTIVE BIT14
586 #define SICR_RXC (BIT15+BIT14)
587 #define SICR_TXC_ACTIVE BIT13
588 #define SICR_TXC_INACTIVE BIT12
589 #define SICR_TXC (BIT13+BIT12)
590 #define SICR_RI_ACTIVE BIT11
591 #define SICR_RI_INACTIVE BIT10
592 #define SICR_RI (BIT11+BIT10)
593 #define SICR_DSR_ACTIVE BIT9
594 #define SICR_DSR_INACTIVE BIT8
595 #define SICR_DSR (BIT9+BIT8)
596 #define SICR_DCD_ACTIVE BIT7
597 #define SICR_DCD_INACTIVE BIT6
598 #define SICR_DCD (BIT7+BIT6)
599 #define SICR_CTS_ACTIVE BIT5
600 #define SICR_CTS_INACTIVE BIT4
601 #define SICR_CTS (BIT5+BIT4)
602 #define SICR_RCC_UNDERFLOW BIT3
603 #define SICR_DPLL_NO_SYNC BIT2
604 #define SICR_BRG1_ZERO BIT1
605 #define SICR_BRG0_ZERO BIT0
606
607 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
608 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
609 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
610 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
611 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
612
613 #define usc_EnableInterrupts( a, b ) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
615
616 #define usc_DisableInterrupts( a, b ) \
617 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
618
619 #define usc_EnableMasterIrqBit(a) \
620 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
621
622 #define usc_DisableMasterIrqBit(a) \
623 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
624
625 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
626
627 /*
628 * Transmit status Bits in Transmit Control status Register (TCSR)
629 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
630 */
631
632 #define TXSTATUS_PREAMBLE_SENT BIT7
633 #define TXSTATUS_IDLE_SENT BIT6
634 #define TXSTATUS_ABORT_SENT BIT5
635 #define TXSTATUS_EOF BIT4
636 #define TXSTATUS_CRC_SENT BIT3
637 #define TXSTATUS_ALL_SENT BIT2
638 #define TXSTATUS_UNDERRUN BIT1
639 #define TXSTATUS_FIFO_EMPTY BIT0
640
641 #define DICR_MASTER BIT15
642 #define DICR_TRANSMIT BIT0
643 #define DICR_RECEIVE BIT1
644
645 #define usc_EnableDmaInterrupts(a,b) \
646 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
647
648 #define usc_DisableDmaInterrupts(a,b) \
649 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
650
651 #define usc_EnableStatusIrqs(a,b) \
652 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
653
654 #define usc_DisablestatusIrqs(a,b) \
655 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
656
657 /* Transmit status Bits in Transmit Control status Register (TCSR) */
658 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
659
660
661 #define DISABLE_UNCONDITIONAL 0
662 #define DISABLE_END_OF_FRAME 1
663 #define ENABLE_UNCONDITIONAL 2
664 #define ENABLE_AUTO_CTS 3
665 #define ENABLE_AUTO_DCD 3
666 #define usc_EnableTransmitter(a,b) \
667 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
668 #define usc_EnableReceiver(a,b) \
669 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
670
671 u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
672 void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
673 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
674
675 u16 usc_InReg( struct mgsl_struct *info, u16 Port );
676 void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
677 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
678 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
679 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
680
681 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
682 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
683
684 void usc_process_rxoverrun_sync( struct mgsl_struct *info );
685 void usc_start_receiver( struct mgsl_struct *info );
686 void usc_stop_receiver( struct mgsl_struct *info );
687
688 void usc_start_transmitter( struct mgsl_struct *info );
689 void usc_stop_transmitter( struct mgsl_struct *info );
690 void usc_set_txidle( struct mgsl_struct *info );
691 void usc_load_txfifo( struct mgsl_struct *info );
692
693 void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
694 void usc_enable_loopback( struct mgsl_struct *info, int enable );
695
696 void usc_get_serial_signals( struct mgsl_struct *info );
697 void usc_set_serial_signals( struct mgsl_struct *info );
698
699 void usc_reset( struct mgsl_struct *info );
700
701 void usc_set_sync_mode( struct mgsl_struct *info );
702 void usc_set_sdlc_mode( struct mgsl_struct *info );
703 void usc_set_async_mode( struct mgsl_struct *info );
704 void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
705
706 void usc_loopback_frame( struct mgsl_struct *info );
707
708 void mgsl_tx_timeout(unsigned long context);
709
710
711 void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
712 void usc_loopmode_insert_request( struct mgsl_struct * info );
713 int usc_loopmode_active( struct mgsl_struct * info);
714 void usc_loopmode_send_done( struct mgsl_struct * info );
715 int usc_loopmode_send_active( struct mgsl_struct * info );
716
717 int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
718
719 #ifdef CONFIG_SYNCLINK_SYNCPPP
720 /* SPPP/HDLC stuff */
721 void mgsl_sppp_init(struct mgsl_struct *info);
722 void mgsl_sppp_delete(struct mgsl_struct *info);
723 int mgsl_sppp_open(struct net_device *d);
724 int mgsl_sppp_close(struct net_device *d);
725 void mgsl_sppp_tx_timeout(struct net_device *d);
726 int mgsl_sppp_tx(struct sk_buff *skb, struct net_device *d);
727 void mgsl_sppp_rx_done(struct mgsl_struct *info, char *buf, int size);
728 void mgsl_sppp_tx_done(struct mgsl_struct *info);
729 int mgsl_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
730 struct net_device_stats *mgsl_net_stats(struct net_device *dev);
731 #endif
732
733 /*
734 * Defines a BUS descriptor value for the PCI adapter
735 * local bus address ranges.
736 */
737
738 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
739 (0x00400020 + \
740 ((WrHold) << 30) + \
741 ((WrDly) << 28) + \
742 ((RdDly) << 26) + \
743 ((Nwdd) << 20) + \
744 ((Nwad) << 15) + \
745 ((Nxda) << 13) + \
746 ((Nrdd) << 11) + \
747 ((Nrad) << 6) )
748
749 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
750
751 /*
752 * Adapter diagnostic routines
753 */
754 BOOLEAN mgsl_register_test( struct mgsl_struct *info );
755 BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
756 BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
757 BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
758 int mgsl_adapter_test( struct mgsl_struct *info );
759
760 /*
761 * device and resource management routines
762 */
763 int mgsl_claim_resources(struct mgsl_struct *info);
764 void mgsl_release_resources(struct mgsl_struct *info);
765 void mgsl_add_device(struct mgsl_struct *info);
766 struct mgsl_struct* mgsl_allocate_device(void);
767 int mgsl_enum_isa_devices(void);
768
769 /*
770 * DMA buffer manupulation functions.
771 */
772 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
773 int mgsl_get_rx_frame( struct mgsl_struct *info );
774 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
775 void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
776 void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
777
778 /*
779 * DMA and Shared Memory buffer allocation and formatting
780 */
781 int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
782 void mgsl_free_dma_buffers(struct mgsl_struct *info);
783 int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
784 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
785 int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
786 void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
787 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
788 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
789
790 /*
791 * Bottom half interrupt handlers
792 */
793 void mgsl_bh_handler(void* Context);
794 void mgsl_bh_receive(struct mgsl_struct *info);
795 void mgsl_bh_transmit(struct mgsl_struct *info);
796 void mgsl_bh_status(struct mgsl_struct *info);
797
798 /*
799 * Interrupt handler routines and dispatch table.
800 */
801 void mgsl_isr_null( struct mgsl_struct *info );
802 void mgsl_isr_transmit_data( struct mgsl_struct *info );
803 void mgsl_isr_receive_data( struct mgsl_struct *info );
804 void mgsl_isr_receive_status( struct mgsl_struct *info );
805 void mgsl_isr_transmit_status( struct mgsl_struct *info );
806 void mgsl_isr_io_pin( struct mgsl_struct *info );
807 void mgsl_isr_misc( struct mgsl_struct *info );
808 void mgsl_isr_receive_dma( struct mgsl_struct *info );
809
810 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
811
812 isr_dispatch_func UscIsrTable[7] =
813 {
814 mgsl_isr_null,
815 mgsl_isr_misc,
816 mgsl_isr_io_pin,
817 mgsl_isr_transmit_data,
818 mgsl_isr_transmit_status,
819 mgsl_isr_receive_data,
820 mgsl_isr_receive_status
821 };
822
823 /*
824 * ioctl call handlers
825 */
826 static int set_modem_info(struct mgsl_struct * info, unsigned int cmd,
827 unsigned int *value);
828 static int get_modem_info(struct mgsl_struct * info, unsigned int *value);
829 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
830 *user_icount);
831 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params);
832 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params);
833 static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode);
834 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
835 static int mgsl_txenable(struct mgsl_struct * info, int enable);
836 static int mgsl_txabort(struct mgsl_struct * info);
837 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
838 static int mgsl_wait_event(struct mgsl_struct * info, int * mask);
839 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
840
841 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
842
843 /*
844 * Global linked list of SyncLink devices
845 */
846 struct mgsl_struct *mgsl_device_list = NULL;
847 int mgsl_device_count = 0;
848
849 /*
850 * Set this param to non-zero to load eax with the
851 * .text section address and breakpoint on module load.
852 * This is useful for use with gdb and add-symbol-file command.
853 */
854 int break_on_load=0;
855
856 /*
857 * Driver major number, defaults to zero to get auto
858 * assigned major number. May be forced as module parameter.
859 */
860 int ttymajor=0;
861
862 int cuamajor=0;
863
864 /*
865 * Array of user specified options for ISA adapters.
866 */
867 static int io[MAX_ISA_DEVICES] = {0,};
868 static int irq[MAX_ISA_DEVICES] = {0,};
869 static int dma[MAX_ISA_DEVICES] = {0,};
870 static int debug_level = 0;
871 static int maxframe[MAX_TOTAL_DEVICES] = {0,};
872 static int dosyncppp[MAX_TOTAL_DEVICES] = {0,};
873
874 MODULE_PARM(break_on_load,"i");
875 MODULE_PARM(ttymajor,"i");
876 MODULE_PARM(cuamajor,"i");
877 MODULE_PARM(io,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
878 MODULE_PARM(irq,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
879 MODULE_PARM(dma,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
880 MODULE_PARM(debug_level,"i");
881 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
882 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES) "i");
883
884 static char *driver_name = "SyncLink serial driver";
885 static char *driver_version = "3.2";
886
887 static int __init synclink_init_one (struct pci_dev *dev,
888 const struct pci_device_id *ent);
889 static void __exit synclink_remove_one (struct pci_dev *dev);
890
891 static struct pci_device_id synclink_pci_tbl[] __devinitdata = {
892 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
893 { 0, }, /* terminate list */
894 };
895 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
896
897 static struct pci_driver synclink_pci_driver = {
898 name: "synclink",
899 id_table: synclink_pci_tbl,
900 probe: synclink_init_one,
901 remove: synclink_remove_one,
902 };
903
904 static struct tty_driver serial_driver, callout_driver;
905 static int serial_refcount;
906
907 /* number of characters left in xmit buffer before we ask for more */
908 #define WAKEUP_CHARS 256
909
910
911 static void mgsl_change_params(struct mgsl_struct *info);
912 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
913
914 static struct tty_struct *serial_table[MAX_TOTAL_DEVICES];
915 static struct termios *serial_termios[MAX_TOTAL_DEVICES];
916 static struct termios *serial_termios_locked[MAX_TOTAL_DEVICES];
917
918 #ifndef MIN
919 #define MIN(a,b) ((a) < (b) ? (a) : (b))
920 #endif
921
922 /*
923 * 1st function defined in .text section. Calling this function in
924 * init_module() followed by a breakpoint allows a remote debugger
925 * (gdb) to get the .text address for the add-symbol-file command.
926 * This allows remote debugging of dynamically loadable modules.
927 */
928 void* mgsl_get_text_ptr(void);
929 void* mgsl_get_text_ptr() {return mgsl_get_text_ptr;}
930
931 /*
932 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
933 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
934 * and some other program tries to do a serial write at the same time.
935 * Since the lock will only come under contention when the system is
936 * swapping and available memory is low, it makes sense to share one
937 * buffer across all the serial ioports, since it significantly saves
938 * memory if large numbers of serial ports are open.
939 */
940 static unsigned char *tmp_buf;
941 static DECLARE_MUTEX(tmp_buf_sem);
942
943 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
944 kdev_t device, const char *routine)
945 {
946 #ifdef MGSL_PARANOIA_CHECK
947 static const char *badmagic =
948 "Warning: bad magic number for mgsl struct (%s) in %s\n";
949 static const char *badinfo =
950 "Warning: null mgsl_struct for (%s) in %s\n";
951
952 if (!info) {
953 printk(badinfo, kdevname(device), routine);
954 return 1;
955 }
956 if (info->magic != MGSL_MAGIC) {
957 printk(badmagic, kdevname(device), routine);
958 return 1;
959 }
960 #endif
961 return 0;
962 }
963
964 /* mgsl_stop() throttle (stop) transmitter
965 *
966 * Arguments: tty pointer to tty info structure
967 * Return Value: None
968 */
969 static void mgsl_stop(struct tty_struct *tty)
970 {
971 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
972 unsigned long flags;
973
974 if (mgsl_paranoia_check(info, tty->device, "mgsl_stop"))
975 return;
976
977 if ( debug_level >= DEBUG_LEVEL_INFO )
978 printk("mgsl_stop(%s)\n",info->device_name);
979
980 spin_lock_irqsave(&info->irq_spinlock,flags);
981 if (info->tx_enabled)
982 usc_stop_transmitter(info);
983 spin_unlock_irqrestore(&info->irq_spinlock,flags);
984
985 } /* end of mgsl_stop() */
986
987 /* mgsl_start() release (start) transmitter
988 *
989 * Arguments: tty pointer to tty info structure
990 * Return Value: None
991 */
992 static void mgsl_start(struct tty_struct *tty)
993 {
994 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
995 unsigned long flags;
996
997 if (mgsl_paranoia_check(info, tty->device, "mgsl_start"))
998 return;
999
1000 if ( debug_level >= DEBUG_LEVEL_INFO )
1001 printk("mgsl_start(%s)\n",info->device_name);
1002
1003 spin_lock_irqsave(&info->irq_spinlock,flags);
1004 if (!info->tx_enabled)
1005 usc_start_transmitter(info);
1006 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1007
1008 } /* end of mgsl_start() */
1009
1010 /*
1011 * Bottom half work queue access functions
1012 */
1013
1014 /* mgsl_bh_action() Return next bottom half action to perform.
1015 * Return Value: BH action code or 0 if nothing to do.
1016 */
1017 int mgsl_bh_action(struct mgsl_struct *info)
1018 {
1019 unsigned long flags;
1020 int rc = 0;
1021
1022 spin_lock_irqsave(&info->irq_spinlock,flags);
1023
1024 if (info->pending_bh & BH_RECEIVE) {
1025 info->pending_bh &= ~BH_RECEIVE;
1026 rc = BH_RECEIVE;
1027 } else if (info->pending_bh & BH_TRANSMIT) {
1028 info->pending_bh &= ~BH_TRANSMIT;
1029 rc = BH_TRANSMIT;
1030 } else if (info->pending_bh & BH_STATUS) {
1031 info->pending_bh &= ~BH_STATUS;
1032 rc = BH_STATUS;
1033 }
1034
1035 if (!rc) {
1036 /* Mark BH routine as complete */
1037 info->bh_running = 0;
1038 info->bh_requested = 0;
1039 }
1040
1041 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1042
1043 return rc;
1044 }
1045
1046 /*
1047 * Perform bottom half processing of work items queued by ISR.
1048 */
1049 void mgsl_bh_handler(void* Context)
1050 {
1051 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1052 int action;
1053
1054 if (!info)
1055 return;
1056
1057 if ( debug_level >= DEBUG_LEVEL_BH )
1058 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1059 __FILE__,__LINE__,info->device_name);
1060
1061 info->bh_running = 1;
1062
1063 while((action = mgsl_bh_action(info)) != 0) {
1064
1065 /* Process work item */
1066 if ( debug_level >= DEBUG_LEVEL_BH )
1067 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1068 __FILE__,__LINE__,action);
1069
1070 switch (action) {
1071
1072 case BH_RECEIVE:
1073 mgsl_bh_receive(info);
1074 break;
1075 case BH_TRANSMIT:
1076 mgsl_bh_transmit(info);
1077 break;
1078 case BH_STATUS:
1079 mgsl_bh_status(info);
1080 break;
1081 default:
1082 /* unknown work item ID */
1083 printk("Unknown work item ID=%08X!\n", action);
1084 break;
1085 }
1086 }
1087
1088 if ( debug_level >= DEBUG_LEVEL_BH )
1089 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1090 __FILE__,__LINE__,info->device_name);
1091 }
1092
1093 void mgsl_bh_receive(struct mgsl_struct *info)
1094 {
1095 if ( debug_level >= DEBUG_LEVEL_BH )
1096 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1097 __FILE__,__LINE__,info->device_name);
1098
1099 while( mgsl_get_rx_frame(info) );
1100 }
1101
1102 void mgsl_bh_transmit(struct mgsl_struct *info)
1103 {
1104 struct tty_struct *tty = info->tty;
1105 unsigned long flags;
1106
1107 if ( debug_level >= DEBUG_LEVEL_BH )
1108 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1109 __FILE__,__LINE__,info->device_name);
1110
1111 if (tty) {
1112 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1113 tty->ldisc.write_wakeup) {
1114 if ( debug_level >= DEBUG_LEVEL_BH )
1115 printk( "%s(%d):calling ldisc.write_wakeup on %s\n",
1116 __FILE__,__LINE__,info->device_name);
1117 (tty->ldisc.write_wakeup)(tty);
1118 }
1119 wake_up_interruptible(&tty->write_wait);
1120 }
1121
1122 /* if transmitter idle and loopmode_send_done_requested
1123 * then start echoing RxD to TxD
1124 */
1125 spin_lock_irqsave(&info->irq_spinlock,flags);
1126 if ( !info->tx_active && info->loopmode_send_done_requested )
1127 usc_loopmode_send_done( info );
1128 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1129 }
1130
1131 void mgsl_bh_status(struct mgsl_struct *info)
1132 {
1133 if ( debug_level >= DEBUG_LEVEL_BH )
1134 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1135 __FILE__,__LINE__,info->device_name);
1136
1137 info->ri_chkcount = 0;
1138 info->dsr_chkcount = 0;
1139 info->dcd_chkcount = 0;
1140 info->cts_chkcount = 0;
1141 }
1142
1143 /* mgsl_isr_receive_status()
1144 *
1145 * Service a receive status interrupt. The type of status
1146 * interrupt is indicated by the state of the RCSR.
1147 * This is only used for HDLC mode.
1148 *
1149 * Arguments: info pointer to device instance data
1150 * Return Value: None
1151 */
1152 void mgsl_isr_receive_status( struct mgsl_struct *info )
1153 {
1154 u16 status = usc_InReg( info, RCSR );
1155
1156 if ( debug_level >= DEBUG_LEVEL_ISR )
1157 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1158 __FILE__,__LINE__,status);
1159
1160 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1161 info->loopmode_insert_requested &&
1162 usc_loopmode_active(info) )
1163 {
1164 ++info->icount.rxabort;
1165 info->loopmode_insert_requested = FALSE;
1166
1167 /* clear CMR:13 to start echoing RxD to TxD */
1168 info->cmr_value &= ~BIT13;
1169 usc_OutReg(info, CMR, info->cmr_value);
1170
1171 /* disable received abort irq (no longer required) */
1172 usc_OutReg(info, RICR,
1173 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1174 }
1175
1176 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1177 if (status & RXSTATUS_EXITED_HUNT)
1178 info->icount.exithunt++;
1179 if (status & RXSTATUS_IDLE_RECEIVED)
1180 info->icount.rxidle++;
1181 wake_up_interruptible(&info->event_wait_q);
1182 }
1183
1184 if (status & RXSTATUS_OVERRUN){
1185 info->icount.rxover++;
1186 usc_process_rxoverrun_sync( info );
1187 }
1188
1189 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1190 usc_UnlatchRxstatusBits( info, status );
1191
1192 } /* end of mgsl_isr_receive_status() */
1193
1194 /* mgsl_isr_transmit_status()
1195 *
1196 * Service a transmit status interrupt
1197 * HDLC mode :end of transmit frame
1198 * Async mode:all data is sent
1199 * transmit status is indicated by bits in the TCSR.
1200 *
1201 * Arguments: info pointer to device instance data
1202 * Return Value: None
1203 */
1204 void mgsl_isr_transmit_status( struct mgsl_struct *info )
1205 {
1206 u16 status = usc_InReg( info, TCSR );
1207
1208 if ( debug_level >= DEBUG_LEVEL_ISR )
1209 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1210 __FILE__,__LINE__,status);
1211
1212 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1213 usc_UnlatchTxstatusBits( info, status );
1214
1215 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1216 {
1217 /* finished sending HDLC abort. This may leave */
1218 /* the TxFifo with data from the aborted frame */
1219 /* so purge the TxFifo. Also shutdown the DMA */
1220 /* channel in case there is data remaining in */
1221 /* the DMA buffer */
1222 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1223 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1224 }
1225
1226 if ( status & TXSTATUS_EOF_SENT )
1227 info->icount.txok++;
1228 else if ( status & TXSTATUS_UNDERRUN )
1229 info->icount.txunder++;
1230 else if ( status & TXSTATUS_ABORT_SENT )
1231 info->icount.txabort++;
1232 else
1233 info->icount.txunder++;
1234
1235 info->tx_active = 0;
1236 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1237 del_timer(&info->tx_timer);
1238
1239 if ( info->drop_rts_on_tx_done ) {
1240 usc_get_serial_signals( info );
1241 if ( info->serial_signals & SerialSignal_RTS ) {
1242 info->serial_signals &= ~SerialSignal_RTS;
1243 usc_set_serial_signals( info );
1244 }
1245 info->drop_rts_on_tx_done = 0;
1246 }
1247
1248 #ifdef CONFIG_SYNCLINK_SYNCPPP
1249 if (info->netcount)
1250 mgsl_sppp_tx_done(info);
1251 else
1252 #endif
1253 {
1254 if (info->tty->stopped || info->tty->hw_stopped) {
1255 usc_stop_transmitter(info);
1256 return;
1257 }
1258 info->pending_bh |= BH_TRANSMIT;
1259 }
1260
1261 } /* end of mgsl_isr_transmit_status() */
1262
1263 /* mgsl_isr_io_pin()
1264 *
1265 * Service an Input/Output pin interrupt. The type of
1266 * interrupt is indicated by bits in the MISR
1267 *
1268 * Arguments: info pointer to device instance data
1269 * Return Value: None
1270 */
1271 void mgsl_isr_io_pin( struct mgsl_struct *info )
1272 {
1273 struct mgsl_icount *icount;
1274 u16 status = usc_InReg( info, MISR );
1275
1276 if ( debug_level >= DEBUG_LEVEL_ISR )
1277 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1278 __FILE__,__LINE__,status);
1279
1280 usc_ClearIrqPendingBits( info, IO_PIN );
1281 usc_UnlatchIostatusBits( info, status );
1282
1283 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1284 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1285 icount = &info->icount;
1286 /* update input line counters */
1287 if (status & MISCSTATUS_RI_LATCHED) {
1288 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1289 usc_DisablestatusIrqs(info,SICR_RI);
1290 icount->rng++;
1291 if ( status & MISCSTATUS_RI )
1292 info->input_signal_events.ri_up++;
1293 else
1294 info->input_signal_events.ri_down++;
1295 }
1296 if (status & MISCSTATUS_DSR_LATCHED) {
1297 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1298 usc_DisablestatusIrqs(info,SICR_DSR);
1299 icount->dsr++;
1300 if ( status & MISCSTATUS_DSR )
1301 info->input_signal_events.dsr_up++;
1302 else
1303 info->input_signal_events.dsr_down++;
1304 }
1305 if (status & MISCSTATUS_DCD_LATCHED) {
1306 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1307 usc_DisablestatusIrqs(info,SICR_DCD);
1308 icount->dcd++;
1309 if (status & MISCSTATUS_DCD) {
1310 info->input_signal_events.dcd_up++;
1311 #ifdef CONFIG_SYNCLINK_SYNCPPP
1312 if (info->netcount)
1313 sppp_reopen(info->netdev);
1314 #endif
1315 } else
1316 info->input_signal_events.dcd_down++;
1317 #ifdef CONFIG_HARD_PPS
1318 if ((info->flags & ASYNC_HARDPPS_CD) &&
1319 (status & MISCSTATUS_DCD_LATCHED))
1320 hardpps();
1321 #endif
1322 }
1323 if (status & MISCSTATUS_CTS_LATCHED)
1324 {
1325 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1326 usc_DisablestatusIrqs(info,SICR_CTS);
1327 icount->cts++;
1328 if ( status & MISCSTATUS_CTS )
1329 info->input_signal_events.cts_up++;
1330 else
1331 info->input_signal_events.cts_down++;
1332 }
1333 wake_up_interruptible(&info->status_event_wait_q);
1334 wake_up_interruptible(&info->event_wait_q);
1335
1336 if ( (info->flags & ASYNC_CHECK_CD) &&
1337 (status & MISCSTATUS_DCD_LATCHED) ) {
1338 if ( debug_level >= DEBUG_LEVEL_ISR )
1339 printk("%s CD now %s...", info->device_name,
1340 (status & MISCSTATUS_DCD) ? "on" : "off");
1341 if (status & MISCSTATUS_DCD)
1342 wake_up_interruptible(&info->open_wait);
1343 else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
1344 (info->flags & ASYNC_CALLOUT_NOHUP))) {
1345 if ( debug_level >= DEBUG_LEVEL_ISR )
1346 printk("doing serial hangup...");
1347 if (info->tty)
1348 tty_hangup(info->tty);
1349 }
1350 }
1351
1352 if ( (info->flags & ASYNC_CTS_FLOW) &&
1353 (status & MISCSTATUS_CTS_LATCHED) ) {
1354 if (info->tty->hw_stopped) {
1355 if (status & MISCSTATUS_CTS) {
1356 if ( debug_level >= DEBUG_LEVEL_ISR )
1357 printk("CTS tx start...");
1358 if (info->tty)
1359 info->tty->hw_stopped = 0;
1360 usc_start_transmitter(info);
1361 info->pending_bh |= BH_TRANSMIT;
1362 return;
1363 }
1364 } else {
1365 if (!(status & MISCSTATUS_CTS)) {
1366 if ( debug_level >= DEBUG_LEVEL_ISR )
1367 printk("CTS tx stop...");
1368 if (info->tty)
1369 info->tty->hw_stopped = 1;
1370 usc_stop_transmitter(info);
1371 }
1372 }
1373 }
1374 }
1375
1376 info->pending_bh |= BH_STATUS;
1377
1378 /* for diagnostics set IRQ flag */
1379 if ( status & MISCSTATUS_TXC_LATCHED ){
1380 usc_OutReg( info, SICR,
1381 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1382 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1383 info->irq_occurred = 1;
1384 }
1385
1386 } /* end of mgsl_isr_io_pin() */
1387
1388 /* mgsl_isr_transmit_data()
1389 *
1390 * Service a transmit data interrupt (async mode only).
1391 *
1392 * Arguments: info pointer to device instance data
1393 * Return Value: None
1394 */
1395 void mgsl_isr_transmit_data( struct mgsl_struct *info )
1396 {
1397 if ( debug_level >= DEBUG_LEVEL_ISR )
1398 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1399 __FILE__,__LINE__,info->xmit_cnt);
1400
1401 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1402
1403 if (info->tty->stopped || info->tty->hw_stopped) {
1404 usc_stop_transmitter(info);
1405 return;
1406 }
1407
1408 if ( info->xmit_cnt )
1409 usc_load_txfifo( info );
1410 else
1411 info->tx_active = 0;
1412
1413 if (info->xmit_cnt < WAKEUP_CHARS)
1414 info->pending_bh |= BH_TRANSMIT;
1415
1416 } /* end of mgsl_isr_transmit_data() */
1417
1418 /* mgsl_isr_receive_data()
1419 *
1420 * Service a receive data interrupt. This occurs
1421 * when operating in asynchronous interrupt transfer mode.
1422 * The receive data FIFO is flushed to the receive data buffers.
1423 *
1424 * Arguments: info pointer to device instance data
1425 * Return Value: None
1426 */
1427 void mgsl_isr_receive_data( struct mgsl_struct *info )
1428 {
1429 int Fifocount;
1430 u16 status;
1431 unsigned char DataByte;
1432 struct tty_struct *tty = info->tty;
1433 struct mgsl_icount *icount = &info->icount;
1434
1435 if ( debug_level >= DEBUG_LEVEL_ISR )
1436 printk("%s(%d):mgsl_isr_receive_data\n",
1437 __FILE__,__LINE__);
1438
1439 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1440
1441 /* select FIFO status for RICR readback */
1442 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1443
1444 /* clear the Wordstatus bit so that status readback */
1445 /* only reflects the status of this byte */
1446 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1447
1448 /* flush the receive FIFO */
1449
1450 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1451 /* read one byte from RxFIFO */
1452 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1453 info->io_base + CCAR );
1454 DataByte = inb( info->io_base + CCAR );
1455
1456 /* get the status of the received byte */
1457 status = usc_InReg(info, RCSR);
1458 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1459 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1460 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1461
1462 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1463 continue;
1464
1465 *tty->flip.char_buf_ptr = DataByte;
1466 icount->rx++;
1467
1468 *tty->flip.flag_buf_ptr = 0;
1469 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1470 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1471 printk("rxerr=%04X\n",status);
1472 /* update error statistics */
1473 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1474 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1475 icount->brk++;
1476 } else if (status & RXSTATUS_PARITY_ERROR)
1477 icount->parity++;
1478 else if (status & RXSTATUS_FRAMING_ERROR)
1479 icount->frame++;
1480 else if (status & RXSTATUS_OVERRUN) {
1481 /* must issue purge fifo cmd before */
1482 /* 16C32 accepts more receive chars */
1483 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1484 icount->overrun++;
1485 }
1486
1487 /* discard char if tty control flags say so */
1488 if (status & info->ignore_status_mask)
1489 continue;
1490
1491 status &= info->read_status_mask;
1492
1493 if (status & RXSTATUS_BREAK_RECEIVED) {
1494 *tty->flip.flag_buf_ptr = TTY_BREAK;
1495 if (info->flags & ASYNC_SAK)
1496 do_SAK(tty);
1497 } else if (status & RXSTATUS_PARITY_ERROR)
1498 *tty->flip.flag_buf_ptr = TTY_PARITY;
1499 else if (status & RXSTATUS_FRAMING_ERROR)
1500 *tty->flip.flag_buf_ptr = TTY_FRAME;
1501 if (status & RXSTATUS_OVERRUN) {
1502 /* Overrun is special, since it's
1503 * reported immediately, and doesn't
1504 * affect the current character
1505 */
1506 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1507 tty->flip.count++;
1508 tty->flip.flag_buf_ptr++;
1509 tty->flip.char_buf_ptr++;
1510 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
1511 }
1512 }
1513 } /* end of if (error) */
1514
1515 tty->flip.flag_buf_ptr++;
1516 tty->flip.char_buf_ptr++;
1517 tty->flip.count++;
1518 }
1519
1520 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1521 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1522 __FILE__,__LINE__,tty->flip.count);
1523 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1524 __FILE__,__LINE__,icount->rx,icount->brk,
1525 icount->parity,icount->frame,icount->overrun);
1526 }
1527
1528 if ( tty->flip.count )
1529 tty_flip_buffer_push(tty);
1530 }
1531
1532 /* mgsl_isr_misc()
1533 *
1534 * Service a miscellaneos interrupt source.
1535 *
1536 * Arguments: info pointer to device extension (instance data)
1537 * Return Value: None
1538 */
1539 void mgsl_isr_misc( struct mgsl_struct *info )
1540 {
1541 u16 status = usc_InReg( info, MISR );
1542
1543 if ( debug_level >= DEBUG_LEVEL_ISR )
1544 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1545 __FILE__,__LINE__,status);
1546
1547 usc_ClearIrqPendingBits( info, MISC );
1548 usc_UnlatchMiscstatusBits( info, status );
1549
1550 } /* end of mgsl_isr_misc() */
1551
1552 /* mgsl_isr_null()
1553 *
1554 * Services undefined interrupt vectors from the
1555 * USC. (hence this function SHOULD never be called)
1556 *
1557 * Arguments: info pointer to device extension (instance data)
1558 * Return Value: None
1559 */
1560 void mgsl_isr_null( struct mgsl_struct *info )
1561 {
1562
1563 } /* end of mgsl_isr_null() */
1564
1565 /* mgsl_isr_receive_dma()
1566 *
1567 * Service a receive DMA channel interrupt.
1568 * For this driver there are two sources of receive DMA interrupts
1569 * as identified in the Receive DMA mode Register (RDMR):
1570 *
1571 * BIT3 EOA/EOL End of List, all receive buffers in receive
1572 * buffer list have been filled (no more free buffers
1573 * available). The DMA controller has shut down.
1574 *
1575 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1576 * DMA buffer is terminated in response to completion
1577 * of a good frame or a frame with errors. The status
1578 * of the frame is stored in the buffer entry in the
1579 * list of receive buffer entries.
1580 *
1581 * Arguments: info pointer to device instance data
1582 * Return Value: None
1583 */
1584 void mgsl_isr_receive_dma( struct mgsl_struct *info )
1585 {
1586 u16 status;
1587
1588 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1589 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1590
1591 /* Read the receive DMA status to identify interrupt type. */
1592 /* This also clears the status bits. */
1593 status = usc_InDmaReg( info, RDMR );
1594
1595 if ( debug_level >= DEBUG_LEVEL_ISR )
1596 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1597 __FILE__,__LINE__,info->device_name,status);
1598
1599 info->pending_bh |= BH_RECEIVE;
1600
1601 if ( status & BIT3 ) {
1602 info->rx_overflow = 1;
1603 info->icount.buf_overrun++;
1604 }
1605
1606 } /* end of mgsl_isr_receive_dma() */
1607
1608 /* mgsl_interrupt()
1609 *
1610 * Interrupt service routine entry point.
1611 *
1612 * Arguments:
1613 *
1614 * irq interrupt number that caused interrupt
1615 * dev_id device ID supplied during interrupt registration
1616 * regs interrupted processor context
1617 *
1618 * Return Value: None
1619 */
1620 static void mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1621 {
1622 struct mgsl_struct * info;
1623 u16 UscVector;
1624 u16 DmaVector;
1625
1626 if ( debug_level >= DEBUG_LEVEL_ISR )
1627 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1628 __FILE__,__LINE__,irq);
1629
1630 info = (struct mgsl_struct *)dev_id;
1631 if (!info)
1632 return;
1633
1634 spin_lock(&info->irq_spinlock);
1635
1636 for(;;) {
1637 /* Read the interrupt vectors from hardware. */
1638 UscVector = usc_InReg(info, IVR) >> 9;
1639 DmaVector = usc_InDmaReg(info, DIVR);
1640
1641 if ( debug_level >= DEBUG_LEVEL_ISR )
1642 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1643 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1644
1645 if ( !UscVector && !DmaVector )
1646 break;
1647
1648 /* Dispatch interrupt vector */
1649 if ( UscVector )
1650 (*UscIsrTable[UscVector])(info);
1651 else
1652 mgsl_isr_receive_dma(info);
1653
1654 if ( info->isr_overflow ) {
1655 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1656 __FILE__,__LINE__,info->device_name, irq);
1657 usc_DisableMasterIrqBit(info);
1658 usc_DisableDmaInterrupts(info,DICR_MASTER);
1659 break;
1660 }
1661 }
1662
1663 /* Request bottom half processing if there's something
1664 * for it to do and the bh is not already running
1665 */
1666
1667 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1668 if ( debug_level >= DEBUG_LEVEL_ISR )
1669 printk("%s(%d):%s queueing bh task.\n",
1670 __FILE__,__LINE__,info->device_name);
1671 queue_task(&info->task, &tq_immediate);
1672 mark_bh(IMMEDIATE_BH);
1673 info->bh_requested = 1;
1674 }
1675
1676 spin_unlock(&info->irq_spinlock);
1677
1678 if ( debug_level >= DEBUG_LEVEL_ISR )
1679 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1680 __FILE__,__LINE__,irq);
1681
1682 } /* end of mgsl_interrupt() */
1683
1684 /* startup()
1685 *
1686 * Initialize and start device.
1687 *
1688 * Arguments: info pointer to device instance data
1689 * Return Value: 0 if success, otherwise error code
1690 */
1691 static int startup(struct mgsl_struct * info)
1692 {
1693 int retval = 0;
1694
1695 if ( debug_level >= DEBUG_LEVEL_INFO )
1696 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1697
1698 if (info->flags & ASYNC_INITIALIZED)
1699 return 0;
1700
1701 if (!info->xmit_buf) {
1702 /* allocate a page of memory for a transmit buffer */
1703 info->xmit_buf = (unsigned char *)get_free_page(GFP_KERNEL);
1704 if (!info->xmit_buf) {
1705 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1706 __FILE__,__LINE__,info->device_name);
1707 return -ENOMEM;
1708 }
1709 }
1710
1711 info->pending_bh = 0;
1712
1713 init_timer(&info->tx_timer);
1714 info->tx_timer.data = (unsigned long)info;
1715 info->tx_timer.function = mgsl_tx_timeout;
1716
1717 /* Allocate and claim adapter resources */
1718 retval = mgsl_claim_resources(info);
1719
1720 /* perform existance check and diagnostics */
1721 if ( !retval )
1722 retval = mgsl_adapter_test(info);
1723
1724 if ( retval ) {
1725 if (capable(CAP_SYS_ADMIN) && info->tty)
1726 set_bit(TTY_IO_ERROR, &info->tty->flags);
1727 mgsl_release_resources(info);
1728 return retval;
1729 }
1730
1731 /* program hardware for current parameters */
1732 mgsl_change_params(info);
1733
1734 if (info->tty)
1735 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1736
1737 info->flags |= ASYNC_INITIALIZED;
1738
1739 return 0;
1740
1741 } /* end of startup() */
1742
1743 /* shutdown()
1744 *
1745 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1746 *
1747 * Arguments: info pointer to device instance data
1748 * Return Value: None
1749 */
1750 static void shutdown(struct mgsl_struct * info)
1751 {
1752 unsigned long flags;
1753
1754 if (!(info->flags & ASYNC_INITIALIZED))
1755 return;
1756
1757 if (debug_level >= DEBUG_LEVEL_INFO)
1758 printk("%s(%d):mgsl_shutdown(%s)\n",
1759 __FILE__,__LINE__, info->device_name );
1760
1761 /* clear status wait queue because status changes */
1762 /* can't happen after shutting down the hardware */
1763 wake_up_interruptible(&info->status_event_wait_q);
1764 wake_up_interruptible(&info->event_wait_q);
1765
1766 del_timer(&info->tx_timer);
1767
1768 if (info->xmit_buf) {
1769 free_page((unsigned long) info->xmit_buf);
1770 info->xmit_buf = 0;
1771 }
1772
1773 spin_lock_irqsave(&info->irq_spinlock,flags);
1774 usc_DisableMasterIrqBit(info);
1775 usc_stop_receiver(info);
1776 usc_stop_transmitter(info);
1777 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1778 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1779 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1780
1781 /* Disable DMAEN (Port 7, Bit 14) */
1782 /* This disconnects the DMA request signal from the ISA bus */
1783 /* on the ISA adapter. This has no effect for the PCI adapter */
1784 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1785
1786 /* Disable INTEN (Port 6, Bit12) */
1787 /* This disconnects the IRQ request signal to the ISA bus */
1788 /* on the ISA adapter. This has no effect for the PCI adapter */
1789 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1790
1791 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1792 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1793 usc_set_serial_signals(info);
1794 }
1795
1796 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1797
1798 mgsl_release_resources(info);
1799
1800 if (info->tty)
1801 set_bit(TTY_IO_ERROR, &info->tty->flags);
1802
1803 info->flags &= ~ASYNC_INITIALIZED;
1804
1805 } /* end of shutdown() */
1806
1807 static void mgsl_program_hw(struct mgsl_struct *info)
1808 {
1809 unsigned long flags;
1810
1811 spin_lock_irqsave(&info->irq_spinlock,flags);
1812
1813 usc_stop_receiver(info);
1814 usc_stop_transmitter(info);
1815 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1816
1817 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
1818 usc_set_sync_mode(info);
1819 else
1820 usc_set_async_mode(info);
1821
1822 usc_set_serial_signals(info);
1823
1824 info->dcd_chkcount = 0;
1825 info->cts_chkcount = 0;
1826 info->ri_chkcount = 0;
1827 info->dsr_chkcount = 0;
1828
1829 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1830 usc_EnableInterrupts(info, IO_PIN);
1831 usc_get_serial_signals(info);
1832
1833 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1834 usc_start_receiver(info);
1835
1836 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1837 }
1838
1839 /* Reconfigure adapter based on new parameters
1840 */
1841 static void mgsl_change_params(struct mgsl_struct *info)
1842 {
1843 unsigned cflag;
1844 int bits_per_char;
1845
1846 if (!info->tty || !info->tty->termios)
1847 return;
1848
1849 if (debug_level >= DEBUG_LEVEL_INFO)
1850 printk("%s(%d):mgsl_change_params(%s)\n",
1851 __FILE__,__LINE__, info->device_name );
1852
1853 cflag = info->tty->termios->c_cflag;
1854
1855 /* if B0 rate (hangup) specified then negate DTR and RTS */
1856 /* otherwise assert DTR and RTS */
1857 if (cflag & CBAUD)
1858 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1859 else
1860 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1861
1862 /* byte size and parity */
1863
1864 switch (cflag & CSIZE) {
1865 case CS5: info->params.data_bits = 5; break;
1866 case CS6: info->params.data_bits = 6; break;
1867 case CS7: info->params.data_bits = 7; break;
1868 case CS8: info->params.data_bits = 8; break;
1869 /* Never happens, but GCC is too dumb to figure it out */
1870 default: info->params.data_bits = 7; break;
1871 }
1872
1873 if (cflag & CSTOPB)
1874 info->params.stop_bits = 2;
1875 else
1876 info->params.stop_bits = 1;
1877
1878 info->params.parity = ASYNC_PARITY_NONE;
1879 if (cflag & PARENB) {
1880 if (cflag & PARODD)
1881 info->params.parity = ASYNC_PARITY_ODD;
1882 else
1883 info->params.parity = ASYNC_PARITY_EVEN;
1884 #ifdef CMSPAR
1885 if (cflag & CMSPAR)
1886 info->params.parity = ASYNC_PARITY_SPACE;
1887 #endif
1888 }
1889
1890 /* calculate number of jiffies to transmit a full
1891 * FIFO (32 bytes) at specified data rate
1892 */
1893 bits_per_char = info->params.data_bits +
1894 info->params.stop_bits + 1;
1895
1896 /* if port data rate is set to 460800 or less then
1897 * allow tty settings to override, otherwise keep the
1898 * current data rate.
1899 */
1900 if (info->params.data_rate <= 460800)
1901 info->params.data_rate = tty_get_baud_rate(info->tty);
1902
1903 if ( info->params.data_rate ) {
1904 info->timeout = (32*HZ*bits_per_char) /
1905 info->params.data_rate;
1906 }
1907 info->timeout += HZ/50; /* Add .02 seconds of slop */
1908
1909 if (cflag & CRTSCTS)
1910 info->flags |= ASYNC_CTS_FLOW;
1911 else
1912 info->flags &= ~ASYNC_CTS_FLOW;
1913
1914 if (cflag & CLOCAL)
1915 info->flags &= ~ASYNC_CHECK_CD;
1916 else
1917 info->flags |= ASYNC_CHECK_CD;
1918
1919 /* process tty input control flags */
1920
1921 info->read_status_mask = RXSTATUS_OVERRUN;
1922 if (I_INPCK(info->tty))
1923 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1924 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
1925 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1926
1927 if (I_IGNPAR(info->tty))
1928 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1929 if (I_IGNBRK(info->tty)) {
1930 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1931 /* If ignoring parity and break indicators, ignore
1932 * overruns too. (For real raw support).
1933 */
1934 if (I_IGNPAR(info->tty))
1935 info->ignore_status_mask |= RXSTATUS_OVERRUN;
1936 }
1937
1938 mgsl_program_hw(info);
1939
1940 } /* end of mgsl_change_params() */
1941
1942 /* mgsl_put_char()
1943 *
1944 * Add a character to the transmit buffer.
1945 *
1946 * Arguments: tty pointer to tty information structure
1947 * ch character to add to transmit buffer
1948 *
1949 * Return Value: None
1950 */
1951 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
1952 {
1953 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1954 unsigned long flags;
1955
1956 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1957 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
1958 __FILE__,__LINE__,ch,info->device_name);
1959 }
1960
1961 if (mgsl_paranoia_check(info, tty->device, "mgsl_put_char"))
1962 return;
1963
1964 if (!tty || !info->xmit_buf)
1965 return;
1966
1967 spin_lock_irqsave(&info->irq_spinlock,flags);
1968
1969 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1970 !info->tx_active ) {
1971
1972 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
1973 info->xmit_buf[info->xmit_head++] = ch;
1974 info->xmit_head &= SERIAL_XMIT_SIZE-1;
1975 info->xmit_cnt++;
1976 }
1977 }
1978
1979 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1980
1981 } /* end of mgsl_put_char() */
1982
1983 /* mgsl_flush_chars()
1984 *
1985 * Enable transmitter so remaining characters in the
1986 * transmit buffer are sent.
1987 *
1988 * Arguments: tty pointer to tty information structure
1989 * Return Value: None
1990 */
1991 static void mgsl_flush_chars(struct tty_struct *tty)
1992 {
1993 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1994 unsigned long flags;
1995
1996 if ( debug_level >= DEBUG_LEVEL_INFO )
1997 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
1998 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
1999
2000 if (mgsl_paranoia_check(info, tty->device, "mgsl_flush_chars"))
2001 return;
2002
2003 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2004 !info->xmit_buf)
2005 return;
2006
2007 if ( debug_level >= DEBUG_LEVEL_INFO )
2008 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2009 __FILE__,__LINE__,info->device_name );
2010
2011 spin_lock_irqsave(&info->irq_spinlock,flags);
2012
2013 if (!info->tx_active) {
2014 if ( (info->params.mode == MGSL_MODE_HDLC) &&
2015 info->xmit_cnt ) {
2016 /* operating in synchronous (frame oriented) mode */
2017 /* copy data from circular xmit_buf to */
2018 /* transmit DMA buffer. */
2019 mgsl_load_tx_dma_buffer(info,
2020 info->xmit_buf,info->xmit_cnt);
2021 }
2022 usc_start_transmitter(info);
2023 }
2024
2025 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2026
2027 } /* end of mgsl_flush_chars() */
2028
2029 /* mgsl_write()
2030 *
2031 * Send a block of data
2032 *
2033 * Arguments:
2034 *
2035 * tty pointer to tty information structure
2036 * from_user flag: 1 = from user process
2037 * buf pointer to buffer containing send data
2038 * count size of send data in bytes
2039 *
2040 * Return Value: number of characters written
2041 */
2042 static int mgsl_write(struct tty_struct * tty, int from_user,
2043 const unsigned char *buf, int count)
2044 {
2045 int c, ret = 0, err;
2046 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2047 unsigned long flags;
2048
2049 if ( debug_level >= DEBUG_LEVEL_INFO )
2050 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2051 __FILE__,__LINE__,info->device_name,count);
2052
2053 if (mgsl_paranoia_check(info, tty->device, "mgsl_write"))
2054 goto cleanup;
2055
2056 if (!tty || !info->xmit_buf || !tmp_buf)
2057 goto cleanup;
2058
2059 if ( info->params.mode == MGSL_MODE_HDLC ) {
2060 /* operating in synchronous (frame oriented) mode */
2061
2062 if (info->tx_active) {
2063 ret = 0; goto cleanup;
2064 }
2065
2066 /* if operating in HDLC LoopMode and the adapter */
2067 /* has yet to be inserted into the loop, we can't */
2068 /* transmit */
2069
2070 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2071 !usc_loopmode_active(info) )
2072 {
2073 ret = 0;
2074 goto cleanup;
2075 }
2076
2077 if ( info->xmit_cnt ) {
2078 /* Send accumulated from send_char() calls */
2079 /* as frame and wait before accepting more data. */
2080 ret = 0;
2081
2082 /* copy data from circular xmit_buf to */
2083 /* transmit DMA buffer. */
2084 mgsl_load_tx_dma_buffer(info,
2085 info->xmit_buf,info->xmit_cnt);
2086 if ( debug_level >= DEBUG_LEVEL_INFO )
2087 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2088 __FILE__,__LINE__,info->device_name);
2089 } else {
2090 if ( debug_level >= DEBUG_LEVEL_INFO )
2091 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2092 __FILE__,__LINE__,info->device_name);
2093 ret = count;
2094 info->xmit_cnt = count;
2095 if (from_user) {
2096 down(&tmp_buf_sem);
2097 COPY_FROM_USER(err,tmp_buf, buf, count);
2098 if (err) {
2099 if ( debug_level >= DEBUG_LEVEL_INFO )
2100 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2101 __FILE__,__LINE__,info->device_name);
2102 ret = -EFAULT;
2103 } else
2104 mgsl_load_tx_dma_buffer(info,tmp_buf,count);
2105 up(&tmp_buf_sem);
2106 }
2107 else
2108 mgsl_load_tx_dma_buffer(info,buf,count);
2109 }
2110 } else {
2111 if (from_user) {
2112 down(&tmp_buf_sem);
2113 while (1) {
2114 c = MIN(count,
2115 MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2116 SERIAL_XMIT_SIZE - info->xmit_head));
2117 if (c <= 0)
2118 break;
2119
2120 COPY_FROM_USER(err,tmp_buf, buf, c);
2121 c -= err;
2122 if (!c) {
2123 if (!ret)
2124 ret = -EFAULT;
2125 break;
2126 }
2127 spin_lock_irqsave(&info->irq_spinlock,flags);
2128 c = MIN(c, MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2129 SERIAL_XMIT_SIZE - info->xmit_head));
2130 memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c);
2131 info->xmit_head = ((info->xmit_head + c) &
2132 (SERIAL_XMIT_SIZE-1));
2133 info->xmit_cnt += c;
2134 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2135 buf += c;
2136 count -= c;
2137 ret += c;
2138 }
2139 up(&tmp_buf_sem);
2140 } else {
2141 while (1) {
2142 spin_lock_irqsave(&info->irq_spinlock,flags);
2143 c = MIN(count,
2144 MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2145 SERIAL_XMIT_SIZE - info->xmit_head));
2146 if (c <= 0) {
2147 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2148 break;
2149 }
2150 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2151 info->xmit_head = ((info->xmit_head + c) &
2152 (SERIAL_XMIT_SIZE-1));
2153 info->xmit_cnt += c;
2154 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2155 buf += c;
2156 count -= c;
2157 ret += c;
2158 }
2159 }
2160 }
2161
2162 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2163 spin_lock_irqsave(&info->irq_spinlock,flags);
2164 if (!info->tx_active)
2165 usc_start_transmitter(info);
2166 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2167 }
2168 cleanup:
2169 if ( debug_level >= DEBUG_LEVEL_INFO )
2170 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2171 __FILE__,__LINE__,info->device_name,ret);
2172
2173 return ret;
2174
2175 } /* end of mgsl_write() */
2176
2177 /* mgsl_write_room()
2178 *
2179 * Return the count of free bytes in transmit buffer
2180 *
2181 * Arguments: tty pointer to tty info structure
2182 * Return Value: None
2183 */
2184 static int mgsl_write_room(struct tty_struct *tty)
2185 {
2186 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2187 int ret;
2188
2189 if (mgsl_paranoia_check(info, tty->device, "mgsl_write_room"))
2190 return 0;
2191 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2192 if (ret < 0)
2193 ret = 0;
2194
2195 if (debug_level >= DEBUG_LEVEL_INFO)
2196 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2197 __FILE__,__LINE__, info->device_name,ret );
2198
2199 if ( info->params.mode == MGSL_MODE_HDLC ) {
2200 /* operating in synchronous (frame oriented) mode */
2201 if ( info->tx_active )
2202 return 0;
2203 else
2204 return HDLC_MAX_FRAME_SIZE;
2205 }
2206
2207 return ret;
2208
2209 } /* end of mgsl_write_room() */
2210
2211 /* mgsl_chars_in_buffer()
2212 *
2213 * Return the count of bytes in transmit buffer
2214 *
2215 * Arguments: tty pointer to tty info structure
2216 * Return Value: None
2217 */
2218 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2219 {
2220 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2221
2222 if (debug_level >= DEBUG_LEVEL_INFO)
2223 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2224 __FILE__,__LINE__, info->device_name );
2225
2226 if (mgsl_paranoia_check(info, tty->device, "mgsl_chars_in_buffer"))
2227 return 0;
2228
2229 if (debug_level >= DEBUG_LEVEL_INFO)
2230 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2231 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2232
2233 if ( info->params.mode == MGSL_MODE_HDLC ) {
2234 /* operating in synchronous (frame oriented) mode */
2235 if ( info->tx_active )
2236 return info->tx_buffer_list[0].rcc;
2237 else
2238 return 0;
2239 }
2240
2241 return info->xmit_cnt;
2242 } /* end of mgsl_chars_in_buffer() */
2243
2244 /* mgsl_flush_buffer()
2245 *
2246 * Discard all data in the send buffer
2247 *
2248 * Arguments: tty pointer to tty info structure
2249 * Return Value: None
2250 */
2251 static void mgsl_flush_buffer(struct tty_struct *tty)
2252 {
2253 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2254 unsigned long flags;
2255
2256 if (debug_level >= DEBUG_LEVEL_INFO)
2257 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2258 __FILE__,__LINE__, info->device_name );
2259
2260 if (mgsl_paranoia_check(info, tty->device, "mgsl_flush_buffer"))
2261 return;
2262
2263 spin_lock_irqsave(&info->irq_spinlock,flags);
2264 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2265 del_timer(&info->tx_timer);
2266 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2267
2268 wake_up_interruptible(&tty->write_wait);
2269 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
2270 tty->ldisc.write_wakeup)
2271 (tty->ldisc.write_wakeup)(tty);
2272
2273 } /* end of mgsl_flush_buffer() */
2274
2275 /* mgsl_send_xchar()
2276 *
2277 * Send a high-priority XON/XOFF character
2278 *
2279 * Arguments: tty pointer to tty info structure
2280 * ch character to send
2281 * Return Value: None
2282 */
2283 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2284 {
2285 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2286 unsigned long flags;
2287
2288 if (debug_level >= DEBUG_LEVEL_INFO)
2289 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2290 __FILE__,__LINE__, info->device_name, ch );
2291
2292 if (mgsl_paranoia_check(info, tty->device, "mgsl_send_xchar"))
2293 return;
2294
2295 info->x_char = ch;
2296 if (ch) {
2297 /* Make sure transmit interrupts are on */
2298 spin_lock_irqsave(&info->irq_spinlock,flags);
2299 if (!info->tx_enabled)
2300 usc_start_transmitter(info);
2301 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2302 }
2303 } /* end of mgsl_send_xchar() */
2304
2305 /* mgsl_throttle()
2306 *
2307 * Signal remote device to throttle send data (our receive data)
2308 *
2309 * Arguments: tty pointer to tty info structure
2310 * Return Value: None
2311 */
2312 static void mgsl_throttle(struct tty_struct * tty)
2313 {
2314 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2315 unsigned long flags;
2316
2317 if (debug_level >= DEBUG_LEVEL_INFO)
2318 printk("%s(%d):mgsl_throttle(%s) entry\n",
2319 __FILE__,__LINE__, info->device_name );
2320
2321 if (mgsl_paranoia_check(info, tty->device, "mgsl_throttle"))
2322 return;
2323
2324 if (I_IXOFF(tty))
2325 mgsl_send_xchar(tty, STOP_CHAR(tty));
2326
2327 if (tty->termios->c_cflag & CRTSCTS) {
2328 spin_lock_irqsave(&info->irq_spinlock,flags);
2329 info->serial_signals &= ~SerialSignal_RTS;
2330 usc_set_serial_signals(info);
2331 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2332 }
2333 } /* end of mgsl_throttle() */
2334
2335 /* mgsl_unthrottle()
2336 *
2337 * Signal remote device to stop throttling send data (our receive data)
2338 *
2339 * Arguments: tty pointer to tty info structure
2340 * Return Value: None
2341 */
2342 static void mgsl_unthrottle(struct tty_struct * tty)
2343 {
2344 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2345 unsigned long flags;
2346
2347 if (debug_level >= DEBUG_LEVEL_INFO)
2348 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2349 __FILE__,__LINE__, info->device_name );
2350
2351 if (mgsl_paranoia_check(info, tty->device, "mgsl_unthrottle"))
2352 return;
2353
2354 if (I_IXOFF(tty)) {
2355 if (info->x_char)
2356 info->x_char = 0;
2357 else
2358 mgsl_send_xchar(tty, START_CHAR(tty));
2359 }
2360
2361 if (tty->termios->c_cflag & CRTSCTS) {
2362 spin_lock_irqsave(&info->irq_spinlock,flags);
2363 info->serial_signals |= SerialSignal_RTS;
2364 usc_set_serial_signals(info);
2365 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2366 }
2367
2368 } /* end of mgsl_unthrottle() */
2369
2370 /* mgsl_get_stats()
2371 *
2372 * get the current serial parameters information
2373 *
2374 * Arguments: info pointer to device instance data
2375 * user_icount pointer to buffer to hold returned stats
2376 *
2377 * Return Value: 0 if success, otherwise error code
2378 */
2379 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount *user_icount)
2380 {
2381 int err;
2382
2383 if (debug_level >= DEBUG_LEVEL_INFO)
2384 printk("%s(%d):mgsl_get_params(%s)\n",
2385 __FILE__,__LINE__, info->device_name);
2386
2387 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2388 if (err) {
2389 if ( debug_level >= DEBUG_LEVEL_INFO )
2390 printk( "%s(%d):mgsl_get_stats(%s) user buffer copy failed\n",
2391 __FILE__,__LINE__,info->device_name);
2392 return -EFAULT;
2393 }
2394
2395 return 0;
2396
2397 } /* end of mgsl_get_stats() */
2398
2399 /* mgsl_get_params()
2400 *
2401 * get the current serial parameters information
2402 *
2403 * Arguments: info pointer to device instance data
2404 * user_params pointer to buffer to hold returned params
2405 *
2406 * Return Value: 0 if success, otherwise error code
2407 */
2408 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params)
2409 {
2410 int err;
2411 if (debug_level >= DEBUG_LEVEL_INFO)
2412 printk("%s(%d):mgsl_get_params(%s)\n",
2413 __FILE__,__LINE__, info->device_name);
2414
2415 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2416 if (err) {
2417 if ( debug_level >= DEBUG_LEVEL_INFO )
2418 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2419 __FILE__,__LINE__,info->device_name);
2420 return -EFAULT;
2421 }
2422
2423 return 0;
2424
2425 } /* end of mgsl_get_params() */
2426
2427 /* mgsl_set_params()
2428 *
2429 * set the serial parameters
2430 *
2431 * Arguments:
2432 *
2433 * info pointer to device instance data
2434 * new_params user buffer containing new serial params
2435 *
2436 * Return Value: 0 if success, otherwise error code
2437 */
2438 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params)
2439 {
2440 unsigned long flags;
2441 MGSL_PARAMS tmp_params;
2442 int err;
2443
2444 if (debug_level >= DEBUG_LEVEL_INFO)
2445 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2446 info->device_name );
2447 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2448 if (err) {
2449 if ( debug_level >= DEBUG_LEVEL_INFO )
2450 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2451 __FILE__,__LINE__,info->device_name);
2452 return -EFAULT;
2453 }
2454
2455 spin_lock_irqsave(&info->irq_spinlock,flags);
2456 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2457 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2458
2459 mgsl_change_params(info);
2460
2461 return 0;
2462
2463 } /* end of mgsl_set_params() */
2464
2465 /* mgsl_get_txidle()
2466 *
2467 * get the current transmit idle mode
2468 *
2469 * Arguments: info pointer to device instance data
2470 * idle_mode pointer to buffer to hold returned idle mode
2471 *
2472 * Return Value: 0 if success, otherwise error code
2473 */
2474 static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode)
2475 {
2476 int err;
2477
2478 if (debug_level >= DEBUG_LEVEL_INFO)
2479 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2480 __FILE__,__LINE__, info->device_name, info->idle_mode);
2481
2482 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2483 if (err) {
2484 if ( debug_level >= DEBUG_LEVEL_INFO )
2485 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2486 __FILE__,__LINE__,info->device_name);
2487 return -EFAULT;
2488 }
2489
2490 return 0;
2491
2492 } /* end of mgsl_get_txidle() */
2493
2494 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2495 *
2496 * Arguments: info pointer to device instance data
2497 * idle_mode new idle mode
2498 *
2499 * Return Value: 0 if success, otherwise error code
2500 */
2501 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2502 {
2503 unsigned long flags;
2504
2505 if (debug_level >= DEBUG_LEVEL_INFO)
2506 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2507 info->device_name, idle_mode );
2508
2509 spin_lock_irqsave(&info->irq_spinlock,flags);
2510 info->idle_mode = idle_mode;
2511 usc_set_txidle( info );
2512 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2513 return 0;
2514
2515 } /* end of mgsl_set_txidle() */
2516
2517 /* mgsl_txenable()
2518 *
2519 * enable or disable the transmitter
2520 *
2521 * Arguments:
2522 *
2523 * info pointer to device instance data
2524 * enable 1 = enable, 0 = disable
2525 *
2526 * Return Value: 0 if success, otherwise error code
2527 */
2528 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2529 {
2530 unsigned long flags;
2531
2532 if (debug_level >= DEBUG_LEVEL_INFO)
2533 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2534 info->device_name, enable);
2535
2536 spin_lock_irqsave(&info->irq_spinlock,flags);
2537 if ( enable ) {
2538 if ( !info->tx_enabled ) {
2539
2540 usc_start_transmitter(info);
2541 /*--------------------------------------------------
2542 * if HDLC/SDLC Loop mode, attempt to insert the
2543 * station in the 'loop' by setting CMR:13. Upon
2544 * receipt of the next GoAhead (RxAbort) sequence,
2545 * the OnLoop indicator (CCSR:7) should go active
2546 * to indicate that we are on the loop
2547 *--------------------------------------------------*/
2548 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2549 usc_loopmode_insert_request( info );
2550 }
2551 } else {
2552 if ( info->tx_enabled )
2553 usc_stop_transmitter(info);
2554 }
2555 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2556 return 0;
2557
2558 } /* end of mgsl_txenable() */
2559
2560 /* mgsl_txabort() abort send HDLC frame
2561 *
2562 * Arguments: info pointer to device instance data
2563 * Return Value: 0 if success, otherwise error code
2564 */
2565 static int mgsl_txabort(struct mgsl_struct * info)
2566 {
2567 unsigned long flags;
2568
2569 if (debug_level >= DEBUG_LEVEL_INFO)
2570 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2571 info->device_name);
2572
2573 spin_lock_irqsave(&info->irq_spinlock,flags);
2574 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2575 {
2576 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2577 usc_loopmode_cancel_transmit( info );
2578 else
2579 usc_TCmd(info,TCmd_SendAbort);
2580 }
2581 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2582 return 0;
2583
2584 } /* end of mgsl_txabort() */
2585
2586 /* mgsl_rxenable() enable or disable the receiver
2587 *
2588 * Arguments: info pointer to device instance data
2589 * enable 1 = enable, 0 = disable
2590 * Return Value: 0 if success, otherwise error code
2591 */
2592 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2593 {
2594 unsigned long flags;
2595
2596 if (debug_level >= DEBUG_LEVEL_INFO)
2597 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2598 info->device_name, enable);
2599
2600 spin_lock_irqsave(&info->irq_spinlock,flags);
2601 if ( enable ) {
2602 if ( !info->rx_enabled )
2603 usc_start_receiver(info);
2604 } else {
2605 if ( info->rx_enabled )
2606 usc_stop_receiver(info);
2607 }
2608 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2609 return 0;
2610
2611 } /* end of mgsl_rxenable() */
2612
2613 /* mgsl_wait_event() wait for specified event to occur
2614 *
2615 * Arguments: info pointer to device instance data
2616 * mask pointer to bitmask of events to wait for
2617 * Return Value: 0 if successful and bit mask updated with
2618 * of events triggerred,
2619 * otherwise error code
2620 */
2621 static int mgsl_wait_event(struct mgsl_struct * info, int * mask_ptr)
2622 {
2623 unsigned long flags;
2624 int s;
2625 int rc=0;
2626 u16 regval;
2627 struct mgsl_icount cprev, cnow;
2628 int events = 0;
2629 int mask;
2630 struct _input_signal_events signal_events_prev, signal_events_now;
2631
2632 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2633 if (rc) {
2634 return -EFAULT;
2635 }
2636
2637 if (debug_level >= DEBUG_LEVEL_INFO)
2638 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2639 info->device_name, mask);
2640
2641 spin_lock_irqsave(&info->irq_spinlock,flags);
2642
2643 usc_get_serial_signals(info);
2644 s = info->serial_signals;
2645
2646 /* note the counters on entry */
2647 cprev = info->icount;
2648 signal_events_prev = info->input_signal_events;
2649
2650 if (mask & MgslEvent_ExitHuntMode) {
2651 /* enable exit hunt mode IRQ */
2652 regval = usc_InReg(info,RICR);
2653 if (!(regval & RXSTATUS_EXITED_HUNT))
2654 usc_OutReg(info, RICR, regval | RXSTATUS_EXITED_HUNT);
2655 }
2656
2657 if (mask & MgslEvent_IdleReceived) {
2658 /* enable idle mode received IRQ */
2659 regval = usc_InReg(info,RICR);
2660 if (!(regval & RXSTATUS_IDLE_RECEIVED))
2661 usc_OutReg(info, RICR, regval | RXSTATUS_IDLE_RECEIVED);
2662 }
2663
2664 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2665
2666 /* Determine if any user requested events for input signals is currently TRUE */
2667
2668 events |= (mask & ((s & SerialSignal_DSR) ?
2669 MgslEvent_DsrActive:MgslEvent_DsrInactive));
2670
2671 events |= (mask & ((s & SerialSignal_DCD) ?
2672 MgslEvent_DcdActive:MgslEvent_DcdInactive));
2673
2674 events |= (mask & ((s & SerialSignal_CTS) ?
2675 MgslEvent_CtsActive:MgslEvent_CtsInactive));
2676
2677 events |= (mask & ((s & SerialSignal_RI) ?
2678 MgslEvent_RiActive:MgslEvent_RiInactive));
2679
2680
2681 while(!events) {
2682 /* sleep until event occurs */
2683 interruptible_sleep_on(&info->event_wait_q);
2684
2685 /* see if a signal woke us */
2686 if (signal_pending(current)) {
2687 rc = -ERESTARTSYS;
2688 break;
2689 }
2690
2691 spin_lock_irqsave(&info->irq_spinlock,flags);
2692
2693 /* get icount and serial signal states */
2694 cnow = info->icount;
2695 signal_events_now = info->input_signal_events;
2696 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2697
2698 if (signal_events_now.dsr_up != signal_events_prev.dsr_up &&
2699 mask & MgslEvent_DsrActive )
2700 events |= MgslEvent_DsrActive;
2701
2702 if (signal_events_now.dsr_down != signal_events_prev.dsr_down &&
2703 mask & MgslEvent_DsrInactive )
2704 events |= MgslEvent_DsrInactive;
2705
2706 if (signal_events_now.dcd_up != signal_events_prev.dcd_up &&
2707 mask & MgslEvent_DcdActive )
2708 events |= MgslEvent_DcdActive;
2709
2710 if (signal_events_now.dcd_down != signal_events_prev.dcd_down &&
2711 mask & MgslEvent_DcdInactive )
2712 events |= MgslEvent_DcdInactive;
2713
2714 if (signal_events_now.cts_up != signal_events_prev.cts_up &&
2715 mask & MgslEvent_CtsActive )
2716 events |= MgslEvent_CtsActive;
2717
2718 if (signal_events_now.cts_down != signal_events_prev.cts_down &&
2719 mask & MgslEvent_CtsInactive )
2720 events |= MgslEvent_CtsInactive;
2721
2722 if (signal_events_now.ri_up != signal_events_prev.ri_up &&
2723 mask & MgslEvent_RiActive )
2724 events |= MgslEvent_RiActive;
2725
2726 if (signal_events_now.ri_down != signal_events_prev.ri_down &&
2727 mask & MgslEvent_RiInactive )
2728 events |= MgslEvent_RiInactive;
2729
2730 if (cnow.exithunt != cprev.exithunt)
2731 events |= (mask & MgslEvent_ExitHuntMode);
2732
2733 if (cnow.rxidle != cprev.rxidle)
2734 events |= (mask & MgslEvent_IdleReceived);
2735
2736 cprev = cnow;
2737 signal_events_prev = signal_events_now;
2738 }
2739
2740 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2741 spin_lock_irqsave(&info->irq_spinlock,flags);
2742 if (!waitqueue_active(&info->event_wait_q)) {
2743 /* disable enable exit hunt mode/idle rcvd IRQs */
2744 regval = usc_InReg(info,RICR);
2745 usc_OutReg(info, RICR, regval &
2746 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2747 }
2748 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2749 }
2750
2751 if ( rc == 0 )
2752 PUT_USER(rc, events, mask_ptr);
2753
2754 return rc;
2755
2756 } /* end of mgsl_wait_event() */
2757
2758 /* get_modem_info()
2759 *
2760 * Read the state of the serial control and
2761 * status signals and return to caller.
2762 *
2763 * Arguments: info pointer to device instance data
2764 * value pointer to int to hold returned info
2765 *
2766 * Return Value: 0 if success, otherwise error code
2767 */
2768 static int get_modem_info(struct mgsl_struct * info, unsigned int *value)
2769 {
2770 unsigned int result = 0;
2771 unsigned long flags;
2772 int err;
2773
2774 spin_lock_irqsave(&info->irq_spinlock,flags);
2775 usc_get_serial_signals(info);
2776 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2777
2778 if (info->serial_signals & SerialSignal_RTS)
2779 result |= TIOCM_RTS;
2780 if (info->serial_signals & SerialSignal_DTR)
2781 result |= TIOCM_DTR;
2782 if (info->serial_signals & SerialSignal_DCD)
2783 result |= TIOCM_CAR;
2784 if (info->serial_signals & SerialSignal_RI)
2785 result |= TIOCM_RNG;
2786 if (info->serial_signals & SerialSignal_DSR)
2787 result |= TIOCM_DSR;
2788 if (info->serial_signals & SerialSignal_CTS)
2789 result |= TIOCM_CTS;
2790
2791 if (debug_level >= DEBUG_LEVEL_INFO)
2792 printk("%s(%d):mgsl_get_modem_info %s value=%08X\n",
2793 __FILE__,__LINE__, info->device_name, result );
2794
2795 PUT_USER(err,result,value);
2796 return err;
2797 } /* end of get_modem_info() */
2798
2799 /* set_modem_info()
2800 *
2801 * Set the state of the modem control signals (DTR/RTS)
2802 *
2803 * Arguments:
2804 *
2805 * info pointer to device instance data
2806 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2807 * TIOCMSET = set/clear signal values
2808 * value bit mask for command
2809 *
2810 * Return Value: 0 if success, otherwise error code
2811 */
2812 static int set_modem_info(struct mgsl_struct * info, unsigned int cmd,
2813 unsigned int *value)
2814 {
2815 int error;
2816 unsigned int arg;
2817 unsigned long flags;
2818
2819 if (debug_level >= DEBUG_LEVEL_INFO)
2820 printk("%s(%d):mgsl_set_modem_info %s\n", __FILE__,__LINE__,
2821 info->device_name );
2822
2823 GET_USER(error,arg,value);
2824 if (error)
2825 return error;
2826
2827 switch (cmd) {
2828 case TIOCMBIS:
2829 if (arg & TIOCM_RTS)
2830 info->serial_signals |= SerialSignal_RTS;
2831 if (arg & TIOCM_DTR)
2832 info->serial_signals |= SerialSignal_DTR;
2833 break;
2834 case TIOCMBIC:
2835 if (arg & TIOCM_RTS)
2836 info->serial_signals &= ~SerialSignal_RTS;
2837 if (arg & TIOCM_DTR)
2838 info->serial_signals &= ~SerialSignal_DTR;
2839 break;
2840 case TIOCMSET:
2841 if (arg & TIOCM_RTS)
2842 info->serial_signals |= SerialSignal_RTS;
2843 else
2844 info->serial_signals &= ~SerialSignal_RTS;
2845
2846 if (arg & TIOCM_DTR)
2847 info->serial_signals |= SerialSignal_DTR;
2848 else
2849 info->serial_signals &= ~SerialSignal_DTR;
2850 break;
2851 default:
2852 return -EINVAL;
2853 }
2854
2855 spin_lock_irqsave(&info->irq_spinlock,flags);
2856 usc_set_serial_signals(info);
2857 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2858
2859 return 0;
2860
2861 } /* end of set_modem_info() */
2862
2863 /* mgsl_break() Set or clear transmit break condition
2864 *
2865 * Arguments: tty pointer to tty instance data
2866 * break_state -1=set break condition, 0=clear
2867 * Return Value: None
2868 */
2869 static void mgsl_break(struct tty_struct *tty, int break_state)
2870 {
2871 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2872 unsigned long flags;
2873
2874 if (debug_level >= DEBUG_LEVEL_INFO)
2875 printk("%s(%d):mgsl_break(%s,%d)\n",
2876 __FILE__,__LINE__, info->device_name, break_state);
2877
2878 if (mgsl_paranoia_check(info, tty->device, "mgsl_break"))
2879 return;
2880
2881 spin_lock_irqsave(&info->irq_spinlock,flags);
2882 if (break_state == -1)
2883 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2884 else
2885 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2886 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2887
2888 } /* end of mgsl_break() */
2889
2890 /* mgsl_ioctl() Service an IOCTL request
2891 *
2892 * Arguments:
2893 *
2894 * tty pointer to tty instance data
2895 * file pointer to associated file object for device
2896 * cmd IOCTL command code
2897 * arg command argument/context
2898 *
2899 * Return Value: 0 if success, otherwise error code
2900 */
2901 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2902 unsigned int cmd, unsigned long arg)
2903 {
2904 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2905
2906 if (debug_level >= DEBUG_LEVEL_INFO)
2907 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2908 info->device_name, cmd );
2909
2910 if (mgsl_paranoia_check(info, tty->device, "mgsl_ioctl"))
2911 return -ENODEV;
2912
2913 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2914 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2915 if (tty->flags & (1 << TTY_IO_ERROR))
2916 return -EIO;
2917 }
2918
2919 return mgsl_ioctl_common(info, cmd, arg);
2920 }
2921
2922 int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2923 {
2924 int error;
2925 struct mgsl_icount cprev, cnow; /* kernel counter temps */
2926 struct serial_icounter_struct *p_cuser; /* user space */
2927 unsigned long flags;
2928
2929 switch (cmd) {
2930 case TIOCMGET:
2931 return get_modem_info(info, (unsigned int *) arg);
2932 case TIOCMBIS:
2933 case TIOCMBIC:
2934 case TIOCMSET:
2935 return set_modem_info(info, cmd, (unsigned int *) arg);
2936 case MGSL_IOCGPARAMS:
2937 return mgsl_get_params(info,(MGSL_PARAMS *)arg);
2938 case MGSL_IOCSPARAMS:
2939 return mgsl_set_params(info,(MGSL_PARAMS *)arg);
2940 case MGSL_IOCGTXIDLE:
2941 return mgsl_get_txidle(info,(int*)arg);
2942 case MGSL_IOCSTXIDLE:
2943 return mgsl_set_txidle(info,(int)arg);
2944 case MGSL_IOCTXENABLE:
2945 return mgsl_txenable(info,(int)arg);
2946 case MGSL_IOCRXENABLE:
2947 return mgsl_rxenable(info,(int)arg);
2948 case MGSL_IOCTXABORT:
2949 return mgsl_txabort(info);
2950 case MGSL_IOCGSTATS:
2951 return mgsl_get_stats(info,(struct mgsl_icount*)arg);
2952 case MGSL_IOCWAITEVENT:
2953 return mgsl_wait_event(info,(int*)arg);
2954 case MGSL_IOCLOOPTXDONE:
2955 return mgsl_loopmode_send_done(info);
2956 case MGSL_IOCCLRMODCOUNT:
2957 while(MOD_IN_USE)
2958 MOD_DEC_USE_COUNT;
2959 return 0;
2960 /*
2961 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
2962 * - mask passed in arg for lines of interest
2963 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
2964 * Caller should use TIOCGICOUNT to see which one it was
2965 */
2966 case TIOCMIWAIT:
2967 spin_lock_irqsave(&info->irq_spinlock,flags);
2968 /* note the counters on entry */
2969 cprev = info->icount;
2970 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2971 while (1) {
2972 interruptible_sleep_on(&info->status_event_wait_q);
2973 /* see if a signal did it */
2974 if (signal_pending(current))
2975 return -ERESTARTSYS;
2976 save_flags(flags); cli();
2977 cnow = info->icount; /* atomic copy */
2978 restore_flags(flags);
2979 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2980 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
2981 return -EIO; /* no change => error */
2982 if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
2983 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
2984 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
2985 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
2986 return 0;
2987 }
2988 cprev = cnow;
2989 }
2990 /* NOTREACHED */
2991
2992 /*
2993 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2994 * Return: write counters to the user passed counter struct
2995 * NB: both 1->0 and 0->1 transitions are counted except for
2996 * RI where only 0->1 is counted.
2997 */
2998 case TIOCGICOUNT:
2999 spin_lock_irqsave(&info->irq_spinlock,flags);
3000 cnow = info->icount;
3001 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3002 p_cuser = (struct serial_icounter_struct *) arg;
3003 PUT_USER(error,cnow.cts, &p_cuser->cts);
3004 if (error) return error;
3005 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3006 if (error) return error;
3007 PUT_USER(error,cnow.rng, &p_cuser->rng);
3008 if (error) return error;
3009 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3010 if (error) return error;
3011 PUT_USER(error,cnow.rx, &p_cuser->rx);
3012 if (error) return error;
3013 PUT_USER(error,cnow.tx, &p_cuser->tx);
3014 if (error) return error;
3015 PUT_USER(error,cnow.frame, &p_cuser->frame);
3016 if (error) return error;
3017 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3018 if (error) return error;
3019 PUT_USER(error,cnow.parity, &p_cuser->parity);
3020 if (error) return error;
3021 PUT_USER(error,cnow.brk, &p_cuser->brk);
3022 if (error) return error;
3023 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3024 if (error) return error;
3025 return 0;
3026 default:
3027 return -ENOIOCTLCMD;
3028 }
3029 return 0;
3030 }
3031
3032 /* mgsl_set_termios()
3033 *
3034 * Set new termios settings
3035 *
3036 * Arguments:
3037 *
3038 * tty pointer to tty structure
3039 * termios pointer to buffer to hold returned old termios
3040 *
3041 * Return Value: None
3042 */
3043 static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3044 {
3045 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3046 unsigned long flags;
3047
3048 if (debug_level >= DEBUG_LEVEL_INFO)
3049 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3050 tty->driver.name );
3051
3052 /* just return if nothing has changed */
3053 if ((tty->termios->c_cflag == old_termios->c_cflag)
3054 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3055 == RELEVANT_IFLAG(old_termios->c_iflag)))
3056 return;
3057
3058 mgsl_change_params(info);
3059
3060 /* Handle transition to B0 status */
3061 if (old_termios->c_cflag & CBAUD &&
3062 !(tty->termios->c_cflag & CBAUD)) {
3063 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3064 spin_lock_irqsave(&info->irq_spinlock,flags);
3065 usc_set_serial_signals(info);
3066 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3067 }
3068
3069 /* Handle transition away from B0 status */
3070 if (!(old_termios->c_cflag & CBAUD) &&
3071 tty->termios->c_cflag & CBAUD) {
3072 info->serial_signals |= SerialSignal_DTR;
3073 if (!(tty->termios->c_cflag & CRTSCTS) ||
3074 !test_bit(TTY_THROTTLED, &tty->flags)) {
3075 info->serial_signals |= SerialSignal_RTS;
3076 }
3077 spin_lock_irqsave(&info->irq_spinlock,flags);
3078 usc_set_serial_signals(info);
3079 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3080 }
3081
3082 /* Handle turning off CRTSCTS */
3083 if (old_termios->c_cflag & CRTSCTS &&
3084 !(tty->termios->c_cflag & CRTSCTS)) {
3085 tty->hw_stopped = 0;
3086 mgsl_start(tty);
3087 }
3088
3089 } /* end of mgsl_set_termios() */
3090
3091 /* mgsl_close()
3092 *
3093 * Called when port is closed. Wait for remaining data to be
3094 * sent. Disable port and free resources.
3095 *
3096 * Arguments:
3097 *
3098 * tty pointer to open tty structure
3099 * filp pointer to open file object
3100 *
3101 * Return Value: None
3102 */
3103 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3104 {
3105 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3106
3107 if (!info || mgsl_paranoia_check(info, tty->device, "mgsl_close"))
3108 return;
3109
3110 if (debug_level >= DEBUG_LEVEL_INFO)
3111 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3112 __FILE__,__LINE__, info->device_name, info->count);
3113
3114 if (!info->count || tty_hung_up_p(filp))
3115 goto cleanup;
3116
3117 if ((tty->count == 1) && (info->count != 1)) {
3118 /*
3119 * tty->count is 1 and the tty structure will be freed.
3120 * info->count should be one in this case.
3121 * if it's not, correct it so that the port is shutdown.
3122 */
3123 printk("mgsl_close: bad refcount; tty->count is 1, "
3124 "info->count is %d\n", info->count);
3125 info->count = 1;
3126 }
3127
3128 info->count--;
3129
3130 /* if at least one open remaining, leave hardware active */
3131 if (info->count)
3132 goto cleanup;
3133
3134 info->flags |= ASYNC_CLOSING;
3135
3136 /* Save the termios structure, since this port may have
3137 * separate termios for callout and dialin.
3138 */
3139 if (info->flags & ASYNC_NORMAL_ACTIVE)
3140 info->normal_termios = *tty->termios;
3141 if (info->flags & ASYNC_CALLOUT_ACTIVE)
3142 info->callout_termios = *tty->termios;
3143
3144 /* set tty->closing to notify line discipline to
3145 * only process XON/XOFF characters. Only the N_TTY
3146 * discipline appears to use this (ppp does not).
3147 */
3148 tty->closing = 1;
3149
3150 /* wait for transmit data to clear all layers */
3151
3152 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3153 if (debug_level >= DEBUG_LEVEL_INFO)
3154 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3155 __FILE__,__LINE__, info->device_name );
3156 tty_wait_until_sent(tty, info->closing_wait);
3157 }
3158
3159 if (info->flags & ASYNC_INITIALIZED)
3160 mgsl_wait_until_sent(tty, info->timeout);
3161
3162 if (tty->driver.flush_buffer)
3163 tty->driver.flush_buffer(tty);
3164
3165 if (tty->ldisc.flush_buffer)
3166 tty->ldisc.flush_buffer(tty);
3167
3168 shutdown(info);
3169
3170 tty->closing = 0;
3171 info->tty = 0;
3172
3173 if (info->blocked_open) {
3174 if (info->close_delay) {
3175 set_current_state(TASK_INTERRUPTIBLE);
3176 schedule_timeout(info->close_delay);
3177 }
3178 wake_up_interruptible(&info->open_wait);
3179 }
3180
3181 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|
3182 ASYNC_CLOSING);
3183
3184 wake_up_interruptible(&info->close_wait);
3185
3186 cleanup:
3187 if (debug_level >= DEBUG_LEVEL_INFO)
3188 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3189 tty->driver.name, info->count);
3190 if(MOD_IN_USE)
3191 MOD_DEC_USE_COUNT;
3192
3193 } /* end of mgsl_close() */
3194
3195 /* mgsl_wait_until_sent()
3196 *
3197 * Wait until the transmitter is empty.
3198 *
3199 * Arguments:
3200 *
3201 * tty pointer to tty info structure
3202 * timeout time to wait for send completion
3203 *
3204 * Return Value: None
3205 */
3206 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3207 {
3208 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3209 unsigned long orig_jiffies, char_time;
3210
3211 if (!info )
3212 return;
3213
3214 if (debug_level >= DEBUG_LEVEL_INFO)
3215 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3216 __FILE__,__LINE__, info->device_name );
3217
3218 if (mgsl_paranoia_check(info, tty->device, "mgsl_wait_until_sent"))
3219 return;
3220
3221 if (!(info->flags & ASYNC_INITIALIZED))
3222 goto exit;
3223
3224 orig_jiffies = jiffies;
3225
3226 /* Set check interval to 1/5 of estimated time to
3227 * send a character, and make it at least 1. The check
3228 * interval should also be less than the timeout.
3229 * Note: use tight timings here to satisfy the NIST-PCTS.
3230 */
3231
3232 if ( info->params.data_rate ) {
3233 char_time = info->timeout/(32 * 5);
3234 if (!char_time)
3235 char_time++;
3236 } else
3237 char_time = 1;
3238
3239 if (timeout)
3240 char_time = MIN(char_time, timeout);
3241
3242 if ( info->params.mode == MGSL_MODE_HDLC ) {
3243 while (info->tx_active) {
3244 set_current_state(TASK_INTERRUPTIBLE);
3245 schedule_timeout(char_time);
3246 if (signal_pending(current))
3247 break;
3248 if (timeout && ((orig_jiffies + timeout) < jiffies))
3249 break;
3250 }
3251 } else {
3252 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3253 info->tx_enabled) {
3254 set_current_state(TASK_INTERRUPTIBLE);
3255 schedule_timeout(char_time);
3256 if (signal_pending(current))
3257 break;
3258 if (timeout && ((orig_jiffies + timeout) < jiffies))
3259 break;
3260 }
3261 }
3262
3263 exit:
3264 if (debug_level >= DEBUG_LEVEL_INFO)
3265 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3266 __FILE__,__LINE__, info->device_name );
3267
3268 } /* end of mgsl_wait_until_sent() */
3269
3270 /* mgsl_hangup()
3271 *
3272 * Called by tty_hangup() when a hangup is signaled.
3273 * This is the same as to closing all open files for the port.
3274 *
3275 * Arguments: tty pointer to associated tty object
3276 * Return Value: None
3277 */
3278 static void mgsl_hangup(struct tty_struct *tty)
3279 {
3280 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3281
3282 if (debug_level >= DEBUG_LEVEL_INFO)
3283 printk("%s(%d):mgsl_hangup(%s)\n",
3284 __FILE__,__LINE__, info->device_name );
3285
3286 if (mgsl_paranoia_check(info, tty->device, "mgsl_hangup"))
3287 return;
3288
3289 mgsl_flush_buffer(tty);
3290 shutdown(info);
3291
3292 info->count = 0;
3293 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
3294 info->tty = 0;
3295
3296 wake_up_interruptible(&info->open_wait);
3297
3298 } /* end of mgsl_hangup() */
3299
3300 /* block_til_ready()
3301 *
3302 * Block the current process until the specified port
3303 * is ready to be opened.
3304 *
3305 * Arguments:
3306 *
3307 * tty pointer to tty info structure
3308 * filp pointer to open file object
3309 * info pointer to device instance data
3310 *
3311 * Return Value: 0 if success, otherwise error code
3312 */
3313 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3314 struct mgsl_struct *info)
3315 {
3316 DECLARE_WAITQUEUE(wait, current);
3317 int retval;
3318 int do_clocal = 0, extra_count = 0;
3319 unsigned long flags;
3320
3321 if (debug_level >= DEBUG_LEVEL_INFO)
3322 printk("%s(%d):block_til_ready on %s\n",
3323 __FILE__,__LINE__, tty->driver.name );
3324
3325 if (tty->driver.subtype == SERIAL_TYPE_CALLOUT) {
3326 /* this is a callout device */
3327 /* just verify that normal device is not in use */
3328 if (info->flags & ASYNC_NORMAL_ACTIVE)
3329 return -EBUSY;
3330 if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
3331 (info->flags & ASYNC_SESSION_LOCKOUT) &&
3332 (info->session != current->session))
3333 return -EBUSY;
3334 if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
3335 (info->flags & ASYNC_PGRP_LOCKOUT) &&
3336 (info->pgrp != current->pgrp))
3337 return -EBUSY;
3338 info->flags |= ASYNC_CALLOUT_ACTIVE;
3339 return 0;
3340 }
3341
3342 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3343 /* nonblock mode is set or port is not enabled */
3344 /* just verify that callout device is not active */
3345 if (info->flags & ASYNC_CALLOUT_ACTIVE)
3346 return -EBUSY;
3347 info->flags |= ASYNC_NORMAL_ACTIVE;
3348 return 0;
3349 }
3350
3351 if (info->flags & ASYNC_CALLOUT_ACTIVE) {
3352 if (info->normal_termios.c_cflag & CLOCAL)
3353 do_clocal = 1;
3354 } else {
3355 if (tty->termios->c_cflag & CLOCAL)
3356 do_clocal = 1;
3357 }
3358
3359 /* Wait for carrier detect and the line to become
3360 * free (i.e., not in use by the callout). While we are in
3361 * this loop, info->count is dropped by one, so that
3362 * mgsl_close() knows when to free things. We restore it upon
3363 * exit, either normal or abnormal.
3364 */
3365
3366 retval = 0;
3367 add_wait_queue(&info->open_wait, &wait);
3368
3369 if (debug_level >= DEBUG_LEVEL_INFO)
3370 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3371 __FILE__,__LINE__, tty->driver.name, info->count );
3372
3373 save_flags(flags); cli();
3374 if (!tty_hung_up_p(filp)) {
3375 extra_count = 1;
3376 info->count--;
3377 }
3378 restore_flags(flags);
3379 info->blocked_open++;
3380
3381 while (1) {
3382 if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
3383 (tty->termios->c_cflag & CBAUD)) {
3384 spin_lock_irqsave(&info->irq_spinlock,flags);
3385 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3386 usc_set_serial_signals(info);
3387 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3388 }
3389
3390 set_current_state(TASK_INTERRUPTIBLE);
3391
3392 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3393 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3394 -EAGAIN : -ERESTARTSYS;
3395 break;
3396 }
3397
3398 spin_lock_irqsave(&info->irq_spinlock,flags);
3399 usc_get_serial_signals(info);
3400 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3401
3402 if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
3403 !(info->flags & ASYNC_CLOSING) &&
3404 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3405 break;
3406 }
3407
3408 if (signal_pending(current)) {
3409 retval = -ERESTARTSYS;
3410 break;
3411 }
3412
3413 if (debug_level >= DEBUG_LEVEL_INFO)
3414 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3415 __FILE__,__LINE__, tty->driver.name, info->count );
3416
3417 schedule();
3418 }
3419
3420 set_current_state(TASK_RUNNING);
3421 remove_wait_queue(&info->open_wait, &wait);
3422
3423 if (extra_count)
3424 info->count++;
3425 info->blocked_open--;
3426
3427 if (debug_level >= DEBUG_LEVEL_INFO)
3428 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3429 __FILE__,__LINE__, tty->driver.name, info->count );
3430
3431 if (!retval)
3432 info->flags |= ASYNC_NORMAL_ACTIVE;
3433
3434 return retval;
3435
3436 } /* end of block_til_ready() */
3437
3438 /* mgsl_open()
3439 *
3440 * Called when a port is opened. Init and enable port.
3441 * Perform serial-specific initialization for the tty structure.
3442 *
3443 * Arguments: tty pointer to tty info structure
3444 * filp associated file pointer
3445 *
3446 * Return Value: 0 if success, otherwise error code
3447 */
3448 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3449 {
3450 struct mgsl_struct *info;
3451 int retval, line;
3452 unsigned long page;
3453 unsigned long flags;
3454
3455 /* verify range of specified line number */
3456 line = MINOR(tty->device) - tty->driver.minor_start;
3457 if ((line < 0) || (line >= mgsl_device_count)) {
3458 printk("%s(%d):mgsl_open with illegal line #%d.\n",
3459 __FILE__,__LINE__,line);
3460 return -ENODEV;
3461 }
3462
3463 /* find the info structure for the specified line */
3464 info = mgsl_device_list;
3465 while(info && info->line != line)
3466 info = info->next_device;
3467 if ( !info ){
3468 printk("%s(%d):Can't find specified device on open (line=%d)\n",
3469 __FILE__,__LINE__,line);
3470 return -ENODEV;
3471 }
3472
3473 tty->driver_data = info;
3474 info->tty = tty;
3475 if (mgsl_paranoia_check(info, tty->device, "mgsl_open"))
3476 return -ENODEV;
3477
3478 if (debug_level >= DEBUG_LEVEL_INFO)
3479 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3480 __FILE__,__LINE__,tty->driver.name, info->count);
3481
3482 MOD_INC_USE_COUNT;
3483
3484 /* If port is closing, signal caller to try again */
3485 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3486 if (info->flags & ASYNC_CLOSING)
3487 interruptible_sleep_on(&info->close_wait);
3488 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3489 -EAGAIN : -ERESTARTSYS);
3490 goto cleanup;
3491 }
3492
3493 if (!tmp_buf) {
3494 page = get_free_page(GFP_KERNEL);
3495 if (!page) {
3496 retval = -ENOMEM;
3497 goto cleanup;
3498 }
3499 if (tmp_buf)
3500 free_page(page);
3501 else
3502 tmp_buf = (unsigned char *) page;
3503 }
3504
3505 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3506
3507 spin_lock_irqsave(&info->netlock, flags);
3508 if (info->netcount) {
3509 retval = -EBUSY;
3510 spin_unlock_irqrestore(&info->netlock, flags);
3511 goto cleanup;
3512 }
3513 info->count++;
3514 spin_unlock_irqrestore(&info->netlock, flags);
3515
3516 if (info->count == 1) {
3517 /* 1st open on this device, init hardware */
3518 retval = startup(info);
3519 if (retval < 0)
3520 goto cleanup;
3521 }
3522
3523 retval = block_til_ready(tty, filp, info);
3524 if (retval) {
3525 if (debug_level >= DEBUG_LEVEL_INFO)
3526 printk("%s(%d):block_til_ready(%s) returned %d\n",
3527 __FILE__,__LINE__, info->device_name, retval);
3528 goto cleanup;
3529 }
3530
3531 if ((info->count == 1) &&
3532 info->flags & ASYNC_SPLIT_TERMIOS) {
3533 if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
3534 *tty->termios = info->normal_termios;
3535 else
3536 *tty->termios = info->callout_termios;
3537 mgsl_change_params(info);
3538 }
3539
3540 info->session = current->session;
3541 info->pgrp = current->pgrp;
3542
3543 if (debug_level >= DEBUG_LEVEL_INFO)
3544 printk("%s(%d):mgsl_open(%s) success\n",
3545 __FILE__,__LINE__, info->device_name);
3546 retval = 0;
3547
3548 cleanup:
3549 if (retval) {
3550 if(MOD_IN_USE)
3551 MOD_DEC_USE_COUNT;
3552 if(info->count)
3553 info->count--;
3554 }
3555
3556 return retval;
3557
3558 } /* end of mgsl_open() */
3559
3560 /*
3561 * /proc fs routines....
3562 */
3563
3564 static inline int line_info(char *buf, struct mgsl_struct *info)
3565 {
3566 char stat_buf[30];
3567 int ret;
3568 unsigned long flags;
3569
3570 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3571 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3572 info->device_name, info->io_base, info->irq_level,
3573 info->phys_memory_base, info->phys_lcr_base);
3574 } else {
3575 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3576 info->device_name, info->io_base,
3577 info->irq_level, info->dma_level);
3578 }
3579
3580 /* output current serial signal states */
3581 spin_lock_irqsave(&info->irq_spinlock,flags);
3582 usc_get_serial_signals(info);
3583 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3584
3585 stat_buf[0] = 0;
3586 stat_buf[1] = 0;
3587 if (info->serial_signals & SerialSignal_RTS)
3588 strcat(stat_buf, "|RTS");
3589 if (info->serial_signals & SerialSignal_CTS)
3590 strcat(stat_buf, "|CTS");
3591 if (info->serial_signals & SerialSignal_DTR)
3592 strcat(stat_buf, "|DTR");
3593 if (info->serial_signals & SerialSignal_DSR)
3594 strcat(stat_buf, "|DSR");
3595 if (info->serial_signals & SerialSignal_DCD)
3596 strcat(stat_buf, "|CD");
3597 if (info->serial_signals & SerialSignal_RI)
3598 strcat(stat_buf, "|RI");
3599
3600 if (info->params.mode == MGSL_MODE_HDLC) {
3601 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3602 info->icount.txok, info->icount.rxok);
3603 if (info->icount.txunder)
3604 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3605 if (info->icount.txabort)
3606 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3607 if (info->icount.rxshort)
3608 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3609 if (info->icount.rxlong)
3610 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3611 if (info->icount.rxover)
3612 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3613 if (info->icount.rxcrc)
3614 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
3615 } else {
3616 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3617 info->icount.tx, info->icount.rx);
3618 if (info->icount.frame)
3619 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3620 if (info->icount.parity)
3621 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3622 if (info->icount.brk)
3623 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3624 if (info->icount.overrun)
3625 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3626 }
3627
3628 /* Append serial signal status to end */
3629 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3630
3631 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3632 info->tx_active,info->bh_requested,info->bh_running,
3633 info->pending_bh);
3634
3635 spin_lock_irqsave(&info->irq_spinlock,flags);
3636 {
3637 u16 Tcsr = usc_InReg( info, TCSR );
3638 u16 Tdmr = usc_InDmaReg( info, TDMR );
3639 u16 Ticr = usc_InReg( info, TICR );
3640 u16 Rscr = usc_InReg( info, RCSR );
3641 u16 Rdmr = usc_InDmaReg( info, RDMR );
3642 u16 Ricr = usc_InReg( info, RICR );
3643 u16 Icr = usc_InReg( info, ICR );
3644 u16 Dccr = usc_InReg( info, DCCR );
3645 u16 Tmr = usc_InReg( info, TMR );
3646 u16 Tccr = usc_InReg( info, TCCR );
3647 u16 Ccar = inw( info->io_base + CCAR );
3648 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3649 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3650 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3651 }
3652 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3653
3654 return ret;
3655
3656 } /* end of line_info() */
3657
3658 /* mgsl_read_proc()
3659 *
3660 * Called to print information about devices
3661 *
3662 * Arguments:
3663 * page page of memory to hold returned info
3664 * start
3665 * off
3666 * count
3667 * eof
3668 * data
3669 *
3670 * Return Value:
3671 */
3672 int mgsl_read_proc(char *page, char **start, off_t off, int count,
3673 int *eof, void *data)
3674 {
3675 int len = 0, l;
3676 off_t begin = 0;
3677 struct mgsl_struct *info;
3678
3679 len += sprintf(page, "synclink driver:%s\n", driver_version);
3680
3681 info = mgsl_device_list;
3682 while( info ) {
3683 l = line_info(page + len, info);
3684 len += l;
3685 if (len+begin > off+count)
3686 goto done;
3687 if (len+begin < off) {
3688 begin += len;
3689 len = 0;
3690 }
3691 info = info->next_device;
3692 }
3693
3694 *eof = 1;
3695 done:
3696 if (off >= len+begin)
3697 return 0;
3698 *start = page + (off-begin);
3699 return ((count < begin+len-off) ? count : begin+len-off);
3700
3701 } /* end of mgsl_read_proc() */
3702
3703 /* mgsl_allocate_dma_buffers()
3704 *
3705 * Allocate and format DMA buffers (ISA adapter)
3706 * or format shared memory buffers (PCI adapter).
3707 *
3708 * Arguments: info pointer to device instance data
3709 * Return Value: 0 if success, otherwise error
3710 */
3711 int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3712 {
3713 unsigned short BuffersPerFrame;
3714
3715 info->last_mem_alloc = 0;
3716
3717 /* Calculate the number of DMA buffers necessary to hold the */
3718 /* largest allowable frame size. Note: If the max frame size is */
3719 /* not an even multiple of the DMA buffer size then we need to */
3720 /* round the buffer count per frame up one. */
3721
3722 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3723 if ( info->max_frame_size % DMABUFFERSIZE )
3724 BuffersPerFrame++;
3725
3726 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3727 /*
3728 * The PCI adapter has 256KBytes of shared memory to use.
3729 * This is 64 PAGE_SIZE buffers.
3730 *
3731 * The first page is used for padding at this time so the
3732 * buffer list does not begin at offset 0 of the PCI
3733 * adapter's shared memory.
3734 *
3735 * The 2nd page is used for the buffer list. A 4K buffer
3736 * list can hold 128 DMA_BUFFER structures at 32 bytes
3737 * each.
3738 *
3739 * This leaves 62 4K pages.
3740 *
3741 * The next N pages are used for a transmit frame. We
3742 * reserve enough 4K page blocks to hold the configured
3743 * MaxFrameSize
3744 *
3745 * Of the remaining pages (62-N), determine how many can
3746 * be used to receive full MaxFrameSize inbound frames
3747 */
3748
3749 info->tx_buffer_count = BuffersPerFrame;
3750 info->rx_buffer_count = 62 - info->tx_buffer_count;
3751 } else {
3752 /* Calculate the number of PAGE_SIZE buffers needed for */
3753 /* receive and transmit DMA buffers. */
3754
3755
3756 /* Calculate the number of DMA buffers necessary to */
3757 /* hold 7 max size receive frames and one max size transmit frame. */
3758 /* The receive buffer count is bumped by one so we avoid an */
3759 /* End of List condition if all receive buffers are used when */
3760 /* using linked list DMA buffers. */
3761
3762 info->tx_buffer_count = BuffersPerFrame;
3763 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3764
3765 /*
3766 * limit total TxBuffers & RxBuffers to 62 4K total
3767 * (ala PCI Allocation)
3768 */
3769
3770 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3771 info->rx_buffer_count = 62 - info->tx_buffer_count;
3772
3773 }
3774
3775 if ( debug_level >= DEBUG_LEVEL_INFO )
3776 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3777 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3778
3779 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3780 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3781 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3782 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ) {
3783 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3784 return -ENOMEM;
3785 }
3786
3787 mgsl_reset_rx_dma_buffers( info );
3788
3789 return 0;
3790
3791 } /* end of mgsl_allocate_dma_buffers() */
3792
3793 /*
3794 * mgsl_alloc_buffer_list_memory()
3795 *
3796 * Allocate a common DMA buffer for use as the
3797 * receive and transmit buffer lists.
3798 *
3799 * A buffer list is a set of buffer entries where each entry contains
3800 * a pointer to an actual buffer and a pointer to the next buffer entry
3801 * (plus some other info about the buffer).
3802 *
3803 * The buffer entries for a list are built to form a circular list so
3804 * that when the entire list has been traversed you start back at the
3805 * beginning.
3806 *
3807 * This function allocates memory for just the buffer entries.
3808 * The links (pointer to next entry) are filled in with the physical
3809 * address of the next entry so the adapter can navigate the list
3810 * using bus master DMA. The pointers to the actual buffers are filled
3811 * out later when the actual buffers are allocated.
3812 *
3813 * Arguments: info pointer to device instance data
3814 * Return Value: 0 if success, otherwise error
3815 */
3816 int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3817 {
3818 unsigned int i;
3819
3820 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3821 /* PCI adapter uses shared memory. */
3822 info->buffer_list = info->memory_base + info->last_mem_alloc;
3823 info->buffer_list_phys = info->last_mem_alloc;
3824 info->last_mem_alloc += BUFFERLISTSIZE;
3825 } else {
3826 /* ISA adapter uses system memory. */
3827 /* The buffer lists are allocated as a common buffer that both */
3828 /* the processor and adapter can access. This allows the driver to */
3829 /* inspect portions of the buffer while other portions are being */
3830 /* updated by the adapter using Bus Master DMA. */
3831
3832 info->buffer_list = kmalloc(BUFFERLISTSIZE, GFP_KERNEL | GFP_DMA);
3833 if ( info->buffer_list == NULL )
3834 return -ENOMEM;
3835
3836 info->buffer_list_phys = virt_to_bus(info->buffer_list);
3837 }
3838
3839 /* We got the memory for the buffer entry lists. */
3840 /* Initialize the memory block to all zeros. */
3841 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3842
3843 /* Save virtual address pointers to the receive and */
3844 /* transmit buffer lists. (Receive 1st). These pointers will */
3845 /* be used by the processor to access the lists. */
3846 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3847 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3848 info->tx_buffer_list += info->rx_buffer_count;
3849
3850 /*
3851 * Build the links for the buffer entry lists such that
3852 * two circular lists are built. (Transmit and Receive).
3853 *
3854 * Note: the links are physical addresses
3855 * which are read by the adapter to determine the next
3856 * buffer entry to use.
3857 */
3858
3859 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3860 /* calculate and store physical address of this buffer entry */
3861 info->rx_buffer_list[i].phys_entry =
3862 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3863
3864 /* calculate and store physical address of */
3865 /* next entry in cirular list of entries */
3866
3867 info->rx_buffer_list[i].link = info->buffer_list_phys;
3868
3869 if ( i < info->rx_buffer_count - 1 )
3870 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3871 }
3872
3873 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3874 /* calculate and store physical address of this buffer entry */
3875 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3876 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3877
3878 /* calculate and store physical address of */
3879 /* next entry in cirular list of entries */
3880
3881 info->tx_buffer_list[i].link = info->buffer_list_phys +
3882 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3883
3884 if ( i < info->tx_buffer_count - 1 )
3885 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3886 }
3887
3888 return 0;
3889
3890 } /* end of mgsl_alloc_buffer_list_memory() */
3891
3892 /* Free DMA buffers allocated for use as the
3893 * receive and transmit buffer lists.
3894 * Warning:
3895 *
3896 * The data transfer buffers associated with the buffer list
3897 * MUST be freed before freeing the buffer list itself because
3898 * the buffer list contains the information necessary to free
3899 * the individual buffers!
3900 */
3901 void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3902 {
3903 if ( info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI )
3904 kfree(info->buffer_list);
3905
3906 info->buffer_list = NULL;
3907 info->rx_buffer_list = NULL;
3908 info->tx_buffer_list = NULL;
3909
3910 } /* end of mgsl_free_buffer_list_memory() */
3911
3912 /*
3913 * mgsl_alloc_frame_memory()
3914 *
3915 * Allocate the frame DMA buffers used by the specified buffer list.
3916 * Each DMA buffer will be one memory page in size. This is necessary
3917 * because memory can fragment enough that it may be impossible
3918 * contiguous pages.
3919 *
3920 * Arguments:
3921 *
3922 * info pointer to device instance data
3923 * BufferList pointer to list of buffer entries
3924 * Buffercount count of buffer entries in buffer list
3925 *
3926 * Return Value: 0 if success, otherwise -ENOMEM
3927 */
3928 int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3929 {
3930 int i;
3931 unsigned long phys_addr;
3932
3933 /* Allocate page sized buffers for the receive buffer list */
3934
3935 for ( i = 0; i < Buffercount; i++ ) {
3936 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3937 /* PCI adapter uses shared memory buffers. */
3938 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3939 phys_addr = info->last_mem_alloc;
3940 info->last_mem_alloc += DMABUFFERSIZE;
3941 } else {
3942 /* ISA adapter uses system memory. */
3943 BufferList[i].virt_addr =
3944 kmalloc(DMABUFFERSIZE, GFP_KERNEL | GFP_DMA);
3945 if ( BufferList[i].virt_addr == NULL )
3946 return -ENOMEM;
3947 phys_addr = virt_to_bus(BufferList[i].virt_addr);
3948 }
3949 BufferList[i].phys_addr = phys_addr;
3950 }
3951
3952 return 0;
3953
3954 } /* end of mgsl_alloc_frame_memory() */
3955
3956 /*
3957 * mgsl_free_frame_memory()
3958 *
3959 * Free the buffers associated with
3960 * each buffer entry of a buffer list.
3961 *
3962 * Arguments:
3963 *
3964 * info pointer to device instance data
3965 * BufferList pointer to list of buffer entries
3966 * Buffercount count of buffer entries in buffer list
3967 *
3968 * Return Value: None
3969 */
3970 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3971 {
3972 int i;
3973
3974 if ( BufferList ) {
3975 for ( i = 0 ; i < Buffercount ; i++ ) {
3976 if ( BufferList[i].virt_addr ) {
3977 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3978 kfree(BufferList[i].virt_addr);
3979 BufferList[i].virt_addr = NULL;
3980 }
3981 }
3982 }
3983
3984 } /* end of mgsl_free_frame_memory() */
3985
3986 /* mgsl_free_dma_buffers()
3987 *
3988 * Free DMA buffers
3989 *
3990 * Arguments: info pointer to device instance data
3991 * Return Value: None
3992 */
3993 void mgsl_free_dma_buffers( struct mgsl_struct *info )
3994 {
3995 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3996 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3997 mgsl_free_buffer_list_memory( info );
3998
3999 } /* end of mgsl_free_dma_buffers() */
4000
4001
4002 /*
4003 * mgsl_alloc_intermediate_rxbuffer_memory()
4004 *
4005 * Allocate a buffer large enough to hold max_frame_size. This buffer
4006 * is used to pass an assembled frame to the line discipline.
4007 *
4008 * Arguments:
4009 *
4010 * info pointer to device instance data
4011 *
4012 * Return Value: 0 if success, otherwise -ENOMEM
4013 */
4014 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4015 {
4016 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
4017 if ( info->intermediate_rxbuffer == NULL )
4018 return -ENOMEM;
4019
4020 return 0;
4021
4022 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4023
4024 /*
4025 * mgsl_free_intermediate_rxbuffer_memory()
4026 *
4027 *
4028 * Arguments:
4029 *
4030 * info pointer to device instance data
4031 *
4032 * Return Value: None
4033 */
4034 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4035 {
4036 if ( info->intermediate_rxbuffer )
4037 kfree(info->intermediate_rxbuffer);
4038
4039 info->intermediate_rxbuffer = NULL;
4040
4041 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4042
4043 int mgsl_claim_resources(struct mgsl_struct *info)
4044 {
4045 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4046 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4047 __FILE__,__LINE__,info->device_name, info->io_base);
4048 return -ENODEV;
4049 }
4050 info->io_addr_requested = 1;
4051
4052 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4053 info->device_name, info ) < 0 ) {
4054 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4055 __FILE__,__LINE__,info->device_name, info->irq_level );
4056 goto errout;
4057 }
4058 info->irq_requested = 1;
4059
4060 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4061 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4062 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4063 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4064 goto errout;
4065 }
4066 info->shared_mem_requested = 1;
4067 if (request_mem_region(info->phys_lcr_base,128,"synclink") == NULL) {
4068 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4069 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
4070 goto errout;
4071 }
4072 info->lcr_mem_requested = 1;
4073
4074 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4075 if (!info->memory_base) {
4076 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4077 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4078 goto errout;
4079 }
4080
4081 if ( !mgsl_memory_test(info) ) {
4082 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4083 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4084 goto errout;
4085 }
4086
4087 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4088 if (!info->lcr_base) {
4089 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4090 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4091 goto errout;
4092 }
4093
4094 } else {
4095 /* claim DMA channel */
4096
4097 if (request_dma(info->dma_level,info->device_name) < 0){
4098 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4099 __FILE__,__LINE__,info->device_name, info->dma_level );
4100 mgsl_release_resources( info );
4101 return -ENODEV;
4102 }
4103 info->dma_requested = 1;
4104
4105 /* ISA adapter uses bus master DMA */
4106 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4107 enable_dma(info->dma_level);
4108 }
4109
4110 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4111 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4112 __FILE__,__LINE__,info->device_name, info->dma_level );
4113 goto errout;
4114 }
4115
4116 return 0;
4117 errout:
4118 mgsl_release_resources(info);
4119 return ENODEV;
4120
4121 } /* end of mgsl_claim_resources() */
4122
4123 void mgsl_release_resources(struct mgsl_struct *info)
4124 {
4125 if ( debug_level >= DEBUG_LEVEL_INFO )
4126 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4127 __FILE__,__LINE__,info->device_name );
4128
4129 if ( info->irq_requested ) {
4130 free_irq(info->irq_level, info);
4131 info->irq_requested = 0;
4132 }
4133 if ( info->dma_requested ) {
4134 disable_dma(info->dma_level);
4135 free_dma(info->dma_level);
4136 info->dma_requested = 0;
4137 }
4138 mgsl_free_dma_buffers(info);
4139 mgsl_free_intermediate_rxbuffer_memory(info);
4140
4141 if ( info->io_addr_requested ) {
4142 release_region(info->io_base,info->io_addr_size);
4143 info->io_addr_requested = 0;
4144 }
4145 if ( info->shared_mem_requested ) {
4146 release_mem_region(info->phys_memory_base,0x40000);
4147 info->shared_mem_requested = 0;
4148 }
4149 if ( info->lcr_mem_requested ) {
4150 release_mem_region(info->phys_lcr_base,128);
4151 info->lcr_mem_requested = 0;
4152 }
4153 if (info->memory_base){
4154 iounmap(info->memory_base);
4155 info->memory_base = 0;
4156 }
4157 if (info->lcr_base){
4158 iounmap(info->lcr_base - info->lcr_offset);
4159 info->lcr_base = 0;
4160 }
4161
4162 if ( debug_level >= DEBUG_LEVEL_INFO )
4163 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4164 __FILE__,__LINE__,info->device_name );
4165
4166 } /* end of mgsl_release_resources() */
4167
4168 /* mgsl_add_device()
4169 *
4170 * Add the specified device instance data structure to the
4171 * global linked list of devices and increment the device count.
4172 *
4173 * Arguments: info pointer to device instance data
4174 * Return Value: None
4175 */
4176 void mgsl_add_device( struct mgsl_struct *info )
4177 {
4178 info->next_device = NULL;
4179 info->line = mgsl_device_count;
4180 sprintf(info->device_name,"ttySL%d",info->line);
4181
4182 if (info->line < MAX_TOTAL_DEVICES) {
4183 if (maxframe[info->line])
4184 info->max_frame_size = maxframe[info->line];
4185 info->dosyncppp = dosyncppp[info->line];
4186 }
4187
4188 mgsl_device_count++;
4189
4190 if ( !mgsl_device_list )
4191 mgsl_device_list = info;
4192 else {
4193 struct mgsl_struct *current_dev = mgsl_device_list;
4194 while( current_dev->next_device )
4195 current_dev = current_dev->next_device;
4196 current_dev->next_device = info;
4197 }
4198
4199 if ( info->max_frame_size < 4096 )
4200 info->max_frame_size = 4096;
4201 else if ( info->max_frame_size > 65535 )
4202 info->max_frame_size = 65535;
4203
4204 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4205 printk( "SyncLink device %s added:PCI bus IO=%04X IRQ=%d Mem=%08X LCR=%08X MaxFrameSize=%u\n",
4206 info->device_name, info->io_base, info->irq_level,
4207 info->phys_memory_base, info->phys_lcr_base,
4208 info->max_frame_size );
4209 } else {
4210 printk( "SyncLink device %s added:ISA bus IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4211 info->device_name, info->io_base, info->irq_level, info->dma_level,
4212 info->max_frame_size );
4213 }
4214
4215 #ifdef CONFIG_SYNCLINK_SYNCPPP
4216 if (info->dosyncppp)
4217 mgsl_sppp_init(info);
4218 #endif
4219 } /* end of mgsl_add_device() */
4220
4221 /* mgsl_allocate_device()
4222 *
4223 * Allocate and initialize a device instance structure
4224 *
4225 * Arguments: none
4226 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4227 */
4228 struct mgsl_struct* mgsl_allocate_device()
4229 {
4230 struct mgsl_struct *info;
4231
4232 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4233 GFP_KERNEL);
4234
4235 if (!info) {
4236 printk("Error can't allocate device instance data\n");
4237 } else {
4238 memset(info, 0, sizeof(struct mgsl_struct));
4239 info->magic = MGSL_MAGIC;
4240 info->task.sync = 0;
4241 info->task.routine = mgsl_bh_handler;
4242 info->task.data = info;
4243 info->max_frame_size = 4096;
4244 info->close_delay = 5*HZ/10;
4245 info->closing_wait = 30*HZ;
4246 init_waitqueue_head(&info->open_wait);
4247 init_waitqueue_head(&info->close_wait);
4248 init_waitqueue_head(&info->status_event_wait_q);
4249 init_waitqueue_head(&info->event_wait_q);
4250 spin_lock_init(&info->irq_spinlock);
4251 spin_lock_init(&info->netlock);
4252 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4253 info->idle_mode = HDLC_TXIDLE_FLAGS;
4254 }
4255
4256 return info;
4257
4258 } /* end of mgsl_allocate_device()*/
4259
4260 /*
4261 * perform tty device initialization
4262 */
4263 int mgsl_init_tty(void);
4264 int mgsl_init_tty()
4265 {
4266 struct mgsl_struct *info;
4267
4268 memset(serial_table,0,sizeof(struct tty_struct*)*MAX_TOTAL_DEVICES);
4269 memset(serial_termios,0,sizeof(struct termios*)*MAX_TOTAL_DEVICES);
4270 memset(serial_termios_locked,0,sizeof(struct termios*)*MAX_TOTAL_DEVICES);
4271
4272 /* Initialize the tty_driver structure */
4273
4274 memset(&serial_driver, 0, sizeof(struct tty_driver));
4275 serial_driver.magic = TTY_DRIVER_MAGIC;
4276 serial_driver.driver_name = "synclink";
4277 serial_driver.name = "ttySL";
4278 serial_driver.major = ttymajor;
4279 serial_driver.minor_start = 64;
4280 serial_driver.num = mgsl_device_count;
4281 serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
4282 serial_driver.subtype = SERIAL_TYPE_NORMAL;
4283 serial_driver.init_termios = tty_std_termios;
4284 serial_driver.init_termios.c_cflag =
4285 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4286 serial_driver.flags = TTY_DRIVER_REAL_RAW;
4287 serial_driver.refcount = &serial_refcount;
4288 serial_driver.table = serial_table;
4289 serial_driver.termios = serial_termios;
4290 serial_driver.termios_locked = serial_termios_locked;
4291
4292 serial_driver.open = mgsl_open;
4293 serial_driver.close = mgsl_close;
4294 serial_driver.write = mgsl_write;
4295 serial_driver.put_char = mgsl_put_char;
4296 serial_driver.flush_chars = mgsl_flush_chars;
4297 serial_driver.write_room = mgsl_write_room;
4298 serial_driver.chars_in_buffer = mgsl_chars_in_buffer;
4299 serial_driver.flush_buffer = mgsl_flush_buffer;
4300 serial_driver.ioctl = mgsl_ioctl;
4301 serial_driver.throttle = mgsl_throttle;
4302 serial_driver.unthrottle = mgsl_unthrottle;
4303 serial_driver.send_xchar = mgsl_send_xchar;
4304 serial_driver.break_ctl = mgsl_break;
4305 serial_driver.wait_until_sent = mgsl_wait_until_sent;
4306 serial_driver.read_proc = mgsl_read_proc;
4307 serial_driver.set_termios = mgsl_set_termios;
4308 serial_driver.stop = mgsl_stop;
4309 serial_driver.start = mgsl_start;
4310 serial_driver.hangup = mgsl_hangup;
4311
4312 /*
4313 * The callout device is just like normal device except for
4314 * major number and the subtype code.
4315 */
4316 callout_driver = serial_driver;
4317 callout_driver.name = "cuaSL";
4318 callout_driver.major = cuamajor;
4319 callout_driver.subtype = SERIAL_TYPE_CALLOUT;
4320 callout_driver.read_proc = 0;
4321 callout_driver.proc_entry = 0;
4322
4323 if (tty_register_driver(&serial_driver) < 0)
4324 printk("%s(%d):Couldn't register serial driver\n",
4325 __FILE__,__LINE__);
4326
4327 if (tty_register_driver(&callout_driver) < 0)
4328 printk("%s(%d):Couldn't register callout driver\n",
4329 __FILE__,__LINE__);
4330
4331 printk("%s version %s, tty major#%d callout major#%d\n",
4332 driver_name, driver_version,
4333 serial_driver.major, callout_driver.major);
4334
4335 /* Propagate these values to all device instances */
4336
4337 info = mgsl_device_list;
4338 while(info){
4339 info->callout_termios = callout_driver.init_termios;
4340 info->normal_termios = serial_driver.init_termios;
4341 info = info->next_device;
4342 }
4343
4344 return 0;
4345 }
4346
4347 /* enumerate user specified ISA adapters
4348 */
4349 int mgsl_enum_isa_devices()
4350 {
4351 struct mgsl_struct *info;
4352 int i;
4353
4354 /* Check for user specified ISA devices */
4355
4356 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4357 if ( debug_level >= DEBUG_LEVEL_INFO )
4358 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4359 io[i], irq[i], dma[i] );
4360
4361 info = mgsl_allocate_device();
4362 if ( !info ) {
4363 /* error allocating device instance data */
4364 if ( debug_level >= DEBUG_LEVEL_ERROR )
4365 printk( "can't allocate device instance data.\n");
4366 continue;
4367 }
4368
4369 /* Copy user configuration info to device instance data */
4370 info->io_base = (unsigned int)io[i];
4371 info->irq_level = (unsigned int)irq[i];
4372 info->irq_level = irq_cannonicalize(info->irq_level);
4373 info->dma_level = (unsigned int)dma[i];
4374 info->bus_type = MGSL_BUS_TYPE_ISA;
4375 info->io_addr_size = 16;
4376 info->irq_flags = 0;
4377
4378 mgsl_add_device( info );
4379 }
4380
4381 return 0;
4382 }
4383
4384 /* mgsl_init()
4385 *
4386 * Driver initialization entry point.
4387 *
4388 * Arguments: None
4389 * Return Value: 0 if success, otherwise error code
4390 */
4391 int __init mgsl_init(void)
4392 {
4393 int rc;
4394
4395 EXPORT_NO_SYMBOLS;
4396
4397 printk("%s version %s\n", driver_name, driver_version);
4398
4399 mgsl_enum_isa_devices();
4400 pci_register_driver(&synclink_pci_driver);
4401
4402 if ( !mgsl_device_list ) {
4403 printk("%s(%d):No SyncLink devices found.\n",__FILE__,__LINE__);
4404 return -ENODEV;
4405 }
4406 if ((rc = mgsl_init_tty()))
4407 return rc;
4408
4409 return 0;
4410 }
4411
4412 static int __init synclink_init(void)
4413 {
4414 /* Uncomment this to kernel debug module.
4415 * mgsl_get_text_ptr() leaves the .text address in eax
4416 * which can be used with add-symbol-file with gdb.
4417 */
4418 if (break_on_load) {
4419 mgsl_get_text_ptr();
4420 BREAKPOINT();
4421 }
4422
4423 return mgsl_init();
4424 }
4425
4426 static void __exit synclink_exit(void)
4427 {
4428 unsigned long flags;
4429 int rc;
4430 struct mgsl_struct *info;
4431
4432 printk("Unloading %s: version %s\n", driver_name, driver_version);
4433 save_flags(flags);
4434 cli();
4435 if ((rc = tty_unregister_driver(&serial_driver)))
4436 printk("%s(%d) failed to unregister tty driver err=%d\n",
4437 __FILE__,__LINE__,rc);
4438 if ((rc = tty_unregister_driver(&callout_driver)))
4439 printk("%s(%d) failed to unregister callout driver err=%d\n",
4440 __FILE__,__LINE__,rc);
4441 restore_flags(flags);
4442
4443 info = mgsl_device_list;
4444 while(info) {
4445 #ifdef CONFIG_SYNCLINK_SYNCPPP
4446 if (info->dosyncppp)
4447 mgsl_sppp_delete(info);
4448 #endif
4449 mgsl_release_resources(info);
4450 info = info->next_device;
4451 }
4452
4453 if (tmp_buf) {
4454 free_page((unsigned long) tmp_buf);
4455 tmp_buf = NULL;
4456 }
4457
4458 pci_unregister_driver(&synclink_pci_driver);
4459 }
4460
4461 module_init(synclink_init);
4462 module_exit(synclink_exit);
4463
4464 /*
4465 * usc_RTCmd()
4466 *
4467 * Issue a USC Receive/Transmit command to the
4468 * Channel Command/Address Register (CCAR).
4469 *
4470 * Notes:
4471 *
4472 * The command is encoded in the most significant 5 bits <15..11>
4473 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4474 * and Bits <6..0> must be written as zeros.
4475 *
4476 * Arguments:
4477 *
4478 * info pointer to device information structure
4479 * Cmd command mask (use symbolic macros)
4480 *
4481 * Return Value:
4482 *
4483 * None
4484 */
4485 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4486 {
4487 /* output command to CCAR in bits <15..11> */
4488 /* preserve bits <10..7>, bits <6..0> must be zero */
4489
4490 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4491
4492 /* Read to flush write to CCAR */
4493 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4494 inw( info->io_base + CCAR );
4495
4496 } /* end of usc_RTCmd() */
4497
4498 /*
4499 * usc_DmaCmd()
4500 *
4501 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4502 *
4503 * Arguments:
4504 *
4505 * info pointer to device information structure
4506 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4507 *
4508 * Return Value:
4509 *
4510 * None
4511 */
4512 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4513 {
4514 /* write command mask to DCAR */
4515 outw( Cmd + info->mbre_bit, info->io_base );
4516
4517 /* Read to flush write to DCAR */
4518 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4519 inw( info->io_base );
4520
4521 } /* end of usc_DmaCmd() */
4522
4523 /*
4524 * usc_OutDmaReg()
4525 *
4526 * Write a 16-bit value to a USC DMA register
4527 *
4528 * Arguments:
4529 *
4530 * info pointer to device info structure
4531 * RegAddr register address (number) for write
4532 * RegValue 16-bit value to write to register
4533 *
4534 * Return Value:
4535 *
4536 * None
4537 *
4538 */
4539 void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4540 {
4541 /* Note: The DCAR is located at the adapter base address */
4542 /* Note: must preserve state of BIT8 in DCAR */
4543
4544 outw( RegAddr + info->mbre_bit, info->io_base );
4545 outw( RegValue, info->io_base );
4546
4547 /* Read to flush write to DCAR */
4548 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4549 inw( info->io_base );
4550
4551 } /* end of usc_OutDmaReg() */
4552
4553 /*
4554 * usc_InDmaReg()
4555 *
4556 * Read a 16-bit value from a DMA register
4557 *
4558 * Arguments:
4559 *
4560 * info pointer to device info structure
4561 * RegAddr register address (number) to read from
4562 *
4563 * Return Value:
4564 *
4565 * The 16-bit value read from register
4566 *
4567 */
4568 u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4569 {
4570 /* Note: The DCAR is located at the adapter base address */
4571 /* Note: must preserve state of BIT8 in DCAR */
4572
4573 outw( RegAddr + info->mbre_bit, info->io_base );
4574 return inw( info->io_base );
4575
4576 } /* end of usc_InDmaReg() */
4577
4578 /*
4579 *
4580 * usc_OutReg()
4581 *
4582 * Write a 16-bit value to a USC serial channel register
4583 *
4584 * Arguments:
4585 *
4586 * info pointer to device info structure
4587 * RegAddr register address (number) to write to
4588 * RegValue 16-bit value to write to register
4589 *
4590 * Return Value:
4591 *
4592 * None
4593 *
4594 */
4595 void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4596 {
4597 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4598 outw( RegValue, info->io_base + CCAR );
4599
4600 /* Read to flush write to CCAR */
4601 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4602 inw( info->io_base + CCAR );
4603
4604 } /* end of usc_OutReg() */
4605
4606 /*
4607 * usc_InReg()
4608 *
4609 * Reads a 16-bit value from a USC serial channel register
4610 *
4611 * Arguments:
4612 *
4613 * info pointer to device extension
4614 * RegAddr register address (number) to read from
4615 *
4616 * Return Value:
4617 *
4618 * 16-bit value read from register
4619 */
4620 u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4621 {
4622 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4623 return inw( info->io_base + CCAR );
4624
4625 } /* end of usc_InReg() */
4626
4627 /* usc_set_sdlc_mode()
4628 *
4629 * Set up the adapter for SDLC DMA communications.
4630 *
4631 * Arguments: info pointer to device instance data
4632 * Return Value: NONE
4633 */
4634 void usc_set_sdlc_mode( struct mgsl_struct *info )
4635 {
4636 u16 RegValue;
4637 int PreSL1660;
4638
4639 /*
4640 * determine if the IUSC on the adapter is pre-SL1660. If
4641 * not, take advantage of the UnderWait feature of more
4642 * modern chips. If an underrun occurs and this bit is set,
4643 * the transmitter will idle the programmed idle pattern
4644 * until the driver has time to service the underrun. Otherwise,
4645 * the dma controller may get the cycles previously requested
4646 * and begin transmitting queued tx data.
4647 */
4648 usc_OutReg(info,TMCR,0x1f);
4649 RegValue=usc_InReg(info,TMDR);
4650 if ( RegValue == IUSC_PRE_SL1660 )
4651 PreSL1660 = 1;
4652 else
4653 PreSL1660 = 0;
4654
4655
4656 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4657 {
4658 /*
4659 ** Channel Mode Register (CMR)
4660 **
4661 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4662 ** <13> 0 0 = Transmit Disabled (initially)
4663 ** <12> 0 1 = Consecutive Idles share common 0
4664 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4665 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4666 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4667 **
4668 ** 1000 1110 0000 0110 = 0x8e06
4669 */
4670 RegValue = 0x8e06;
4671
4672 /*--------------------------------------------------
4673 * ignore user options for UnderRun Actions and
4674 * preambles
4675 *--------------------------------------------------*/
4676 }
4677 else
4678 {
4679 /* Channel mode Register (CMR)
4680 *
4681 * <15..14> 00 Tx Sub modes, Underrun Action
4682 * <13> 0 1 = Send Preamble before opening flag
4683 * <12> 0 1 = Consecutive Idles share common 0
4684 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4685 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4686 * <3..0> 0110 Receiver mode = HDLC/SDLC
4687 *
4688 * 0000 0110 0000 0110 = 0x0606
4689 */
4690
4691 RegValue = 0x0606;
4692
4693 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4694 RegValue |= BIT14;
4695 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4696 RegValue |= BIT15;
4697 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4698 RegValue |= BIT15 + BIT14;
4699
4700 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4701 RegValue |= BIT13;
4702 }
4703
4704 if ( info->params.flags & HDLC_FLAG_SHARE_ZERO )
4705 RegValue |= BIT12;
4706
4707 if ( info->params.addr_filter != 0xff )
4708 {
4709 /* set up receive address filtering */
4710 usc_OutReg( info, RSR, info->params.addr_filter );
4711 RegValue |= BIT4;
4712 }
4713
4714 usc_OutReg( info, CMR, RegValue );
4715 info->cmr_value = RegValue;
4716
4717 /* Receiver mode Register (RMR)
4718 *
4719 * <15..13> 000 encoding
4720 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4721 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4722 * <9> 0 1 = Include Receive chars in CRC
4723 * <8> 1 1 = Use Abort/PE bit as abort indicator
4724 * <7..6> 00 Even parity
4725 * <5> 0 parity disabled
4726 * <4..2> 000 Receive Char Length = 8 bits
4727 * <1..0> 00 Disable Receiver
4728 *
4729 * 0000 0101 0000 0000 = 0x0500
4730 */
4731
4732 RegValue = 0x0500;
4733
4734 switch ( info->params.encoding ) {
4735 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4736 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4737 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4738 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4739 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4740 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4741 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4742 }
4743
4744 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
4745 RegValue |= BIT9;
4746 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
4747 RegValue |= ( BIT12 | BIT10 | BIT9 );
4748
4749 usc_OutReg( info, RMR, RegValue );
4750
4751
4752
4753 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4754 /* When an opening flag of an SDLC frame is recognized the */
4755 /* Receive Character count (RCC) is loaded with the value in */
4756 /* RCLR. The RCC is decremented for each received byte. The */
4757 /* value of RCC is stored after the closing flag of the frame */
4758 /* allowing the frame size to be computed. */
4759
4760 usc_OutReg( info, RCLR, RCLRVALUE );
4761
4762 usc_RCmd( info, RCmd_SelectRicrdma_level );
4763
4764 /* Receive Interrupt Control Register (RICR)
4765 *
4766 * <15..8> ? RxFIFO DMA Request Level
4767 * <7> 0 Exited Hunt IA (Interrupt Arm)
4768 * <6> 0 Idle Received IA
4769 * <5> 0 Break/Abort IA
4770 * <4> 0 Rx Bound IA
4771 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4772 * <2> 0 Abort/PE IA
4773 * <1> 1 Rx Overrun IA
4774 * <0> 0 Select TC0 value for readback
4775 *
4776 * 0000 0000 0000 1000 = 0x000a
4777 */
4778
4779 /* Carry over the Exit Hunt and Idle Received bits */
4780 /* in case they have been armed by usc_ArmEvents. */
4781
4782 RegValue = usc_InReg( info, RICR ) & 0xc0;
4783
4784 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4785 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4786 else
4787 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4788
4789 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4790
4791 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4792 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4793
4794 /* Transmit mode Register (TMR)
4795 *
4796 * <15..13> 000 encoding
4797 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4798 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4799 * <9> 0 1 = Tx CRC Enabled
4800 * <8> 0 1 = Append CRC to end of transmit frame
4801 * <7..6> 00 Transmit parity Even
4802 * <5> 0 Transmit parity Disabled
4803 * <4..2> 000 Tx Char Length = 8 bits
4804 * <1..0> 00 Disable Transmitter
4805 *
4806 * 0000 0100 0000 0000 = 0x0400
4807 */
4808
4809 RegValue = 0x0400;
4810
4811 switch ( info->params.encoding ) {
4812 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4813 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4814 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4815 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4816 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4817 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4818 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4819 }
4820
4821 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
4822 RegValue |= BIT9 + BIT8;
4823 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
4824 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4825
4826 usc_OutReg( info, TMR, RegValue );
4827
4828 usc_set_txidle( info );
4829
4830
4831 usc_TCmd( info, TCmd_SelectTicrdma_level );
4832
4833 /* Transmit Interrupt Control Register (TICR)
4834 *
4835 * <15..8> ? Transmit FIFO DMA Level
4836 * <7> 0 Present IA (Interrupt Arm)
4837 * <6> 0 Idle Sent IA
4838 * <5> 1 Abort Sent IA
4839 * <4> 1 EOF/EOM Sent IA
4840 * <3> 0 CRC Sent IA
4841 * <2> 1 1 = Wait for SW Trigger to Start Frame
4842 * <1> 1 Tx Underrun IA
4843 * <0> 0 TC0 constant on read back
4844 *
4845 * 0000 0000 0011 0110 = 0x0036
4846 */
4847
4848 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4849 usc_OutReg( info, TICR, 0x0736 );
4850 else
4851 usc_OutReg( info, TICR, 0x1436 );
4852
4853 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4854 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4855
4856 /*
4857 ** Transmit Command/Status Register (TCSR)
4858 **
4859 ** <15..12> 0000 TCmd
4860 ** <11> 0/1 UnderWait
4861 ** <10..08> 000 TxIdle
4862 ** <7> x PreSent
4863 ** <6> x IdleSent
4864 ** <5> x AbortSent
4865 ** <4> x EOF/EOM Sent
4866 ** <3> x CRC Sent
4867 ** <2> x All Sent
4868 ** <1> x TxUnder
4869 ** <0> x TxEmpty
4870 **
4871 ** 0000 0000 0000 0000 = 0x0000
4872 */
4873 info->tcsr_value = 0;
4874
4875 if ( !PreSL1660 )
4876 info->tcsr_value |= TCSR_UNDERWAIT;
4877
4878 usc_OutReg( info, TCSR, info->tcsr_value );
4879
4880 /* Clock mode Control Register (CMCR)
4881 *
4882 * <15..14> 00 counter 1 Source = Disabled
4883 * <13..12> 00 counter 0 Source = Disabled
4884 * <11..10> 11 BRG1 Input is TxC Pin
4885 * <9..8> 11 BRG0 Input is TxC Pin
4886 * <7..6> 01 DPLL Input is BRG1 Output
4887 * <5..3> XXX TxCLK comes from Port 0
4888 * <2..0> XXX RxCLK comes from Port 1
4889 *
4890 * 0000 1111 0111 0111 = 0x0f77
4891 */
4892
4893 RegValue = 0x0f40;
4894
4895 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4896 RegValue |= 0x0003; /* RxCLK from DPLL */
4897 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4898 RegValue |= 0x0004; /* RxCLK from BRG0 */
4899 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4900 RegValue |= 0x0006; /* RxCLK from TXC Input */
4901 else
4902 RegValue |= 0x0007; /* RxCLK from Port1 */
4903
4904 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4905 RegValue |= 0x0018; /* TxCLK from DPLL */
4906 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4907 RegValue |= 0x0020; /* TxCLK from BRG0 */
4908 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4909 RegValue |= 0x0038; /* RxCLK from TXC Input */
4910 else
4911 RegValue |= 0x0030; /* TxCLK from Port0 */
4912
4913 usc_OutReg( info, CMCR, RegValue );
4914
4915
4916 /* Hardware Configuration Register (HCR)
4917 *
4918 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4919 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4920 * <12> 0 CVOK:0=report code violation in biphase
4921 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4922 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4923 * <7..6> 00 reserved
4924 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4925 * <4> X BRG1 Enable
4926 * <3..2> 00 reserved
4927 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4928 * <0> 0 BRG0 Enable
4929 */
4930
4931 RegValue = 0x0000;
4932
4933 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
4934 u32 XtalSpeed;
4935 u32 DpllDivisor;
4936 u16 Tc;
4937
4938 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4939 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4940
4941 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4942 XtalSpeed = 11059200;
4943 else
4944 XtalSpeed = 14745600;
4945
4946 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4947 DpllDivisor = 16;
4948 RegValue |= BIT10;
4949 }
4950 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4951 DpllDivisor = 8;
4952 RegValue |= BIT11;
4953 }
4954 else
4955 DpllDivisor = 32;
4956
4957 /* Tc = (Xtal/Speed) - 1 */
4958 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4959 /* then rounding up gives a more precise time constant. Instead */
4960 /* of rounding up and then subtracting 1 we just don't subtract */
4961 /* the one in this case. */
4962
4963 /*--------------------------------------------------
4964 * ejz: for DPLL mode, application should use the
4965 * same clock speed as the partner system, even
4966 * though clocking is derived from the input RxData.
4967 * In case the user uses a 0 for the clock speed,
4968 * default to 0xffffffff and don't try to divide by
4969 * zero
4970 *--------------------------------------------------*/
4971 if ( info->params.clock_speed )
4972 {
4973 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4974 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4975 / info->params.clock_speed) )
4976 Tc--;
4977 }
4978 else
4979 Tc = -1;
4980
4981
4982 /* Write 16-bit Time Constant for BRG1 */
4983 usc_OutReg( info, TC1R, Tc );
4984
4985 RegValue |= BIT4; /* enable BRG1 */
4986
4987 switch ( info->params.encoding ) {
4988 case HDLC_ENCODING_NRZ:
4989 case HDLC_ENCODING_NRZB:
4990 case HDLC_ENCODING_NRZI_MARK:
4991 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
4992 case HDLC_ENCODING_BIPHASE_MARK:
4993 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
4994 case HDLC_ENCODING_BIPHASE_LEVEL:
4995 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
4996 }
4997 }
4998
4999 usc_OutReg( info, HCR, RegValue );
5000
5001
5002 /* Channel Control/status Register (CCSR)
5003 *
5004 * <15> X RCC FIFO Overflow status (RO)
5005 * <14> X RCC FIFO Not Empty status (RO)
5006 * <13> 0 1 = Clear RCC FIFO (WO)
5007 * <12> X DPLL Sync (RW)
5008 * <11> X DPLL 2 Missed Clocks status (RO)
5009 * <10> X DPLL 1 Missed Clock status (RO)
5010 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5011 * <7> X SDLC Loop On status (RO)
5012 * <6> X SDLC Loop Send status (RO)
5013 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5014 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5015 * <1..0> 00 reserved
5016 *
5017 * 0000 0000 0010 0000 = 0x0020
5018 */
5019
5020 usc_OutReg( info, CCSR, 0x1020 );
5021
5022
5023 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5024 usc_OutReg( info, SICR,
5025 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5026 }
5027
5028
5029 /* enable Master Interrupt Enable bit (MIE) */
5030 usc_EnableMasterIrqBit( info );
5031
5032 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5033 TRANSMIT_STATUS + TRANSMIT_DATA );
5034
5035 info->mbre_bit = 0;
5036 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5037 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5038 info->mbre_bit = BIT8;
5039 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5040
5041 /* Enable DMAEN (Port 7, Bit 14) */
5042 /* This connects the DMA request signal to the ISA bus */
5043 /* on the ISA adapter. This has no effect for the PCI adapter */
5044 usc_OutReg( info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14) );
5045
5046 /* DMA Control Register (DCR)
5047 *
5048 * <15..14> 10 Priority mode = Alternating Tx/Rx
5049 * 01 Rx has priority
5050 * 00 Tx has priority
5051 *
5052 * <13> 1 Enable Priority Preempt per DCR<15..14>
5053 * (WARNING DCR<11..10> must be 00 when this is 1)
5054 * 0 Choose activate channel per DCR<11..10>
5055 *
5056 * <12> 0 Little Endian for Array/List
5057 * <11..10> 00 Both Channels can use each bus grant
5058 * <9..6> 0000 reserved
5059 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5060 * <4> 0 1 = drive D/C and S/D pins
5061 * <3> 1 1 = Add one wait state to all DMA cycles.
5062 * <2> 0 1 = Strobe /UAS on every transfer.
5063 * <1..0> 11 Addr incrementing only affects LS24 bits
5064 *
5065 * 0110 0000 0000 1011 = 0x600b
5066 */
5067
5068 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5069 /* PCI adapter does not need DMA wait state */
5070 usc_OutDmaReg( info, DCR, 0xa00b );
5071 }
5072 else
5073 usc_OutDmaReg( info, DCR, 0x800b );
5074
5075
5076 /* Receive DMA mode Register (RDMR)
5077 *
5078 * <15..14> 11 DMA mode = Linked List Buffer mode
5079 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5080 * <12> 1 Clear count of List Entry after fetching
5081 * <11..10> 00 Address mode = Increment
5082 * <9> 1 Terminate Buffer on RxBound
5083 * <8> 0 Bus Width = 16bits
5084 * <7..0> ? status Bits (write as 0s)
5085 *
5086 * 1111 0010 0000 0000 = 0xf200
5087 */
5088
5089 usc_OutDmaReg( info, RDMR, 0xf200 );
5090
5091
5092 /* Transmit DMA mode Register (TDMR)
5093 *
5094 * <15..14> 11 DMA mode = Linked List Buffer mode
5095 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5096 * <12> 1 Clear count of List Entry after fetching
5097 * <11..10> 00 Address mode = Increment
5098 * <9> 1 Terminate Buffer on end of frame
5099 * <8> 0 Bus Width = 16bits
5100 * <7..0> ? status Bits (Read Only so write as 0)
5101 *
5102 * 1111 0010 0000 0000 = 0xf200
5103 */
5104
5105 usc_OutDmaReg( info, TDMR, 0xf200 );
5106
5107
5108 /* DMA Interrupt Control Register (DICR)
5109 *
5110 * <15> 1 DMA Interrupt Enable
5111 * <14> 0 1 = Disable IEO from USC
5112 * <13> 0 1 = Don't provide vector during IntAck
5113 * <12> 1 1 = Include status in Vector
5114 * <10..2> 0 reserved, Must be 0s
5115 * <1> 0 1 = Rx DMA Interrupt Enabled
5116 * <0> 0 1 = Tx DMA Interrupt Enabled
5117 *
5118 * 1001 0000 0000 0000 = 0x9000
5119 */
5120
5121 usc_OutDmaReg( info, DICR, 0x9000 );
5122
5123 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5124 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5125 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5126
5127 /* Channel Control Register (CCR)
5128 *
5129 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5130 * <13> 0 Trigger Tx on SW Command Disabled
5131 * <12> 0 Flag Preamble Disabled
5132 * <11..10> 00 Preamble Length
5133 * <9..8> 00 Preamble Pattern
5134 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5135 * <5> 0 Trigger Rx on SW Command Disabled
5136 * <4..0> 0 reserved
5137 *
5138 * 1000 0000 1000 0000 = 0x8080
5139 */
5140
5141 RegValue = 0x8080;
5142
5143 switch ( info->params.preamble_length ) {
5144 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5145 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5146 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5147 }
5148
5149 switch ( info->params.preamble ) {
5150 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5151 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5152 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5153 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5154 }
5155
5156 usc_OutReg( info, CCR, RegValue );
5157
5158
5159 /*
5160 * Burst/Dwell Control Register
5161 *
5162 * <15..8> 0x20 Maximum number of transfers per bus grant
5163 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5164 */
5165
5166 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5167 /* don't limit bus occupancy on PCI adapter */
5168 usc_OutDmaReg( info, BDCR, 0x0000 );
5169 }
5170 else
5171 usc_OutDmaReg( info, BDCR, 0x2000 );
5172
5173 usc_stop_transmitter(info);
5174 usc_stop_receiver(info);
5175
5176 } /* end of usc_set_sdlc_mode() */
5177
5178 /* usc_enable_loopback()
5179 *
5180 * Set the 16C32 for internal loopback mode.
5181 * The TxCLK and RxCLK signals are generated from the BRG0 and
5182 * the TxD is looped back to the RxD internally.
5183 *
5184 * Arguments: info pointer to device instance data
5185 * enable 1 = enable loopback, 0 = disable
5186 * Return Value: None
5187 */
5188 void usc_enable_loopback(struct mgsl_struct *info, int enable)
5189 {
5190 if (enable) {
5191 /* blank external TXD output */
5192 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5193
5194 /* Clock mode Control Register (CMCR)
5195 *
5196 * <15..14> 00 counter 1 Disabled
5197 * <13..12> 00 counter 0 Disabled
5198 * <11..10> 11 BRG1 Input is TxC Pin
5199 * <9..8> 11 BRG0 Input is TxC Pin
5200 * <7..6> 01 DPLL Input is BRG1 Output
5201 * <5..3> 100 TxCLK comes from BRG0
5202 * <2..0> 100 RxCLK comes from BRG0
5203 *
5204 * 0000 1111 0110 0100 = 0x0f64
5205 */
5206
5207 usc_OutReg( info, CMCR, 0x0f64 );
5208
5209 /* Write 16-bit Time Constant for BRG0 */
5210 /* use clock speed if available, otherwise use 8 for diagnostics */
5211 if (info->params.clock_speed) {
5212 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5213 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5214 else
5215 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5216 } else
5217 usc_OutReg(info, TC0R, (u16)8);
5218
5219 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5220 mode = Continuous Set Bit 0 to enable BRG0. */
5221 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5222
5223 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5224 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5225
5226 /* set Internal Data loopback mode */
5227 info->loopback_bits = 0x300;
5228 outw( 0x0300, info->io_base + CCAR );
5229 } else {
5230 /* enable external TXD output */
5231 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5232
5233 /* clear Internal Data loopback mode */
5234 info->loopback_bits = 0;
5235 outw( 0,info->io_base + CCAR );
5236 }
5237
5238 } /* end of usc_enable_loopback() */
5239
5240 /* usc_enable_aux_clock()
5241 *
5242 * Enabled the AUX clock output at the specified frequency.
5243 *
5244 * Arguments:
5245 *
5246 * info pointer to device extension
5247 * data_rate data rate of clock in bits per second
5248 * A data rate of 0 disables the AUX clock.
5249 *
5250 * Return Value: None
5251 */
5252 void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5253 {
5254 u32 XtalSpeed;
5255 u16 Tc;
5256
5257 if ( data_rate ) {
5258 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5259 XtalSpeed = 11059200;
5260 else
5261 XtalSpeed = 14745600;
5262
5263
5264 /* Tc = (Xtal/Speed) - 1 */
5265 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5266 /* then rounding up gives a more precise time constant. Instead */
5267 /* of rounding up and then subtracting 1 we just don't subtract */
5268 /* the one in this case. */
5269
5270
5271 Tc = (u16)(XtalSpeed/data_rate);
5272 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5273 Tc--;
5274
5275 /* Write 16-bit Time Constant for BRG0 */
5276 usc_OutReg( info, TC0R, Tc );
5277
5278 /*
5279 * Hardware Configuration Register (HCR)
5280 * Clear Bit 1, BRG0 mode = Continuous
5281 * Set Bit 0 to enable BRG0.
5282 */
5283
5284 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5285
5286 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5287 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5288 } else {
5289 /* data rate == 0 so turn off BRG0 */
5290 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5291 }
5292
5293 } /* end of usc_enable_aux_clock() */
5294
5295 /*
5296 *
5297 * usc_process_rxoverrun_sync()
5298 *
5299 * This function processes a receive overrun by resetting the
5300 * receive DMA buffers and issuing a Purge Rx FIFO command
5301 * to allow the receiver to continue receiving.
5302 *
5303 * Arguments:
5304 *
5305 * info pointer to device extension
5306 *
5307 * Return Value: None
5308 */
5309 void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5310 {
5311 int start_index;
5312 int end_index;
5313 int frame_start_index;
5314 int start_of_frame_found = FALSE;
5315 int end_of_frame_found = FALSE;
5316 int reprogram_dma = FALSE;
5317
5318 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5319 u32 phys_addr;
5320
5321 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5322 usc_RCmd( info, RCmd_EnterHuntmode );
5323 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5324
5325 /* CurrentRxBuffer points to the 1st buffer of the next */
5326 /* possibly available receive frame. */
5327
5328 frame_start_index = start_index = end_index = info->current_rx_buffer;
5329
5330 /* Search for an unfinished string of buffers. This means */
5331 /* that a receive frame started (at least one buffer with */
5332 /* count set to zero) but there is no terminiting buffer */
5333 /* (status set to non-zero). */
5334
5335 while( !buffer_list[end_index].count )
5336 {
5337 /* Count field has been reset to zero by 16C32. */
5338 /* This buffer is currently in use. */
5339
5340 if ( !start_of_frame_found )
5341 {
5342 start_of_frame_found = TRUE;
5343 frame_start_index = end_index;
5344 end_of_frame_found = FALSE;
5345 }
5346
5347 if ( buffer_list[end_index].status )
5348 {
5349 /* Status field has been set by 16C32. */
5350 /* This is the last buffer of a received frame. */
5351
5352 /* We want to leave the buffers for this frame intact. */
5353 /* Move on to next possible frame. */
5354
5355 start_of_frame_found = FALSE;
5356 end_of_frame_found = TRUE;
5357 }
5358
5359 /* advance to next buffer entry in linked list */
5360 end_index++;
5361 if ( end_index == info->rx_buffer_count )
5362 end_index = 0;
5363
5364 if ( start_index == end_index )
5365 {
5366 /* The entire list has been searched with all Counts == 0 and */
5367 /* all Status == 0. The receive buffers are */
5368 /* completely screwed, reset all receive buffers! */
5369 mgsl_reset_rx_dma_buffers( info );
5370 frame_start_index = 0;
5371 start_of_frame_found = FALSE;
5372 reprogram_dma = TRUE;
5373 break;
5374 }
5375 }
5376
5377 if ( start_of_frame_found && !end_of_frame_found )
5378 {
5379 /* There is an unfinished string of receive DMA buffers */
5380 /* as a result of the receiver overrun. */
5381
5382 /* Reset the buffers for the unfinished frame */
5383 /* and reprogram the receive DMA controller to start */
5384 /* at the 1st buffer of unfinished frame. */
5385
5386 start_index = frame_start_index;
5387
5388 do
5389 {
5390 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5391
5392 /* Adjust index for wrap around. */
5393 if ( start_index == info->rx_buffer_count )
5394 start_index = 0;
5395
5396 } while( start_index != end_index );
5397
5398 reprogram_dma = TRUE;
5399 }
5400
5401 if ( reprogram_dma )
5402 {
5403 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5404 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5405 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5406
5407 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5408
5409 /* This empties the receive FIFO and loads the RCC with RCLR */
5410 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5411
5412 /* program 16C32 with physical address of 1st DMA buffer entry */
5413 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5414 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5415 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5416
5417 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5418 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5419 usc_EnableInterrupts( info, RECEIVE_STATUS );
5420
5421 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5422 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5423
5424 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5425 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5426 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5427 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5428 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5429 else
5430 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5431 }
5432 else
5433 {
5434 /* This empties the receive FIFO and loads the RCC with RCLR */
5435 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5436 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5437 }
5438
5439 } /* end of usc_process_rxoverrun_sync() */
5440
5441 /* usc_stop_receiver()
5442 *
5443 * Disable USC receiver
5444 *
5445 * Arguments: info pointer to device instance data
5446 * Return Value: None
5447 */
5448 void usc_stop_receiver( struct mgsl_struct *info )
5449 {
5450 if (debug_level >= DEBUG_LEVEL_ISR)
5451 printk("%s(%d):usc_stop_receiver(%s)\n",
5452 __FILE__,__LINE__, info->device_name );
5453
5454 /* Disable receive DMA channel. */
5455 /* This also disables receive DMA channel interrupts */
5456 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5457
5458 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5459 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5460 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5461
5462 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5463
5464 /* This empties the receive FIFO and loads the RCC with RCLR */
5465 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5466 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5467
5468 info->rx_enabled = 0;
5469 info->rx_overflow = 0;
5470
5471 } /* end of stop_receiver() */
5472
5473 /* usc_start_receiver()
5474 *
5475 * Enable the USC receiver
5476 *
5477 * Arguments: info pointer to device instance data
5478 * Return Value: None
5479 */
5480 void usc_start_receiver( struct mgsl_struct *info )
5481 {
5482 u32 phys_addr;
5483
5484 if (debug_level >= DEBUG_LEVEL_ISR)
5485 printk("%s(%d):usc_start_receiver(%s)\n",
5486 __FILE__,__LINE__, info->device_name );
5487
5488 mgsl_reset_rx_dma_buffers( info );
5489 usc_stop_receiver( info );
5490
5491 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5492 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5493
5494 if ( info->params.mode == MGSL_MODE_HDLC ) {
5495 /* DMA mode Transfers */
5496 /* Program the DMA controller. */
5497 /* Enable the DMA controller end of buffer interrupt. */
5498
5499 /* program 16C32 with physical address of 1st DMA buffer entry */
5500 phys_addr = info->rx_buffer_list[0].phys_entry;
5501 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5502 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5503
5504 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5505 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5506 usc_EnableInterrupts( info, RECEIVE_STATUS );
5507
5508 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5509 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5510
5511 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5512 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5513 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5514 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5515 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5516 else
5517 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5518 } else {
5519 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5520 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5521 usc_EnableInterrupts(info, RECEIVE_DATA);
5522
5523 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5524 usc_RCmd( info, RCmd_EnterHuntmode );
5525
5526 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5527 }
5528
5529 usc_OutReg( info, CCSR, 0x1020 );
5530
5531 info->rx_enabled = 1;
5532
5533 } /* end of usc_start_receiver() */
5534
5535 /* usc_start_transmitter()
5536 *
5537 * Enable the USC transmitter and send a transmit frame if
5538 * one is loaded in the DMA buffers.
5539 *
5540 * Arguments: info pointer to device instance data
5541 * Return Value: None
5542 */
5543 void usc_start_transmitter( struct mgsl_struct *info )
5544 {
5545 u32 phys_addr;
5546 unsigned int FrameSize;
5547
5548 if (debug_level >= DEBUG_LEVEL_ISR)
5549 printk("%s(%d):usc_start_transmitter(%s)\n",
5550 __FILE__,__LINE__, info->device_name );
5551
5552 if ( info->xmit_cnt ) {
5553
5554 /* If auto RTS enabled and RTS is inactive, then assert */
5555 /* RTS and set a flag indicating that the driver should */
5556 /* negate RTS when the transmission completes. */
5557
5558 info->drop_rts_on_tx_done = 0;
5559
5560 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5561 usc_get_serial_signals( info );
5562 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5563 info->serial_signals |= SerialSignal_RTS;
5564 usc_set_serial_signals( info );
5565 info->drop_rts_on_tx_done = 1;
5566 }
5567 }
5568
5569
5570 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5571 if ( !info->tx_active ) {
5572 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5573 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5574 usc_EnableInterrupts(info, TRANSMIT_DATA);
5575 usc_load_txfifo(info);
5576 }
5577 } else {
5578 /* Disable transmit DMA controller while programming. */
5579 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5580
5581 /* Transmit DMA buffer is loaded, so program USC */
5582 /* to send the frame contained in the buffers. */
5583
5584
5585 FrameSize = info->tx_buffer_list[0].rcc;
5586
5587 /* Program the Transmit Character Length Register (TCLR) */
5588 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5589 usc_OutReg( info, TCLR, (u16)FrameSize );
5590
5591 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5592
5593 /* Program the address of the 1st DMA Buffer Entry in linked list */
5594 phys_addr = info->tx_buffer_list[0].phys_entry;
5595 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5596 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5597
5598 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5599 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5600 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5601
5602 /* Initialize Transmit DMA Channel */
5603 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5604
5605 usc_TCmd( info, TCmd_SendFrame );
5606
5607 info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
5608 add_timer(&info->tx_timer);
5609 }
5610 info->tx_active = 1;
5611 }
5612
5613 if ( !info->tx_enabled ) {
5614 info->tx_enabled = 1;
5615 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5616 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5617 else
5618 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5619 }
5620
5621 } /* end of usc_start_transmitter() */
5622
5623 /* usc_stop_transmitter()
5624 *
5625 * Stops the transmitter and DMA
5626 *
5627 * Arguments: info pointer to device isntance data
5628 * Return Value: None
5629 */
5630 void usc_stop_transmitter( struct mgsl_struct *info )
5631 {
5632 if (debug_level >= DEBUG_LEVEL_ISR)
5633 printk("%s(%d):usc_stop_transmitter(%s)\n",
5634 __FILE__,__LINE__, info->device_name );
5635
5636 del_timer(&info->tx_timer);
5637
5638 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5639 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5640 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5641
5642 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5643 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5644 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5645
5646 info->tx_enabled = 0;
5647 info->tx_active = 0;
5648
5649 } /* end of usc_stop_transmitter() */
5650
5651 /* usc_load_txfifo()
5652 *
5653 * Fill the transmit FIFO until the FIFO is full or
5654 * there is no more data to load.
5655 *
5656 * Arguments: info pointer to device extension (instance data)
5657 * Return Value: None
5658 */
5659 void usc_load_txfifo( struct mgsl_struct *info )
5660 {
5661 int Fifocount;
5662 u8 TwoBytes[2];
5663
5664 if ( !info->xmit_cnt && !info->x_char )
5665 return;
5666
5667 /* Select transmit FIFO status readback in TICR */
5668 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5669
5670 /* load the Transmit FIFO until FIFOs full or all data sent */
5671
5672 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5673 /* there is more space in the transmit FIFO and */
5674 /* there is more data in transmit buffer */
5675
5676 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5677 /* write a 16-bit word from transmit buffer to 16C32 */
5678
5679 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5680 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5681 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5682 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5683
5684 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5685
5686 info->xmit_cnt -= 2;
5687 info->icount.tx += 2;
5688 } else {
5689 /* only 1 byte left to transmit or 1 FIFO slot left */
5690
5691 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5692 info->io_base + CCAR );
5693
5694 if (info->x_char) {
5695 /* transmit pending high priority char */
5696 outw( info->x_char,info->io_base + CCAR );
5697 info->x_char = 0;
5698 } else {
5699 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5700 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5701 info->xmit_cnt--;
5702 }
5703 info->icount.tx++;
5704 }
5705 }
5706
5707 } /* end of usc_load_txfifo() */
5708
5709 /* usc_reset()
5710 *
5711 * Reset the adapter to a known state and prepare it for further use.
5712 *
5713 * Arguments: info pointer to device instance data
5714 * Return Value: None
5715 */
5716 void usc_reset( struct mgsl_struct *info )
5717 {
5718 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5719 int i;
5720 u32 readval;
5721
5722 /* Set BIT30 of Misc Control Register */
5723 /* (Local Control Register 0x50) to force reset of USC. */
5724
5725 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5726 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5727
5728 info->misc_ctrl_value |= BIT30;
5729 *MiscCtrl = info->misc_ctrl_value;
5730
5731 /*
5732 * Force at least 170ns delay before clearing
5733 * reset bit. Each read from LCR takes at least
5734 * 30ns so 10 times for 300ns to be safe.
5735 */
5736 for(i=0;i<10;i++)
5737 readval = *MiscCtrl;
5738
5739 info->misc_ctrl_value &= ~BIT30;
5740 *MiscCtrl = info->misc_ctrl_value;
5741
5742 *LCR0BRDR = BUS_DESCRIPTOR(
5743 1, // Write Strobe Hold (0-3)
5744 2, // Write Strobe Delay (0-3)
5745 2, // Read Strobe Delay (0-3)
5746 0, // NWDD (Write data-data) (0-3)
5747 4, // NWAD (Write Addr-data) (0-31)
5748 0, // NXDA (Read/Write Data-Addr) (0-3)
5749 0, // NRDD (Read Data-Data) (0-3)
5750 5 // NRAD (Read Addr-Data) (0-31)
5751 );
5752 } else {
5753 /* do HW reset */
5754 outb( 0,info->io_base + 8 );
5755 }
5756
5757 info->mbre_bit = 0;
5758 info->loopback_bits = 0;
5759 info->usc_idle_mode = 0;
5760
5761 /*
5762 * Program the Bus Configuration Register (BCR)
5763 *
5764 * <15> 0 Don't use seperate address
5765 * <14..6> 0 reserved
5766 * <5..4> 00 IAckmode = Default, don't care
5767 * <3> 1 Bus Request Totem Pole output
5768 * <2> 1 Use 16 Bit data bus
5769 * <1> 0 IRQ Totem Pole output
5770 * <0> 0 Don't Shift Right Addr
5771 *
5772 * 0000 0000 0000 1100 = 0x000c
5773 *
5774 * By writing to io_base + SDPIN the Wait/Ack pin is
5775 * programmed to work as a Wait pin.
5776 */
5777
5778 outw( 0x000c,info->io_base + SDPIN );
5779
5780
5781 outw( 0,info->io_base );
5782 outw( 0,info->io_base + CCAR );
5783
5784 /* select little endian byte ordering */
5785 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5786
5787
5788 /* Port Control Register (PCR)
5789 *
5790 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5791 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5792 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5793 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5794 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5795 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5796 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5797 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5798 *
5799 * 1111 0000 1111 0101 = 0xf0f5
5800 */
5801
5802 usc_OutReg( info, PCR, 0xf0f5 );
5803
5804
5805 /*
5806 * Input/Output Control Register
5807 *
5808 * <15..14> 00 CTS is active low input
5809 * <13..12> 00 DCD is active low input
5810 * <11..10> 00 TxREQ pin is input (DSR)
5811 * <9..8> 00 RxREQ pin is input (RI)
5812 * <7..6> 00 TxD is output (Transmit Data)
5813 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5814 * <2..0> 100 RxC is Output (drive with BRG0)
5815 *
5816 * 0000 0000 0000 0100 = 0x0004
5817 */
5818
5819 usc_OutReg( info, IOCR, 0x0004 );
5820
5821 } /* end of usc_reset() */
5822
5823 /* usc_set_async_mode()
5824 *
5825 * Program adapter for asynchronous communications.
5826 *
5827 * Arguments: info pointer to device instance data
5828 * Return Value: None
5829 */
5830 void usc_set_async_mode( struct mgsl_struct *info )
5831 {
5832 u16 RegValue;
5833
5834 /* disable interrupts while programming USC */
5835 usc_DisableMasterIrqBit( info );
5836
5837 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5838 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5839
5840 usc_loopback_frame( info );
5841
5842 /* Channel mode Register (CMR)
5843 *
5844 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5845 * <13..12> 00 00 = 16X Clock
5846 * <11..8> 0000 Transmitter mode = Asynchronous
5847 * <7..6> 00 reserved?
5848 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5849 * <3..0> 0000 Receiver mode = Asynchronous
5850 *
5851 * 0000 0000 0000 0000 = 0x0
5852 */
5853
5854 RegValue = 0;
5855 if ( info->params.stop_bits != 1 )
5856 RegValue |= BIT14;
5857 usc_OutReg( info, CMR, RegValue );
5858
5859
5860 /* Receiver mode Register (RMR)
5861 *
5862 * <15..13> 000 encoding = None
5863 * <12..08> 00000 reserved (Sync Only)
5864 * <7..6> 00 Even parity
5865 * <5> 0 parity disabled
5866 * <4..2> 000 Receive Char Length = 8 bits
5867 * <1..0> 00 Disable Receiver
5868 *
5869 * 0000 0000 0000 0000 = 0x0
5870 */
5871
5872 RegValue = 0;
5873
5874 if ( info->params.data_bits != 8 )
5875 RegValue |= BIT4+BIT3+BIT2;
5876
5877 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5878 RegValue |= BIT5;
5879 if ( info->params.parity != ASYNC_PARITY_ODD )
5880 RegValue |= BIT6;
5881 }
5882
5883 usc_OutReg( info, RMR, RegValue );
5884
5885
5886 /* Set IRQ trigger level */
5887
5888 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5889
5890
5891 /* Receive Interrupt Control Register (RICR)
5892 *
5893 * <15..8> ? RxFIFO IRQ Request Level
5894 *
5895 * Note: For async mode the receive FIFO level must be set
5896 * to 0 to aviod the situation where the FIFO contains fewer bytes
5897 * than the trigger level and no more data is expected.
5898 *
5899 * <7> 0 Exited Hunt IA (Interrupt Arm)
5900 * <6> 0 Idle Received IA
5901 * <5> 0 Break/Abort IA
5902 * <4> 0 Rx Bound IA
5903 * <3> 0 Queued status reflects oldest byte in FIFO
5904 * <2> 0 Abort/PE IA
5905 * <1> 0 Rx Overrun IA
5906 * <0> 0 Select TC0 value for readback
5907 *
5908 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5909 */
5910
5911 usc_OutReg( info, RICR, 0x0000 );
5912
5913 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5914 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5915
5916
5917 /* Transmit mode Register (TMR)
5918 *
5919 * <15..13> 000 encoding = None
5920 * <12..08> 00000 reserved (Sync Only)
5921 * <7..6> 00 Transmit parity Even
5922 * <5> 0 Transmit parity Disabled
5923 * <4..2> 000 Tx Char Length = 8 bits
5924 * <1..0> 00 Disable Transmitter
5925 *
5926 * 0000 0000 0000 0000 = 0x0
5927 */
5928
5929 RegValue = 0;
5930
5931 if ( info->params.data_bits != 8 )
5932 RegValue |= BIT4+BIT3+BIT2;
5933
5934 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5935 RegValue |= BIT5;
5936 if ( info->params.parity != ASYNC_PARITY_ODD )
5937 RegValue |= BIT6;
5938 }
5939
5940 usc_OutReg( info, TMR, RegValue );
5941
5942 usc_set_txidle( info );
5943
5944
5945 /* Set IRQ trigger level */
5946
5947 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5948
5949
5950 /* Transmit Interrupt Control Register (TICR)
5951 *
5952 * <15..8> ? Transmit FIFO IRQ Level
5953 * <7> 0 Present IA (Interrupt Arm)
5954 * <6> 1 Idle Sent IA
5955 * <5> 0 Abort Sent IA
5956 * <4> 0 EOF/EOM Sent IA
5957 * <3> 0 CRC Sent IA
5958 * <2> 0 1 = Wait for SW Trigger to Start Frame
5959 * <1> 0 Tx Underrun IA
5960 * <0> 0 TC0 constant on read back
5961 *
5962 * 0000 0000 0100 0000 = 0x0040
5963 */
5964
5965 usc_OutReg( info, TICR, 0x1f40 );
5966
5967 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5968 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5969
5970 usc_enable_async_clock( info, info->params.data_rate );
5971
5972
5973 /* Channel Control/status Register (CCSR)
5974 *
5975 * <15> X RCC FIFO Overflow status (RO)
5976 * <14> X RCC FIFO Not Empty status (RO)
5977 * <13> 0 1 = Clear RCC FIFO (WO)
5978 * <12> X DPLL in Sync status (RO)
5979 * <11> X DPLL 2 Missed Clocks status (RO)
5980 * <10> X DPLL 1 Missed Clock status (RO)
5981 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5982 * <7> X SDLC Loop On status (RO)
5983 * <6> X SDLC Loop Send status (RO)
5984 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5985 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5986 * <1..0> 00 reserved
5987 *
5988 * 0000 0000 0010 0000 = 0x0020
5989 */
5990
5991 usc_OutReg( info, CCSR, 0x0020 );
5992
5993 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
5994 RECEIVE_DATA + RECEIVE_STATUS );
5995
5996 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
5997 RECEIVE_DATA + RECEIVE_STATUS );
5998
5999 usc_EnableMasterIrqBit( info );
6000
6001 /* Enable INTEN (Port 6, Bit12) */
6002 /* This connects the IRQ request signal to the ISA bus */
6003 /* on the ISA adapter. This has no effect for the PCI adapter */
6004 usc_OutReg( info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
6005
6006 } /* end of usc_set_async_mode() */
6007
6008 /* usc_loopback_frame()
6009 *
6010 * Loop back a small (2 byte) dummy SDLC frame.
6011 * Interrupts and DMA are NOT used. The purpose of this is to
6012 * clear any 'stale' status info left over from running in async mode.
6013 *
6014 * The 16C32 shows the strange behaviour of marking the 1st
6015 * received SDLC frame with a CRC error even when there is no
6016 * CRC error. To get around this a small dummy from of 2 bytes
6017 * is looped back when switching from async to sync mode.
6018 *
6019 * Arguments: info pointer to device instance data
6020 * Return Value: None
6021 */
6022 void usc_loopback_frame( struct mgsl_struct *info )
6023 {
6024 int i;
6025
6026 usc_DisableMasterIrqBit( info );
6027
6028 usc_set_sdlc_mode( info );
6029 usc_enable_loopback( info, 1 );
6030
6031 /* Write 16-bit Time Constant for BRG0 */
6032 usc_OutReg( info, TC0R, 0 );
6033
6034 /* Channel Control Register (CCR)
6035 *
6036 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6037 * <13> 0 Trigger Tx on SW Command Disabled
6038 * <12> 0 Flag Preamble Disabled
6039 * <11..10> 00 Preamble Length = 8-Bits
6040 * <9..8> 01 Preamble Pattern = flags
6041 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6042 * <5> 0 Trigger Rx on SW Command Disabled
6043 * <4..0> 0 reserved
6044 *
6045 * 0000 0001 0000 0000 = 0x0100
6046 */
6047
6048 usc_OutReg( info, CCR, 0x0100 );
6049
6050 /* SETUP RECEIVER */
6051 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6052 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6053
6054 /* SETUP TRANSMITTER */
6055 /* Program the Transmit Character Length Register (TCLR) */
6056 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6057 usc_OutReg( info, TCLR, 2 );
6058 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6059
6060 /* unlatch Tx status bits, and start transmit channel. */
6061 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6062 outw(0,info->io_base + DATAREG);
6063
6064 /* ENABLE TRANSMITTER */
6065 usc_TCmd( info, TCmd_SendFrame );
6066 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6067
6068 /* WAIT FOR RECEIVE COMPLETE */
6069 for (i=0 ; i<1000 ; i++)
6070 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6071 break;
6072
6073 /* clear Internal Data loopback mode */
6074 usc_enable_loopback(info, 0);
6075
6076 usc_EnableMasterIrqBit(info);
6077
6078 } /* end of usc_loopback_frame() */
6079
6080 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6081 *
6082 * Arguments: info pointer to adapter info structure
6083 * Return Value: None
6084 */
6085 void usc_set_sync_mode( struct mgsl_struct *info )
6086 {
6087 usc_loopback_frame( info );
6088 usc_set_sdlc_mode( info );
6089
6090 /* Enable INTEN (Port 6, Bit12) */
6091 /* This connects the IRQ request signal to the ISA bus */
6092 /* on the ISA adapter. This has no effect for the PCI adapter */
6093 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6094
6095 usc_enable_aux_clock(info, info->params.clock_speed);
6096
6097 if (info->params.loopback)
6098 usc_enable_loopback(info,1);
6099
6100 } /* end of mgsl_set_sync_mode() */
6101
6102 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6103 *
6104 * Arguments: info pointer to device instance data
6105 * Return Value: None
6106 */
6107 void usc_set_txidle( struct mgsl_struct *info )
6108 {
6109 u16 usc_idle_mode = IDLEMODE_FLAGS;
6110
6111 /* Map API idle mode to USC register bits */
6112
6113 switch( info->idle_mode ){
6114 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6115 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6116 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6117 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6118 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6119 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6120 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6121 }
6122
6123 info->usc_idle_mode = usc_idle_mode;
6124 //usc_OutReg(info, TCSR, usc_idle_mode);
6125 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6126 info->tcsr_value += usc_idle_mode;
6127 usc_OutReg(info, TCSR, info->tcsr_value);
6128
6129 } /* end of usc_set_txidle() */
6130
6131 /* usc_get_serial_signals()
6132 *
6133 * Query the adapter for the state of the V24 status (input) signals.
6134 *
6135 * Arguments: info pointer to device instance data
6136 * Return Value: None
6137 */
6138 void usc_get_serial_signals( struct mgsl_struct *info )
6139 {
6140 u16 status;
6141
6142 /* clear all serial signals except DTR and RTS */
6143 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6144
6145 /* Read the Misc Interrupt status Register (MISR) to get */
6146 /* the V24 status signals. */
6147
6148 status = usc_InReg( info, MISR );
6149
6150 /* set serial signal bits to reflect MISR */
6151
6152 if ( status & MISCSTATUS_CTS )
6153 info->serial_signals |= SerialSignal_CTS;
6154
6155 if ( status & MISCSTATUS_DCD )
6156 info->serial_signals |= SerialSignal_DCD;
6157
6158 if ( status & MISCSTATUS_RI )
6159 info->serial_signals |= SerialSignal_RI;
6160
6161 if ( status & MISCSTATUS_DSR )
6162 info->serial_signals |= SerialSignal_DSR;
6163
6164 } /* end of usc_get_serial_signals() */
6165
6166 /* usc_set_serial_signals()
6167 *
6168 * Set the state of DTR and RTS based on contents of
6169 * serial_signals member of device extension.
6170 *
6171 * Arguments: info pointer to device instance data
6172 * Return Value: None
6173 */
6174 void usc_set_serial_signals( struct mgsl_struct *info )
6175 {
6176 u16 Control;
6177 unsigned char V24Out = info->serial_signals;
6178
6179 /* get the current value of the Port Control Register (PCR) */
6180
6181 Control = usc_InReg( info, PCR );
6182
6183 if ( V24Out & SerialSignal_RTS )
6184 Control &= ~(BIT6);
6185 else
6186 Control |= BIT6;
6187
6188 if ( V24Out & SerialSignal_DTR )
6189 Control &= ~(BIT4);
6190 else
6191 Control |= BIT4;
6192
6193 usc_OutReg( info, PCR, Control );
6194
6195 } /* end of usc_set_serial_signals() */
6196
6197 /* usc_enable_async_clock()
6198 *
6199 * Enable the async clock at the specified frequency.
6200 *
6201 * Arguments: info pointer to device instance data
6202 * data_rate data rate of clock in bps
6203 * 0 disables the AUX clock.
6204 * Return Value: None
6205 */
6206 void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6207 {
6208 if ( data_rate ) {
6209 /*
6210 * Clock mode Control Register (CMCR)
6211 *
6212 * <15..14> 00 counter 1 Disabled
6213 * <13..12> 00 counter 0 Disabled
6214 * <11..10> 11 BRG1 Input is TxC Pin
6215 * <9..8> 11 BRG0 Input is TxC Pin
6216 * <7..6> 01 DPLL Input is BRG1 Output
6217 * <5..3> 100 TxCLK comes from BRG0
6218 * <2..0> 100 RxCLK comes from BRG0
6219 *
6220 * 0000 1111 0110 0100 = 0x0f64
6221 */
6222
6223 usc_OutReg( info, CMCR, 0x0f64 );
6224
6225
6226 /*
6227 * Write 16-bit Time Constant for BRG0
6228 * Time Constant = (ClkSpeed / data_rate) - 1
6229 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6230 */
6231
6232 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6233 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6234 else
6235 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6236
6237
6238 /*
6239 * Hardware Configuration Register (HCR)
6240 * Clear Bit 1, BRG0 mode = Continuous
6241 * Set Bit 0 to enable BRG0.
6242 */
6243
6244 usc_OutReg( info, HCR,
6245 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6246
6247
6248 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6249
6250 usc_OutReg( info, IOCR,
6251 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6252 } else {
6253 /* data rate == 0 so turn off BRG0 */
6254 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6255 }
6256
6257 } /* end of usc_enable_async_clock() */
6258
6259 /*
6260 * Buffer Structures:
6261 *
6262 * Normal memory access uses virtual addresses that can make discontiguous
6263 * physical memory pages appear to be contiguous in the virtual address
6264 * space (the processors memory mapping handles the conversions).
6265 *
6266 * DMA transfers require physically contiguous memory. This is because
6267 * the DMA system controller and DMA bus masters deal with memory using
6268 * only physical addresses.
6269 *
6270 * This causes a problem under Windows NT when large DMA buffers are
6271 * needed. Fragmentation of the nonpaged pool prevents allocations of
6272 * physically contiguous buffers larger than the PAGE_SIZE.
6273 *
6274 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6275 * allows DMA transfers to physically discontiguous buffers. Information
6276 * about each data transfer buffer is contained in a memory structure
6277 * called a 'buffer entry'. A list of buffer entries is maintained
6278 * to track and control the use of the data transfer buffers.
6279 *
6280 * To support this strategy we will allocate sufficient PAGE_SIZE
6281 * contiguous memory buffers to allow for the total required buffer
6282 * space.
6283 *
6284 * The 16C32 accesses the list of buffer entries using Bus Master
6285 * DMA. Control information is read from the buffer entries by the
6286 * 16C32 to control data transfers. status information is written to
6287 * the buffer entries by the 16C32 to indicate the status of completed
6288 * transfers.
6289 *
6290 * The CPU writes control information to the buffer entries to control
6291 * the 16C32 and reads status information from the buffer entries to
6292 * determine information about received and transmitted frames.
6293 *
6294 * Because the CPU and 16C32 (adapter) both need simultaneous access
6295 * to the buffer entries, the buffer entry memory is allocated with
6296 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6297 * entry list to PAGE_SIZE.
6298 *
6299 * The actual data buffers on the other hand will only be accessed
6300 * by the CPU or the adapter but not by both simultaneously. This allows
6301 * Scatter/Gather packet based DMA procedures for using physically
6302 * discontiguous pages.
6303 */
6304
6305 /*
6306 * mgsl_reset_rx_dma_buffers()
6307 *
6308 * Set the count for all receive buffers to DMABUFFERSIZE
6309 * and set the current buffer to the first buffer. This effectively
6310 * makes all buffers free and discards any data in buffers.
6311 *
6312 * Arguments: info pointer to device instance data
6313 * Return Value: None
6314 */
6315 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6316 {
6317 unsigned int i;
6318
6319 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6320 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6321 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6322 // info->rx_buffer_list[i].status = 0;
6323 }
6324
6325 info->current_rx_buffer = 0;
6326
6327 } /* end of mgsl_reset_rx_dma_buffers() */
6328
6329 /*
6330 * mgsl_free_rx_frame_buffers()
6331 *
6332 * Free the receive buffers used by a received SDLC
6333 * frame such that the buffers can be reused.
6334 *
6335 * Arguments:
6336 *
6337 * info pointer to device instance data
6338 * StartIndex index of 1st receive buffer of frame
6339 * EndIndex index of last receive buffer of frame
6340 *
6341 * Return Value: None
6342 */
6343 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6344 {
6345 int Done = 0;
6346 DMABUFFERENTRY *pBufEntry;
6347 unsigned int Index;
6348
6349 /* Starting with 1st buffer entry of the frame clear the status */
6350 /* field and set the count field to DMA Buffer Size. */
6351
6352 Index = StartIndex;
6353
6354 while( !Done ) {
6355 pBufEntry = &(info->rx_buffer_list[Index]);
6356
6357 if ( Index == EndIndex ) {
6358 /* This is the last buffer of the frame! */
6359 Done = 1;
6360 }
6361
6362 /* reset current buffer for reuse */
6363 // pBufEntry->status = 0;
6364 // pBufEntry->count = DMABUFFERSIZE;
6365 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6366
6367 /* advance to next buffer entry in linked list */
6368 Index++;
6369 if ( Index == info->rx_buffer_count )
6370 Index = 0;
6371 }
6372
6373 /* set current buffer to next buffer after last buffer of frame */
6374 info->current_rx_buffer = Index;
6375
6376 } /* end of free_rx_frame_buffers() */
6377
6378 /* mgsl_get_rx_frame()
6379 *
6380 * This function attempts to return a received SDLC frame from the
6381 * receive DMA buffers. Only frames received without errors are returned.
6382 *
6383 * Arguments: info pointer to device extension
6384 * Return Value: 1 if frame returned, otherwise 0
6385 */
6386 int mgsl_get_rx_frame(struct mgsl_struct *info)
6387 {
6388 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6389 unsigned short status;
6390 DMABUFFERENTRY *pBufEntry;
6391 unsigned int framesize;
6392 int ReturnCode = 0;
6393 unsigned long flags;
6394 struct tty_struct *tty = info->tty;
6395
6396 /*
6397 * current_rx_buffer points to the 1st buffer of the next available
6398 * receive frame. To find the last buffer of the frame look for
6399 * a non-zero status field in the buffer entries. (The status
6400 * field is set by the 16C32 after completing a receive frame.
6401 */
6402
6403 StartIndex = EndIndex = info->current_rx_buffer;
6404
6405 while( !info->rx_buffer_list[EndIndex].status ) {
6406 /*
6407 * If the count field of the buffer entry is non-zero then
6408 * this buffer has not been used. (The 16C32 clears the count
6409 * field when it starts using the buffer.) If an unused buffer
6410 * is encountered then there are no frames available.
6411 */
6412
6413 if ( info->rx_buffer_list[EndIndex].count )
6414 goto Cleanup;
6415
6416 /* advance to next buffer entry in linked list */
6417 EndIndex++;
6418 if ( EndIndex == info->rx_buffer_count )
6419 EndIndex = 0;
6420
6421 /* if entire list searched then no frame available */
6422 if ( EndIndex == StartIndex ) {
6423 /* If this occurs then something bad happened,
6424 * all buffers have been 'used' but none mark
6425 * the end of a frame. Reset buffers and receiver.
6426 */
6427
6428 if ( info->rx_enabled ){
6429 spin_lock_irqsave(&info->irq_spinlock,flags);
6430 usc_start_receiver(info);
6431 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6432 }
6433 goto Cleanup;
6434 }
6435 }
6436
6437
6438 /* check status of receive frame */
6439
6440 status = info->rx_buffer_list[EndIndex].status;
6441
6442 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6443 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6444 if ( status & RXSTATUS_SHORT_FRAME )
6445 info->icount.rxshort++;
6446 else if ( status & RXSTATUS_ABORT )
6447 info->icount.rxabort++;
6448 else if ( status & RXSTATUS_OVERRUN )
6449 info->icount.rxover++;
6450 else
6451 info->icount.rxcrc++;
6452 framesize = 0;
6453 #ifdef CONFIG_SYNCLINK_SYNCPPP
6454 info->netstats.rx_errors++;
6455 info->netstats.rx_frame_errors++;
6456 #endif
6457 } else {
6458 /* receive frame has no errors, get frame size.
6459 * The frame size is the starting value of the RCC (which was
6460 * set to 0xffff) minus the ending value of the RCC (decremented
6461 * once for each receive character) minus 2 for the 16-bit CRC.
6462 */
6463
6464 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6465
6466 /* adjust frame size for CRC if any */
6467 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6468 framesize -= 2;
6469 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6470 framesize -= 4;
6471 }
6472
6473 if ( debug_level >= DEBUG_LEVEL_BH )
6474 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6475 __FILE__,__LINE__,info->device_name,status,framesize);
6476
6477 if ( debug_level >= DEBUG_LEVEL_DATA )
6478 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6479 MIN(framesize,DMABUFFERSIZE),0);
6480
6481 if (framesize) {
6482 if (framesize > info->max_frame_size)
6483 info->icount.rxlong++;
6484 else {
6485 /* copy dma buffer(s) to contiguous intermediate buffer */
6486 int copy_count = framesize;
6487 int index = StartIndex;
6488 unsigned char *ptmp = info->intermediate_rxbuffer;
6489
6490 info->icount.rxok++;
6491
6492 while(copy_count) {
6493 int partial_count;
6494 if ( copy_count > DMABUFFERSIZE )
6495 partial_count = DMABUFFERSIZE;
6496 else
6497 partial_count = copy_count;
6498
6499 pBufEntry = &(info->rx_buffer_list[index]);
6500 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6501 ptmp += partial_count;
6502 copy_count -= partial_count;
6503
6504 if ( ++index == info->rx_buffer_count )
6505 index = 0;
6506 }
6507
6508 #ifdef CONFIG_SYNCLINK_SYNCPPP
6509 if (info->netcount) {
6510 /* pass frame to syncppp device */
6511 mgsl_sppp_rx_done(info,info->intermediate_rxbuffer,framesize);
6512 }
6513 else
6514 #endif
6515 {
6516 /* Call the line discipline receive callback directly. */
6517 tty->ldisc.receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6518 }
6519 }
6520 }
6521 /* Free the buffers used by this frame. */
6522 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6523
6524 ReturnCode = 1;
6525
6526 Cleanup:
6527
6528 if ( info->rx_enabled && info->rx_overflow ) {
6529 /* The receiver needs to restarted because of
6530 * a receive overflow (buffer or FIFO). If the
6531 * receive buffers are now empty, then restart receiver.
6532 */
6533
6534 if ( !info->rx_buffer_list[EndIndex].status &&
6535 info->rx_buffer_list[EndIndex].count ) {
6536 spin_lock_irqsave(&info->irq_spinlock,flags);
6537 usc_start_receiver(info);
6538 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6539 }
6540 }
6541
6542 return ReturnCode;
6543
6544 } /* end of mgsl_get_rx_frame() */
6545
6546 /* mgsl_load_tx_dma_buffer()
6547 *
6548 * Load the transmit DMA buffer with the specified data.
6549 *
6550 * Arguments:
6551 *
6552 * info pointer to device extension
6553 * Buffer pointer to buffer containing frame to load
6554 * BufferSize size in bytes of frame in Buffer
6555 *
6556 * Return Value: None
6557 */
6558 void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, const char *Buffer,
6559 unsigned int BufferSize)
6560 {
6561 unsigned short Copycount;
6562 unsigned int i = 0;
6563 DMABUFFERENTRY *pBufEntry;
6564
6565 if ( debug_level >= DEBUG_LEVEL_DATA )
6566 mgsl_trace_block(info,Buffer, MIN(BufferSize,DMABUFFERSIZE), 1);
6567
6568 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6569 /* set CMR:13 to start transmit when
6570 * next GoAhead (abort) is received
6571 */
6572 info->cmr_value |= BIT13;
6573 }
6574
6575 /* Setup the status and RCC (Frame Size) fields of the 1st */
6576 /* buffer entry in the transmit DMA buffer list. */
6577
6578 info->tx_buffer_list[0].status = info->cmr_value & 0xf000;
6579 info->tx_buffer_list[0].rcc = BufferSize;
6580 info->tx_buffer_list[0].count = BufferSize;
6581
6582 /* Copy frame data from 1st source buffer to the DMA buffers. */
6583 /* The frame data may span multiple DMA buffers. */
6584
6585 while( BufferSize ){
6586 /* Get a pointer to next DMA buffer entry. */
6587 pBufEntry = &info->tx_buffer_list[i++];
6588
6589 /* Calculate the number of bytes that can be copied from */
6590 /* the source buffer to this DMA buffer. */
6591 if ( BufferSize > DMABUFFERSIZE )
6592 Copycount = DMABUFFERSIZE;
6593 else
6594 Copycount = BufferSize;
6595
6596 /* Actually copy data from source buffer to DMA buffer. */
6597 /* Also set the data count for this individual DMA buffer. */
6598 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6599 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6600 else
6601 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6602
6603 pBufEntry->count = Copycount;
6604
6605 /* Advance source pointer and reduce remaining data count. */
6606 Buffer += Copycount;
6607 BufferSize -= Copycount;
6608 }
6609
6610 } /* end of mgsl_load_tx_dma_buffer() */
6611
6612 /*
6613 * mgsl_register_test()
6614 *
6615 * Performs a register test of the 16C32.
6616 *
6617 * Arguments: info pointer to device instance data
6618 * Return Value: TRUE if test passed, otherwise FALSE
6619 */
6620 BOOLEAN mgsl_register_test( struct mgsl_struct *info )
6621 {
6622 static unsigned short BitPatterns[] =
6623 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6624 static unsigned int Patterncount = sizeof(BitPatterns)/sizeof(unsigned short);
6625 unsigned int i;
6626 BOOLEAN rc = TRUE;
6627 unsigned long flags;
6628
6629 spin_lock_irqsave(&info->irq_spinlock,flags);
6630 usc_reset(info);
6631
6632 /* Verify the reset state of some registers. */
6633
6634 if ( (usc_InReg( info, SICR ) != 0) ||
6635 (usc_InReg( info, IVR ) != 0) ||
6636 (usc_InDmaReg( info, DIVR ) != 0) ){
6637 rc = FALSE;
6638 }
6639
6640 if ( rc == TRUE ){
6641 /* Write bit patterns to various registers but do it out of */
6642 /* sync, then read back and verify values. */
6643
6644 for ( i = 0 ; i < Patterncount ; i++ ) {
6645 usc_OutReg( info, TC0R, BitPatterns[i] );
6646 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6647 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6648 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6649 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6650 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6651
6652 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6653 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6654 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6655 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6656 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6657 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6658 rc = FALSE;
6659 break;
6660 }
6661 }
6662 }
6663
6664 usc_reset(info);
6665 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6666
6667 return rc;
6668
6669 } /* end of mgsl_register_test() */
6670
6671 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6672 *
6673 * Arguments: info pointer to device instance data
6674 * Return Value: TRUE if test passed, otherwise FALSE
6675 */
6676 BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
6677 {
6678 unsigned long EndTime;
6679 unsigned long flags;
6680
6681 spin_lock_irqsave(&info->irq_spinlock,flags);
6682 usc_reset(info);
6683
6684 /*
6685 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
6686 * The ISR sets irq_occurred to 1.
6687 */
6688
6689 info->irq_occurred = FALSE;
6690
6691 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
6692 /* Enable INTEN (Port 6, Bit12) */
6693 /* This connects the IRQ request signal to the ISA bus */
6694 /* on the ISA adapter. This has no effect for the PCI adapter */
6695 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
6696
6697 usc_EnableMasterIrqBit(info);
6698 usc_EnableInterrupts(info, IO_PIN);
6699 usc_ClearIrqPendingBits(info, IO_PIN);
6700
6701 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
6702 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
6703
6704 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6705
6706 EndTime=100;
6707 while( EndTime-- && !info->irq_occurred ) {
6708 set_current_state(TASK_INTERRUPTIBLE);
6709 schedule_timeout(jiffies_from_ms(10));
6710 }
6711
6712 spin_lock_irqsave(&info->irq_spinlock,flags);
6713 usc_reset(info);
6714 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6715
6716 if ( !info->irq_occurred )
6717 return FALSE;
6718 else
6719 return TRUE;
6720
6721 } /* end of mgsl_irq_test() */
6722
6723 /* mgsl_dma_test()
6724 *
6725 * Perform a DMA test of the 16C32. A small frame is
6726 * transmitted via DMA from a transmit buffer to a receive buffer
6727 * using single buffer DMA mode.
6728 *
6729 * Arguments: info pointer to device instance data
6730 * Return Value: TRUE if test passed, otherwise FALSE
6731 */
6732 BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
6733 {
6734 unsigned short FifoLevel;
6735 unsigned long phys_addr;
6736 unsigned int FrameSize;
6737 unsigned int i;
6738 char *TmpPtr;
6739 BOOLEAN rc = TRUE;
6740 unsigned short status;
6741 unsigned long EndTime;
6742 unsigned long flags;
6743 MGSL_PARAMS tmp_params;
6744
6745 /* save current port options */
6746 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
6747 /* load default port options */
6748 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
6749
6750 #define TESTFRAMESIZE 40
6751
6752 spin_lock_irqsave(&info->irq_spinlock,flags);
6753
6754 /* setup 16C32 for SDLC DMA transfer mode */
6755
6756 usc_reset(info);
6757 usc_set_sdlc_mode(info);
6758 usc_enable_loopback(info,1);
6759
6760 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
6761 * field of the buffer entry after fetching buffer address. This
6762 * way we can detect a DMA failure for a DMA read (which should be
6763 * non-destructive to system memory) before we try and write to
6764 * memory (where a failure could corrupt system memory).
6765 */
6766
6767 /* Receive DMA mode Register (RDMR)
6768 *
6769 * <15..14> 11 DMA mode = Linked List Buffer mode
6770 * <13> 1 RSBinA/L = store Rx status Block in List entry
6771 * <12> 0 1 = Clear count of List Entry after fetching
6772 * <11..10> 00 Address mode = Increment
6773 * <9> 1 Terminate Buffer on RxBound
6774 * <8> 0 Bus Width = 16bits
6775 * <7..0> ? status Bits (write as 0s)
6776 *
6777 * 1110 0010 0000 0000 = 0xe200
6778 */
6779
6780 usc_OutDmaReg( info, RDMR, 0xe200 );
6781
6782 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6783
6784
6785 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
6786
6787 FrameSize = TESTFRAMESIZE;
6788
6789 /* setup 1st transmit buffer entry: */
6790 /* with frame size and transmit control word */
6791
6792 info->tx_buffer_list[0].count = FrameSize;
6793 info->tx_buffer_list[0].rcc = FrameSize;
6794 info->tx_buffer_list[0].status = 0x4000;
6795
6796 /* build a transmit frame in 1st transmit DMA buffer */
6797
6798 TmpPtr = info->tx_buffer_list[0].virt_addr;
6799 for (i = 0; i < FrameSize; i++ )
6800 *TmpPtr++ = i;
6801
6802 /* setup 1st receive buffer entry: */
6803 /* clear status, set max receive buffer size */
6804
6805 info->rx_buffer_list[0].status = 0;
6806 info->rx_buffer_list[0].count = FrameSize + 4;
6807
6808 /* zero out the 1st receive buffer */
6809
6810 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
6811
6812 /* Set count field of next buffer entries to prevent */
6813 /* 16C32 from using buffers after the 1st one. */
6814
6815 info->tx_buffer_list[1].count = 0;
6816 info->rx_buffer_list[1].count = 0;
6817
6818
6819 /***************************/
6820 /* Program 16C32 receiver. */
6821 /***************************/
6822
6823 spin_lock_irqsave(&info->irq_spinlock,flags);
6824
6825 /* setup DMA transfers */
6826 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6827
6828 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
6829 phys_addr = info->rx_buffer_list[0].phys_entry;
6830 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
6831 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
6832
6833 /* Clear the Rx DMA status bits (read RDMR) and start channel */
6834 usc_InDmaReg( info, RDMR );
6835 usc_DmaCmd( info, DmaCmd_InitRxChannel );
6836
6837 /* Enable Receiver (RMR <1..0> = 10) */
6838 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
6839
6840 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6841
6842
6843 /*************************************************************/
6844 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
6845 /*************************************************************/
6846
6847 /* Wait 100ms for interrupt. */
6848 EndTime = jiffies + jiffies_from_ms(100);
6849
6850 for(;;) {
6851 if ( jiffies > EndTime ) {
6852 rc = FALSE;
6853 break;
6854 }
6855
6856 spin_lock_irqsave(&info->irq_spinlock,flags);
6857 status = usc_InDmaReg( info, RDMR );
6858 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6859
6860 if ( !(status & BIT4) && (status & BIT5) ) {
6861 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
6862 /* BUSY (BIT 5) is active (channel still active). */
6863 /* This means the buffer entry read has completed. */
6864 break;
6865 }
6866 }
6867
6868
6869 /******************************/
6870 /* Program 16C32 transmitter. */
6871 /******************************/
6872
6873 spin_lock_irqsave(&info->irq_spinlock,flags);
6874
6875 /* Program the Transmit Character Length Register (TCLR) */
6876 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6877
6878 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
6879 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6880
6881 /* Program the address of the 1st DMA Buffer Entry in linked list */
6882
6883 phys_addr = info->tx_buffer_list[0].phys_entry;
6884 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
6885 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
6886
6887 /* unlatch Tx status bits, and start transmit channel. */
6888
6889 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
6890 usc_DmaCmd( info, DmaCmd_InitTxChannel );
6891
6892 /* wait for DMA controller to fill transmit FIFO */
6893
6894 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
6895
6896 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6897
6898
6899 /**********************************/
6900 /* WAIT FOR TRANSMIT FIFO TO FILL */
6901 /**********************************/
6902
6903 /* Wait 100ms */
6904 EndTime = jiffies + jiffies_from_ms(100);
6905
6906 for(;;) {
6907 if ( jiffies > EndTime ) {
6908 rc = FALSE;
6909 break;
6910 }
6911
6912 spin_lock_irqsave(&info->irq_spinlock,flags);
6913 FifoLevel = usc_InReg(info, TICR) >> 8;
6914 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6915
6916 if ( FifoLevel < 16 )
6917 break;
6918 else
6919 if ( FrameSize < 32 ) {
6920 /* This frame is smaller than the entire transmit FIFO */
6921 /* so wait for the entire frame to be loaded. */
6922 if ( FifoLevel <= (32 - FrameSize) )
6923 break;
6924 }
6925 }
6926
6927
6928 if ( rc == TRUE )
6929 {
6930 /* Enable 16C32 transmitter. */
6931
6932 spin_lock_irqsave(&info->irq_spinlock,flags);
6933
6934 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
6935 usc_TCmd( info, TCmd_SendFrame );
6936 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
6937
6938 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6939
6940
6941 /******************************/
6942 /* WAIT FOR TRANSMIT COMPLETE */
6943 /******************************/
6944
6945 /* Wait 100ms */
6946 EndTime = jiffies + jiffies_from_ms(100);
6947
6948 /* While timer not expired wait for transmit complete */
6949
6950 spin_lock_irqsave(&info->irq_spinlock,flags);
6951 status = usc_InReg( info, TCSR );
6952 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6953
6954 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
6955 if ( jiffies > EndTime ) {
6956 rc = FALSE;
6957 break;
6958 }
6959
6960 spin_lock_irqsave(&info->irq_spinlock,flags);
6961 status = usc_InReg( info, TCSR );
6962 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6963 }
6964 }
6965
6966
6967 if ( rc == TRUE ){
6968 /* CHECK FOR TRANSMIT ERRORS */
6969 if ( status & (BIT5 + BIT1) )
6970 rc = FALSE;
6971 }
6972
6973 if ( rc == TRUE ) {
6974 /* WAIT FOR RECEIVE COMPLETE */
6975
6976 /* Wait 100ms */
6977 EndTime = jiffies + jiffies_from_ms(100);
6978
6979 /* Wait for 16C32 to write receive status to buffer entry. */
6980 status=info->rx_buffer_list[0].status;
6981 while ( status == 0 ) {
6982 if ( jiffies > EndTime ) {
6983 printk(KERN_ERR"mark 4\n");
6984 rc = FALSE;
6985 break;
6986 }
6987 status=info->rx_buffer_list[0].status;
6988 }
6989 }
6990
6991
6992 if ( rc == TRUE ) {
6993 /* CHECK FOR RECEIVE ERRORS */
6994 status = info->rx_buffer_list[0].status;
6995
6996 if ( status & (BIT8 + BIT3 + BIT1) ) {
6997 /* receive error has occured */
6998 rc = FALSE;
6999 } else {
7000 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7001 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7002 rc = FALSE;
7003 }
7004 }
7005 }
7006
7007 spin_lock_irqsave(&info->irq_spinlock,flags);
7008 usc_reset( info );
7009 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7010
7011 /* restore current port options */
7012 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7013
7014 return rc;
7015
7016 } /* end of mgsl_dma_test() */
7017
7018 /* mgsl_adapter_test()
7019 *
7020 * Perform the register, IRQ, and DMA tests for the 16C32.
7021 *
7022 * Arguments: info pointer to device instance data
7023 * Return Value: 0 if success, otherwise -ENODEV
7024 */
7025 int mgsl_adapter_test( struct mgsl_struct *info )
7026 {
7027 if ( debug_level >= DEBUG_LEVEL_INFO )
7028 printk( "%s(%d):Testing device %s\n",
7029 __FILE__,__LINE__,info->device_name );
7030
7031 if ( !mgsl_register_test( info ) ) {
7032 info->init_error = DiagStatus_AddressFailure;
7033 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7034 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7035 return -ENODEV;
7036 }
7037
7038 if ( !mgsl_irq_test( info ) ) {
7039 info->init_error = DiagStatus_IrqFailure;
7040 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7041 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7042 return -ENODEV;
7043 }
7044
7045 if ( !mgsl_dma_test( info ) ) {
7046 info->init_error = DiagStatus_DmaFailure;
7047 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7048 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7049 return -ENODEV;
7050 }
7051
7052 if ( debug_level >= DEBUG_LEVEL_INFO )
7053 printk( "%s(%d):device %s passed diagnostics\n",
7054 __FILE__,__LINE__,info->device_name );
7055
7056 return 0;
7057
7058 } /* end of mgsl_adapter_test() */
7059
7060 /* mgsl_memory_test()
7061 *
7062 * Test the shared memory on a PCI adapter.
7063 *
7064 * Arguments: info pointer to device instance data
7065 * Return Value: TRUE if test passed, otherwise FALSE
7066 */
7067 BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7068 {
7069 static unsigned long BitPatterns[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7070 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7071 unsigned long Patterncount = sizeof(BitPatterns)/sizeof(unsigned long);
7072 unsigned long i;
7073 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7074 unsigned long * TestAddr;
7075
7076 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7077 return TRUE;
7078
7079 TestAddr = (unsigned long *)info->memory_base;
7080
7081 /* Test data lines with test pattern at one location. */
7082
7083 for ( i = 0 ; i < Patterncount ; i++ ) {
7084 *TestAddr = BitPatterns[i];
7085 if ( *TestAddr != BitPatterns[i] )
7086 return FALSE;
7087 }
7088
7089 /* Test address lines with incrementing pattern over */
7090 /* entire address range. */
7091
7092 for ( i = 0 ; i < TestLimit ; i++ ) {
7093 *TestAddr = i * 4;
7094 TestAddr++;
7095 }
7096
7097 TestAddr = (unsigned long *)info->memory_base;
7098
7099 for ( i = 0 ; i < TestLimit ; i++ ) {
7100 if ( *TestAddr != i * 4 )
7101 return FALSE;
7102 TestAddr++;
7103 }
7104
7105 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7106
7107 return TRUE;
7108
7109 } /* End Of mgsl_memory_test() */
7110
7111
7112 /* mgsl_load_pci_memory()
7113 *
7114 * Load a large block of data into the PCI shared memory.
7115 * Use this instead of memcpy() or memmove() to move data
7116 * into the PCI shared memory.
7117 *
7118 * Notes:
7119 *
7120 * This function prevents the PCI9050 interface chip from hogging
7121 * the adapter local bus, which can starve the 16C32 by preventing
7122 * 16C32 bus master cycles.
7123 *
7124 * The PCI9050 documentation says that the 9050 will always release
7125 * control of the local bus after completing the current read
7126 * or write operation.
7127 *
7128 * It appears that as long as the PCI9050 write FIFO is full, the
7129 * PCI9050 treats all of the writes as a single burst transaction
7130 * and will not release the bus. This causes DMA latency problems
7131 * at high speeds when copying large data blocks to the shared
7132 * memory.
7133 *
7134 * This function in effect, breaks the a large shared memory write
7135 * into multiple transations by interleaving a shared memory read
7136 * which will flush the write FIFO and 'complete' the write
7137 * transation. This allows any pending DMA request to gain control
7138 * of the local bus in a timely fasion.
7139 *
7140 * Arguments:
7141 *
7142 * TargetPtr pointer to target address in PCI shared memory
7143 * SourcePtr pointer to source buffer for data
7144 * count count in bytes of data to copy
7145 *
7146 * Return Value: None
7147 */
7148 void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7149 unsigned short count )
7150 {
7151 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7152 #define PCI_LOAD_INTERVAL 64
7153
7154 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7155 unsigned short Index;
7156 unsigned long Dummy;
7157
7158 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7159 {
7160 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7161 Dummy = *((volatile unsigned long *)TargetPtr);
7162 TargetPtr += PCI_LOAD_INTERVAL;
7163 SourcePtr += PCI_LOAD_INTERVAL;
7164 }
7165
7166 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7167
7168 } /* End Of mgsl_load_pci_memory() */
7169
7170 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7171 {
7172 int i;
7173 int linecount;
7174 if (xmit)
7175 printk("%s tx data:\n",info->device_name);
7176 else
7177 printk("%s rx data:\n",info->device_name);
7178
7179 while(count) {
7180 if (count > 16)
7181 linecount = 16;
7182 else
7183 linecount = count;
7184
7185 for(i=0;i<linecount;i++)
7186 printk("%02X ",(unsigned char)data[i]);
7187 for(;i<17;i++)
7188 printk(" ");
7189 for(i=0;i<linecount;i++) {
7190 if (data[i]>=040 && data[i]<=0176)
7191 printk("%c",data[i]);
7192 else
7193 printk(".");
7194 }
7195 printk("\n");
7196
7197 data += linecount;
7198 count -= linecount;
7199 }
7200 } /* end of mgsl_trace_block() */
7201
7202 /* mgsl_tx_timeout()
7203 *
7204 * called when HDLC frame times out
7205 * update stats and do tx completion processing
7206 *
7207 * Arguments: context pointer to device instance data
7208 * Return Value: None
7209 */
7210 void mgsl_tx_timeout(unsigned long context)
7211 {
7212 struct mgsl_struct *info = (struct mgsl_struct*)context;
7213 unsigned long flags;
7214
7215 if ( debug_level >= DEBUG_LEVEL_INFO )
7216 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7217 __FILE__,__LINE__,info->device_name);
7218 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
7219 info->icount.txtimeout++;
7220 }
7221 spin_lock_irqsave(&info->irq_spinlock,flags);
7222 info->tx_active = 0;
7223 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7224
7225 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7226 usc_loopmode_cancel_transmit( info );
7227
7228 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7229
7230 #ifdef CONFIG_SYNCLINK_SYNCPPP
7231 if (info->netcount)
7232 mgsl_sppp_tx_done(info);
7233 else
7234 #endif
7235 mgsl_bh_transmit(info);
7236
7237 } /* end of mgsl_tx_timeout() */
7238
7239 /* signal that there are no more frames to send, so that
7240 * line is 'released' by echoing RxD to TxD when current
7241 * transmission is complete (or immediately if no tx in progress).
7242 */
7243 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7244 {
7245 unsigned long flags;
7246
7247 spin_lock_irqsave(&info->irq_spinlock,flags);
7248 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7249 if (info->tx_active)
7250 info->loopmode_send_done_requested = TRUE;
7251 else
7252 usc_loopmode_send_done(info);
7253 }
7254 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7255
7256 return 0;
7257 }
7258
7259 /* release the line by echoing RxD to TxD
7260 * upon completion of a transmit frame
7261 */
7262 void usc_loopmode_send_done( struct mgsl_struct * info )
7263 {
7264 info->loopmode_send_done_requested = FALSE;
7265 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7266 info->cmr_value &= ~BIT13;
7267 usc_OutReg(info, CMR, info->cmr_value);
7268 }
7269
7270 /* abort a transmit in progress while in HDLC LoopMode
7271 */
7272 void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7273 {
7274 /* reset tx dma channel and purge TxFifo */
7275 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7276 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7277 usc_loopmode_send_done( info );
7278 }
7279
7280 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7281 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7282 * we must clear CMR:13 to begin repeating TxData to RxData
7283 */
7284 void usc_loopmode_insert_request( struct mgsl_struct * info )
7285 {
7286 info->loopmode_insert_requested = TRUE;
7287
7288 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7289 * begin repeating TxData on RxData (complete insertion)
7290 */
7291 usc_OutReg( info, RICR,
7292 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7293
7294 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7295 info->cmr_value |= BIT13;
7296 usc_OutReg(info, CMR, info->cmr_value);
7297 }
7298
7299 /* return 1 if station is inserted into the loop, otherwise 0
7300 */
7301 int usc_loopmode_active( struct mgsl_struct * info)
7302 {
7303 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7304 }
7305
7306 /* return 1 if USC is in loop send mode, otherwise 0
7307 */
7308 int usc_loopmode_send_active( struct mgsl_struct * info )
7309 {
7310 return usc_InReg( info, CCSR ) & BIT6 ? 1 : 0 ;
7311 }
7312
7313 #ifdef CONFIG_SYNCLINK_SYNCPPP
7314 /* syncppp net device routines
7315 */
7316
7317 void mgsl_sppp_init(struct mgsl_struct *info)
7318 {
7319 struct net_device *d;
7320
7321 sprintf(info->netname,"mgsl%d",info->line);
7322
7323 info->if_ptr = &info->pppdev;
7324 info->netdev = info->pppdev.dev = &info->netdevice;
7325
7326 sppp_attach(&info->pppdev);
7327
7328 d = info->netdev;
7329 strcpy(d->name,info->netname);
7330 d->base_addr = info->io_base;
7331 d->irq = info->irq_level;
7332 d->dma = info->dma_level;
7333 d->priv = info;
7334 d->init = NULL;
7335 d->open = mgsl_sppp_open;
7336 d->stop = mgsl_sppp_close;
7337 d->hard_start_xmit = mgsl_sppp_tx;
7338 d->do_ioctl = mgsl_sppp_ioctl;
7339 d->get_stats = mgsl_net_stats;
7340 d->tx_timeout = mgsl_sppp_tx_timeout;
7341 d->watchdog_timeo = 10*HZ;
7342
7343 dev_init_buffers(d);
7344
7345 if (register_netdev(d) == -1) {
7346 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
7347 sppp_detach(info->netdev);
7348 return;
7349 }
7350
7351 if (debug_level >= DEBUG_LEVEL_INFO)
7352 printk("mgsl_sppp_init()\n");
7353 }
7354
7355 void mgsl_sppp_delete(struct mgsl_struct *info)
7356 {
7357 if (debug_level >= DEBUG_LEVEL_INFO)
7358 printk("mgsl_sppp_delete(%s)\n",info->netname);
7359 sppp_detach(info->netdev);
7360 unregister_netdev(info->netdev);
7361 }
7362
7363 int mgsl_sppp_open(struct net_device *d)
7364 {
7365 struct mgsl_struct *info = d->priv;
7366 int err, flags;
7367
7368 if (debug_level >= DEBUG_LEVEL_INFO)
7369 printk("mgsl_sppp_open(%s)\n",info->netname);
7370
7371 spin_lock_irqsave(&info->netlock, flags);
7372 if (info->count != 0 || info->netcount != 0) {
7373 printk(KERN_WARNING "%s: sppp_open returning busy\n", info->netname);
7374 spin_unlock_irqrestore(&info->netlock, flags);
7375 return -EBUSY;
7376 }
7377 info->netcount=1;
7378 MOD_INC_USE_COUNT;
7379 spin_unlock_irqrestore(&info->netlock, flags);
7380
7381 /* claim resources and init adapter */
7382 if ((err = startup(info)) != 0)
7383 goto open_fail;
7384
7385 /* allow syncppp module to do open processing */
7386 if ((err = sppp_open(d)) != 0) {
7387 shutdown(info);
7388 goto open_fail;
7389 }
7390
7391 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7392 mgsl_program_hw(info);
7393
7394 d->trans_start = jiffies;
7395 netif_start_queue(d);
7396 return 0;
7397
7398 open_fail:
7399 spin_lock_irqsave(&info->netlock, flags);
7400 info->netcount=0;
7401 MOD_DEC_USE_COUNT;
7402 spin_unlock_irqrestore(&info->netlock, flags);
7403 return err;
7404 }
7405
7406 void mgsl_sppp_tx_timeout(struct net_device *dev)
7407 {
7408 struct mgsl_struct *info = dev->priv;
7409 int flags;
7410
7411 if (debug_level >= DEBUG_LEVEL_INFO)
7412 printk("mgsl_sppp_tx_timeout(%s)\n",info->netname);
7413
7414 info->netstats.tx_errors++;
7415 info->netstats.tx_aborted_errors++;
7416
7417 spin_lock_irqsave(&info->irq_spinlock,flags);
7418 usc_stop_transmitter(info);
7419 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7420
7421 netif_wake_queue(dev);
7422 }
7423
7424 int mgsl_sppp_tx(struct sk_buff *skb, struct net_device *dev)
7425 {
7426 struct mgsl_struct *info = dev->priv;
7427 unsigned long flags;
7428
7429 if (debug_level >= DEBUG_LEVEL_INFO)
7430 printk("mgsl_sppp_tx(%s)\n",info->netname);
7431
7432 netif_stop_queue(dev);
7433
7434 info->xmit_cnt = skb->len;
7435 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7436 info->netstats.tx_packets++;
7437 info->netstats.tx_bytes += skb->len;
7438 dev_kfree_skb(skb);
7439
7440 dev->trans_start = jiffies;
7441
7442 spin_lock_irqsave(&info->irq_spinlock,flags);
7443 if (!info->tx_active)
7444 usc_start_transmitter(info);
7445 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7446
7447 return 0;
7448 }
7449
7450 int mgsl_sppp_close(struct net_device *d)
7451 {
7452 struct mgsl_struct *info = d->priv;
7453 unsigned long flags;
7454
7455 if (debug_level >= DEBUG_LEVEL_INFO)
7456 printk("mgsl_sppp_close(%s)\n",info->netname);
7457
7458 /* shutdown adapter and release resources */
7459 shutdown(info);
7460
7461 /* allow syncppp to do close processing */
7462 sppp_close(d);
7463 netif_stop_queue(d);
7464
7465 spin_lock_irqsave(&info->netlock, flags);
7466 info->netcount=0;
7467 MOD_DEC_USE_COUNT;
7468 spin_unlock_irqrestore(&info->netlock, flags);
7469 return 0;
7470 }
7471
7472 void mgsl_sppp_rx_done(struct mgsl_struct *info, char *buf, int size)
7473 {
7474 struct sk_buff *skb = dev_alloc_skb(size);
7475 if (debug_level >= DEBUG_LEVEL_INFO)
7476 printk("mgsl_sppp_rx_done(%s)\n",info->netname);
7477 if (skb == NULL) {
7478 printk(KERN_NOTICE "%s: cant alloc skb, dropping packet\n",
7479 info->netname);
7480 info->netstats.rx_dropped++;
7481 return;
7482 }
7483
7484 memcpy(skb_put(skb, size),buf,size);
7485
7486 skb->protocol = htons(ETH_P_WAN_PPP);
7487 skb->dev = info->netdev;
7488 skb->mac.raw = skb->data;
7489 info->netstats.rx_packets++;
7490 info->netstats.rx_bytes += size;
7491 netif_rx(skb);
7492 info->netdev->trans_start = jiffies;
7493 }
7494
7495 void mgsl_sppp_tx_done(struct mgsl_struct *info)
7496 {
7497 if (netif_queue_stopped(info->netdev))
7498 netif_wake_queue(info->netdev);
7499 }
7500
7501 struct net_device_stats *mgsl_net_stats(struct net_device *dev)
7502 {
7503 struct mgsl_struct *info = dev->priv;
7504 if (debug_level >= DEBUG_LEVEL_INFO)
7505 printk("mgsl_net_stats(%s)\n",info->netname);
7506 return &info->netstats;
7507 }
7508
7509 int mgsl_sppp_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7510 {
7511 struct mgsl_struct *info = (struct mgsl_struct *)dev->priv;
7512 if (debug_level >= DEBUG_LEVEL_INFO)
7513 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
7514 info->netname, cmd );
7515 return sppp_do_ioctl(dev, ifr, cmd);
7516 }
7517
7518 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
7519
7520 static int __init synclink_init_one (struct pci_dev *dev,
7521 const struct pci_device_id *ent)
7522 {
7523 struct mgsl_struct *info;
7524
7525 if (pci_enable_device(dev)) {
7526 printk("error enabling pci device %p\n", dev);
7527 return -EIO;
7528 }
7529
7530 if (!(info = mgsl_allocate_device())) {
7531 printk("can't allocate device instance data.\n");
7532 return -EIO;
7533 }
7534
7535 /* Copy user configuration info to device instance data */
7536
7537 info->io_base = pci_resource_start(dev, 2);
7538 info->irq_level = dev->irq;
7539 info->phys_memory_base = pci_resource_start(dev, 3);
7540
7541 /* Because veremap only works on page boundaries we must map
7542 * a larger area than is actually implemented for the LCR
7543 * memory range. We map a full page starting at the page boundary.
7544 */
7545 info->phys_lcr_base = pci_resource_start(dev, 0);
7546 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
7547 info->phys_lcr_base &= ~(PAGE_SIZE-1);
7548
7549 info->bus_type = MGSL_BUS_TYPE_PCI;
7550 info->io_addr_size = 8;
7551 info->irq_flags = SA_SHIRQ;
7552
7553 /* Store the PCI9050 misc control register value because a flaw
7554 * in the PCI9050 prevents LCR registers from being read if
7555 * BIOS assigns an LCR base address with bit 7 set.
7556 *
7557 * Only the misc control register is accessed for which only
7558 * write access is needed, so set an initial value and change
7559 * bits to the device instance data as we write the value
7560 * to the actual misc control register.
7561 */
7562 info->misc_ctrl_value = 0x087e4546;
7563
7564 mgsl_add_device(info);
7565
7566 return 0;
7567 }
7568
7569 static void __exit synclink_remove_one (struct pci_dev *dev)
7570 {
7571 }
7572
7573
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.