1 /* $Id: vino.h,v 1.2 1999/02/09 23:03:53 ulfc Exp $
2 * drivers/sgi/vino.h
3 *
4 * Copyright (C) 1999 Ulf Carlsson (ulfc@bun.falkenberg.se)
5 */
6
7 #define VINO_BASE 0x0008000
8
9 #define VINO_REVID 0x0000
10 #define VINO_CTRL 0x0008
11 #define VINO_INTSTAT 0x0010 /* Interrupt status */
12 #define VINO_I2C_CTRL 0x0018
13 #define VINO_I2C_DATA 0x0020
14 #define VINO_A_ALPHA 0x0028 /* Channel A ... */
15 #define VINO_A_CLIPS 0x0030 /* Clipping start */
16 #define VINO_A_CLIPE 0x0038 /* Clipping end */
17 #define VINO_A_FRAMERT 0x0040 /* Framerate */
18 #define VINO_A_FLDCNT 0x0048 /* Field counter */
19 #define VINO_A_LNSZ 0x0050
20 #define VINO_A_LNCNT 0x0058
21 #define VINO_A_PGIX 0x0060 /* Page index */
22 #define VINO_A_DESC_PTR 0x0068 /* Ptr to next four descriptors */
23 #define VINO_A_DESC_TLB_PTR 0x0070 /* Ptr to start of descriptor table */
24 #define VINO_A_DESC_DATA0 0x0078 /* Descriptor data 0 */
25 #define VINO_A_DESC_DATA1 0x0080 /* ... */
26 #define VINO_A_DESC_DATA2 0x0088
27 #define VINO_A_DESC_DATA3 0x0090
28 #define VINO_A_FIFO_THRESHOLD 0x0098 /* FIFO threshold */
29 #define VINO_A_FIFO_RP 0x00a0
30 #define VINO_A_FIFO_WP 0x00a8
31 #define VINO_B_ALPHA 0x00b0 /* Channel B ... */
32 #define VINO_B_CLIPS 0x00b8
33 #define VINO_B_CLIPE 0x00c0
34 #define VINO_B_FRAMERT 0x00c8
35 #define VINO_B_FLDCNT 0x00d0
36 #define VINO_B_LNSZ 0x00d8
37 #define VINO_B_LNCNT 0x00e0
38 #define VINO_B_PGIX 0x00e8
39 #define VINO_B_DESC_PTR 0x00f0
40 #define VINO_B_DESC_TLB_PTR 0x00f8
41 #define VINO_B_DESC_DATA0 0x0100
42 #define VINO_B_DESC_DATA1 0x0108
43 #define VINO_B_DESC_DATA2 0x0110
44 #define VINO_B_DESC_DATA3 0x0118
45 #define VINO_B_FIFO_THRESHOLD 0x0120
46 #define VINO_B_FIFO_RP 0x0128
47 #define VINO_B_FIFO_WP 0x0130
48
49 /* Bits in the VINO_REVID register */
50
51 #define VINO_REVID_REV_MASK 0x000f /* bits 0:3 */
52 #define VINO_REVID_ID_MASK 0x00f0 /* bits 4:7 */
53
54 /* Bits in the VINO_CTRL register */
55
56 #define VINO_CTRL_LITTLE_ENDIAN (1<<0)
57 #define VINO_CTRL_A_FIELD_TRANS_INT (1<<1) /* Field transferred int */
58 #define VINO_CTRL_A_FIFO_OF_INT (1<<2) /* FIFO overflow int */
59 #define VINO_CTRL_A_END_DESC_TBL_INT (1<<3) /* End of desc table int */
60 #define VINO_CTRL_B_FIELD_TRANS_INT (1<<4) /* Field transferred int */
61 #define VINO_CTRL_B_FIFO_OF_INT (1<<5) /* FIFO overflow int */
62 #define VINO_CTRL_B_END_DESC_TLB_INT (1<<6) /* End of desc table int */
63 #define VINO_CTRL_A_DMA_ENBL (1<<7)
64 #define VINO_CTRL_A_INTERLEAVE_ENBL (1<<8)
65 #define VINO_CTRL_A_SYNC_ENBL (1<<9)
66 #define VINO_CTRL_A_SELECT (1<<10) /* 1=D1 0=Philips */
67 #define VINO_CTRL_A_RGB (1<<11) /* 1=RGB 0=YUV */
68 #define VINO_CTRL_A_LUMA_ONLY (1<<12)
69 #define VINO_CTRL_A_DEC_ENBL (1<<13) /* Decimation */
70 #define VINO_CTRL_A_DEC_SCALE_MASK 0x1c000 /* bits 14:17 */
71 #define VINO_CTRL_A_DEC_HOR_ONLY (1<<17) /* Horizontal only */
72 #define VINO_CTRL_A_DITHER (1<<18) /* 24 -> 8 bit dither */
73 #define VINO_CTRL_B_DMA_ENBL (1<<19)
74 #define VINO_CTRL_B_INTERLEAVE_ENBL (1<<20)
75 #define VINO_CTRL_B_SYNC_ENBL (1<<21)
76 #define VINO_CTRL_B_SELECT (1<<22) /* 1=D1 0=Philips */
77 #define VINO_CTRL_B_RGB (1<<22) /* 1=RGB 0=YUV */
78 #define VINO_CTRL_B_LUMA_ONLY (1<<23)
79 #define VINO_CTRL_B_DEC_ENBL (1<<24) /* Decimation */
80 #define VINO_CTRL_B_DEC_SCALE_MASK 0x1c000000 /* bits 25:28 */
81 #define VINO_CTRL_B_DEC_HOR_ONLY (1<<29) /* Decimation horizontal only */
82 #define VINO_CTRL_B_DITHER (1<<30) /* ChanB 24 -> 8 bit dither */
83
84 /* Bits in the Interrupt and Status register */
85
86 #define VINO_INTSTAT_A_FIELD_TRANS (1<<0) /* Field transferred int */
87 #define VINO_INTSTAT_A_FIFO_OF (1<<1) /* FIFO overflow int */
88 #define VINO_INTSTAT_A_END_DESC_TBL (1<<2) /* End of desc table int */
89 #define VINO_INTSTAT_B_FIELD_TRANS (1<<3) /* Field transferred int */
90 #define VINO_INTSTAT_B_FIFO_OF (1<<4) /* FIFO overflow int */
91 #define VINO_INTSTAT_B_END_DESC_TBL (1<<5) /* End of desc table int */
92
93 /* Bits in the Clipping Start register */
94
95 #define VINO_CLIPS_START 0x3ff /* bits 0:9 */
96 #define VINO_CLIPS_ODD_MASK 0x7fc00 /* bits 10:18 */
97 #define VINO_CLIPS_EVEN_MASK 0xff80000 /* bits 19:27 */
98
99 /* Bits in the Clipping End register */
100
101 #define VINO_CLIPE_END 0x3ff /* bits 0:9 */
102 #define VINO_CLIPE_ODD_MASK 0x7fc00 /* bits 10:18 */
103 #define VINO_CLIPE_EVEN_MASK 0xff80000 /* bits 19:27 */
104
105 /* Bits in the Frame Rate register */
106
107 #define VINO_FRAMERT_PAL (1<<0) /* 0=NTSC 1=PAL */
108 #define VINO_FRAMERT_RT_MASK 0x1ffe /* bits 1:12 */
109
110 /* Bits in the VINO_I2C_CTRL */
111
112 #define VINO_CTRL_I2C_IDLE (1<<0) /* write: 0=force idle
113 * read: 0=idle 1=not idle */
114 #define VINO_CTRL_I2C_DIR (1<<1) /* 0=read 1=write */
115 #define VINO_CTRL_I2C_MORE_BYTES (1<<2) /* 0=last byte 1=more bytes */
116 #define VINO_CTRL_I2C_TRANS_BUSY (1<<4) /* 0=trans done 1=trans busy */
117 #define VINO_CTRL_I2C_ACK (1<<5) /* 0=ack received 1=ack not */
118 #define VINO_CTRL_I2C_BUS_ERROR (1<<7) /* 0=no bus err 1=bus err */
119
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