1 /*
2 * linux/drivers/ide/sis5513.c Version 0.11 June 9, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to SIS Taiwan for direct support and hardware.
8 * Tested and designed on the SiS620/5513 chipset.
9 */
10
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/timer.h>
16 #include <linux/mm.h>
17 #include <linux/ioport.h>
18 #include <linux/blkdev.h>
19 #include <linux/hdreg.h>
20
21 #include <linux/interrupt.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/ide.h>
25
26 #include <asm/io.h>
27 #include <asm/irq.h>
28
29 #include "ide_modes.h"
30
31 #define DISPLAY_SIS_TIMINGS
32 #define SIS5513_DEBUG_DRIVE_INFO 0
33
34 static struct pci_dev *host_dev = NULL;
35
36 #define SIS5513_FLAG_ATA_00 0x00000000
37 #define SIS5513_FLAG_ATA_16 0x00000001
38 #define SIS5513_FLAG_ATA_33 0x00000002
39 #define SIS5513_FLAG_ATA_66 0x00000004
40 #define SIS5513_FLAG_LATENCY 0x00000010
41
42 static const struct {
43 const char *name;
44 unsigned short host_id;
45 unsigned int flags;
46 } SiSHostChipInfo[] = {
47 { "SiS530", PCI_DEVICE_ID_SI_530, SIS5513_FLAG_ATA_66, },
48 { "SiS540", PCI_DEVICE_ID_SI_540, SIS5513_FLAG_ATA_66, },
49 { "SiS620", PCI_DEVICE_ID_SI_620, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
50 { "SiS630", PCI_DEVICE_ID_SI_630, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
51 { "SiS730", PCI_DEVICE_ID_SI_730, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
52 { "SiS5591", PCI_DEVICE_ID_SI_5591, SIS5513_FLAG_ATA_33, },
53 { "SiS5597", PCI_DEVICE_ID_SI_5597, SIS5513_FLAG_ATA_33, },
54 { "SiS5600", PCI_DEVICE_ID_SI_5600, SIS5513_FLAG_ATA_33, },
55 { "SiS5511", PCI_DEVICE_ID_SI_5511, SIS5513_FLAG_ATA_16, },
56 };
57
58 #if 0
59
60 static struct _pio_mode_mapping {
61 byte data_active;
62 byte recovery;
63 byte pio_mode;
64 } pio_mode_mapping[] = {
65 { 8, 12, 0 },
66 { 6, 7, 1 },
67 { 4, 4, 2 },
68 { 3, 3, 3 },
69 { 3, 1, 4 }
70 };
71
72 static struct _dma_mode_mapping {
73 byte data_active;
74 byte recovery;
75 byte dma_mode;
76 } dma_mode_mapping[] = {
77 { 8, 8, 0 },
78 { 3, 2, 1 },
79 { 3, 1, 2 }
80 };
81
82 static struct _udma_mode_mapping {
83 byte cycle_time;
84 char * udma_mode;
85 } udma_mode_mapping[] = {
86 { 8, "Mode 0" },
87 { 6, "Mode 1" },
88 { 4, "Mode 2" },
89 { 3, "Mode 3" },
90 { 2, "Mode 4" },
91 { 0, "Undefined" }
92 };
93
94 static __inline__ char * find_udma_mode (byte cycle_time)
95 {
96 int n;
97
98 for (n = 0; n <= 4; n++)
99 if (udma_mode_mapping[n].cycle_time <= cycle_time)
100 return udma_mode_mapping[n].udma_mode;
101 return udma_mode_mapping[4].udma_mode;
102 }
103 #endif
104
105 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
106 #include <linux/stat.h>
107 #include <linux/proc_fs.h>
108
109 static int sis_get_info(char *, char **, off_t, int);
110 extern int (*sis_display_info)(char *, char **, off_t, int); /* ide-proc.c */
111 static struct pci_dev *bmide_dev;
112
113 static char *cable_type[] = {
114 "80 pins",
115 "40 pins"
116 };
117
118 static char *recovery_time [] ={
119 "12 PCICLK", "1 PCICLK",
120 "2 PCICLK", "3 PCICLK",
121 "4 PCICLK", "5 PCICLCK",
122 "6 PCICLK", "7 PCICLCK",
123 "8 PCICLK", "9 PCICLCK",
124 "10 PCICLK", "11 PCICLK",
125 "13 PCICLK", "14 PCICLK",
126 "15 PCICLK", "15 PCICLK"
127 };
128
129 static char * cycle_time [] = {
130 "Undefined", "2 CLCK",
131 "3 CLK", "4 CLK",
132 "5 CLK", "6 CLK",
133 "7 CLK", "8 CLK"
134 };
135
136 static char * active_time [] = {
137 "8 PCICLK", "1 PCICLCK",
138 "2 PCICLK", "2 PCICLK",
139 "4 PCICLK", "5 PCICLK",
140 "6 PCICLK", "12 PCICLK"
141 };
142
143 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
144 {
145 int rc;
146 char *p = buffer;
147 byte reg,reg1;
148 u16 reg2, reg3;
149
150 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
151 rc = pci_read_config_byte(bmide_dev, 0x4a, ®);
152 p += sprintf(p, "Channel Status: %s \t \t \t \t %s \n",
153 (reg & 0x02) ? "On" : "Off",
154 (reg & 0x04) ? "On" : "Off");
155
156 rc = pci_read_config_byte(bmide_dev, 0x09, ®);
157 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
158 (reg & 0x01) ? "Native" : "Compatible",
159 (reg & 0x04) ? "Native" : "Compatible");
160
161 rc = pci_read_config_byte(bmide_dev, 0x48, ®);
162 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
163 (reg & 0x10) ? cable_type[1] : cable_type[0],
164 (reg & 0x20) ? cable_type[1] : cable_type[0]);
165
166 rc = pci_read_config_word(bmide_dev, 0x4c, ®2);
167 rc = pci_read_config_word(bmide_dev, 0x4e, ®3);
168 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
169 reg2, reg3);
170
171 rc = pci_read_config_byte(bmide_dev, 0x4b, ®);
172 p += sprintf(p, "Drive 0: Postwrite %s \t \t Postwrite %s\n",
173 (reg & 0x10) ? "Enabled" : "Disabled",
174 (reg & 0x40) ? "Enabled" : "Disabled");
175 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
176 (reg & 0x01) ? "Enabled" : "Disabled",
177 (reg & 0x04) ? "Enabled" : "Disabled");
178
179 rc = pci_read_config_byte(bmide_dev, 0x41, ®);
180 rc = pci_read_config_byte(bmide_dev, 0x45, ®1);
181 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
182 (reg & 0x80) ? "Enabled" : "Disabled",
183 (reg1 & 0x80) ? "Enabled" : "Disabled");
184 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
185 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
186 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
187 active_time[(reg & 0x07)], active_time[(reg1 &0x07)] );
188
189 rc = pci_read_config_byte(bmide_dev, 0x40, ®);
190 rc = pci_read_config_byte(bmide_dev, 0x44, ®1);
191 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
192 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
193
194
195 rc = pci_read_config_byte(bmide_dev, 0x4b, ®);
196 p += sprintf(p, "Drive 1: Postwrite %s \t \t Postwrite %s\n",
197 (reg & 0x20) ? "Enabled" : "Disabled",
198 (reg & 0x80) ? "Enabled" : "Disabled");
199 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
200 (reg & 0x02) ? "Enabled" : "Disabled",
201 (reg & 0x08) ? "Enabled" : "Disabled");
202
203 rc = pci_read_config_byte(bmide_dev, 0x43, ®);
204 rc = pci_read_config_byte(bmide_dev, 0x47, ®1);
205 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
206 (reg & 0x80) ? "Enabled" : "Disabled",
207 (reg1 & 0x80) ? "Enabled" : "Disabled");
208 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
209 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
210 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
211 active_time[(reg & 0x07)], active_time[(reg1 &0x07)] );
212
213 rc = pci_read_config_byte(bmide_dev, 0x42, ®);
214 rc = pci_read_config_byte(bmide_dev, 0x46, ®1);
215 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
216 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
217 return p-buffer;
218 }
219 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
220
221 byte sis_proc = 0;
222 extern char *ide_xfer_verbose (byte xfer_rate);
223
224 static void config_drive_art_rwp (ide_drive_t *drive)
225 {
226 ide_hwif_t *hwif = HWIF(drive);
227 struct pci_dev *dev = hwif->pci_dev;
228
229 byte reg4bh = 0;
230 byte rw_prefetch = (0x11 << drive->dn);
231
232 pci_read_config_byte(dev, 0x4b, ®4bh);
233 if (drive->media != ide_disk)
234 return;
235
236 if ((reg4bh & rw_prefetch) != rw_prefetch)
237 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
238 }
239
240 static void config_art_rwp_pio (ide_drive_t *drive, byte pio)
241 {
242 ide_hwif_t *hwif = HWIF(drive);
243 struct pci_dev *dev = hwif->pci_dev;
244
245 byte timing, drive_pci, test1, test2;
246
247 unsigned short eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
248 unsigned short xfer_pio = drive->id->eide_pio_modes;
249
250 config_drive_art_rwp(drive);
251 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
252
253 if (xfer_pio> 4)
254 xfer_pio = 0;
255
256 if (drive->id->eide_pio_iordy > 0) {
257 for (xfer_pio = 5;
258 xfer_pio>0 &&
259 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
260 xfer_pio--);
261 } else {
262 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
263 (drive->id->eide_pio_modes & 2) ? 0x04 :
264 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
265 }
266
267 timing = (xfer_pio >= pio) ? xfer_pio : pio;
268
269 /*
270 * Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
271 * Active time 8T (240ns) 6T (180ns) 4T (120ns) 3T (90ns) 3T (90ns)
272 * 0x41 2:0 bits 000 110 100 011 011
273 * Recovery time 12T (360ns) 7T (210ns) 4T (120ns) 3T (90ns) 1T (30ns)
274 * 0x40 3:0 bits 0000 0111 0100 0011 0001
275 * Cycle time 20T (600ns) 13T (390ns) 8T (240ns) 6T (180ns) 4T (120ns)
276 */
277
278 switch(drive->dn) {
279 case 0: drive_pci = 0x40; break;
280 case 1: drive_pci = 0x42; break;
281 case 2: drive_pci = 0x44; break;
282 case 3: drive_pci = 0x46; break;
283 default: return;
284 }
285
286 pci_read_config_byte(dev, drive_pci, &test1);
287 pci_read_config_byte(dev, drive_pci|0x01, &test2);
288
289 /*
290 * Do a blanket clear of active and recovery timings.
291 */
292
293 test1 &= ~0x07;
294 test2 &= ~0x0F;
295
296 switch(timing) {
297 case 4: test1 |= 0x01; test2 |= 0x03; break;
298 case 3: test1 |= 0x03; test2 |= 0x03; break;
299 case 2: test1 |= 0x04; test2 |= 0x04; break;
300 case 1: test1 |= 0x07; test2 |= 0x06; break;
301 default: break;
302 }
303
304 pci_write_config_byte(dev, drive_pci, test1);
305 pci_write_config_byte(dev, drive_pci|0x01, test2);
306 }
307
308 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
309 {
310 int err;
311 byte speed;
312
313 switch(pio) {
314 case 4: speed = XFER_PIO_4; break;
315 case 3: speed = XFER_PIO_3; break;
316 case 2: speed = XFER_PIO_2; break;
317 case 1: speed = XFER_PIO_1; break;
318 default: speed = XFER_PIO_0; break;
319 }
320
321 config_art_rwp_pio(drive, pio);
322 drive->current_speed = speed;
323 err = ide_config_drive_speed(drive, speed);
324 return err;
325 }
326
327 static int sis5513_tune_chipset (ide_drive_t *drive, byte speed)
328 {
329 ide_hwif_t *hwif = HWIF(drive);
330 struct pci_dev *dev = hwif->pci_dev;
331
332 byte drive_pci, test1, test2;
333 byte unmask, four_two, mask = 0;
334
335 if (host_dev) {
336 switch(host_dev->device) {
337 case PCI_DEVICE_ID_SI_530:
338 case PCI_DEVICE_ID_SI_540:
339 case PCI_DEVICE_ID_SI_620:
340 case PCI_DEVICE_ID_SI_630:
341 case PCI_DEVICE_ID_SI_730:
342 unmask = 0xF0;
343 four_two = 0x01;
344 break;
345 default:
346 unmask = 0xE0;
347 four_two = 0x00;
348 break;
349 }
350 } else {
351 unmask = 0xE0;
352 four_two = 0x00;
353 }
354
355 switch(drive->dn) {
356 case 0: drive_pci = 0x40;break;
357 case 1: drive_pci = 0x42;break;
358 case 2: drive_pci = 0x44;break;
359 case 3: drive_pci = 0x46;break;
360 default: return ide_dma_off;
361 }
362
363 pci_read_config_byte(dev, drive_pci, &test1);
364 pci_read_config_byte(dev, drive_pci|0x01, &test2);
365
366 if ((speed <= XFER_MW_DMA_2) && (test2 & 0x80)) {
367 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~0x80);
368 pci_read_config_byte(dev, drive_pci|0x01, &test2);
369 } else {
370 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
371 }
372
373 switch(speed) {
374 #ifdef CONFIG_BLK_DEV_IDEDMA
375 case XFER_UDMA_5: mask = 0x80; break;
376 case XFER_UDMA_4: mask = 0x90; break;
377 case XFER_UDMA_3: mask = 0xA0; break;
378 case XFER_UDMA_2: mask = (four_two) ? 0xB0 : 0xA0; break;
379 case XFER_UDMA_1: mask = (four_two) ? 0xD0 : 0xC0; break;
380 case XFER_UDMA_0: mask = unmask; break;
381 case XFER_MW_DMA_2:
382 case XFER_MW_DMA_1:
383 case XFER_MW_DMA_0:
384 case XFER_SW_DMA_2:
385 case XFER_SW_DMA_1:
386 case XFER_SW_DMA_0: break;
387 #endif /* CONFIG_BLK_DEV_IDEDMA */
388 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
389 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
390 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
391 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
392 case XFER_PIO_0:
393 default: return((int) config_chipset_for_pio(drive, 0));
394 }
395
396 if (speed > XFER_MW_DMA_2)
397 pci_write_config_byte(dev, drive_pci|0x01, test2|mask);
398
399 drive->current_speed = speed;
400 return ((int) ide_config_drive_speed(drive, speed));
401 }
402
403 static void sis5513_tune_drive (ide_drive_t *drive, byte pio)
404 {
405 (void) config_chipset_for_pio(drive, pio);
406 }
407
408 #ifdef CONFIG_BLK_DEV_IDEDMA
409 /*
410 * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
411 */
412 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
413 {
414 struct hd_driveid *id = drive->id;
415 ide_hwif_t *hwif = HWIF(drive);
416
417 byte four_two = 0, speed = 0;
418 int err;
419
420 byte unit = (drive->select.b.unit & 0x01);
421 byte udma_66 = eighty_ninty_three(drive);
422 byte ultra_100 = 0;
423
424 if (host_dev) {
425 switch(host_dev->device) {
426 case PCI_DEVICE_ID_SI_730:
427 ultra_100 = 1;
428 case PCI_DEVICE_ID_SI_530:
429 case PCI_DEVICE_ID_SI_540:
430 case PCI_DEVICE_ID_SI_620:
431 case PCI_DEVICE_ID_SI_630:
432 four_two = 0x01;
433 break;
434 default:
435 four_two = 0x00; break;
436 }
437 }
438
439 if ((id->dma_ultra & 0x0020) && (ultra) && (udma_66) && (four_two) && (ultra_100))
440 speed = XFER_UDMA_5;
441 else if ((id->dma_ultra & 0x0010) && (ultra) && (udma_66) && (four_two))
442 speed = XFER_UDMA_4;
443 else if ((id->dma_ultra & 0x0008) && (ultra) && (udma_66) && (four_two))
444 speed = XFER_UDMA_3;
445 else if ((id->dma_ultra & 0x0004) && (ultra))
446 speed = XFER_UDMA_2;
447 else if ((id->dma_ultra & 0x0002) && (ultra))
448 speed = XFER_UDMA_1;
449 else if ((id->dma_ultra & 0x0001) && (ultra))
450 speed = XFER_UDMA_0;
451 else if (id->dma_mword & 0x0004)
452 speed = XFER_MW_DMA_2;
453 else if (id->dma_mword & 0x0002)
454 speed = XFER_MW_DMA_1;
455 else if (id->dma_mword & 0x0001)
456 speed = XFER_MW_DMA_0;
457 else if (id->dma_1word & 0x0004)
458 speed = XFER_SW_DMA_2;
459 else if (id->dma_1word & 0x0002)
460 speed = XFER_SW_DMA_1;
461 else if (id->dma_1word & 0x0001)
462 speed = XFER_SW_DMA_0;
463 else
464 return ((int) ide_dma_off_quietly);
465
466 outb(inb(hwif->dma_base+2)|(1<<(5+unit)), hwif->dma_base+2);
467
468 err = sis5513_tune_chipset(drive, speed);
469
470 #if SIS5513_DEBUG_DRIVE_INFO
471 printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn);
472 #endif /* SIS5513_DEBUG_DRIVE_INFO */
473
474 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
475 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
476 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
477 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
478 ide_dma_off_quietly);
479 }
480
481 static int config_drive_xfer_rate (ide_drive_t *drive)
482 {
483 struct hd_driveid *id = drive->id;
484 ide_dma_action_t dma_func = ide_dma_off_quietly;
485
486 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
487 /* Consult the list of known "bad" drives */
488 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
489 dma_func = ide_dma_off;
490 goto fast_ata_pio;
491 }
492 dma_func = ide_dma_off_quietly;
493 if (id->field_valid & 4) {
494 if (id->dma_ultra & 0x001F) {
495 /* Force if Capable UltraDMA */
496 dma_func = config_chipset_for_dma(drive, 1);
497 if ((id->field_valid & 2) &&
498 (dma_func != ide_dma_on))
499 goto try_dma_modes;
500 }
501 } else if (id->field_valid & 2) {
502 try_dma_modes:
503 if ((id->dma_mword & 0x0007) ||
504 (id->dma_1word & 0x0007)) {
505 /* Force if Capable regular DMA modes */
506 dma_func = config_chipset_for_dma(drive, 0);
507 if (dma_func != ide_dma_on)
508 goto no_dma_set;
509 }
510 } else if ((ide_dmaproc(ide_dma_good_drive, drive)) &&
511 (id->eide_dma_time > 150)) {
512 /* Consult the list of known "good" drives */
513 dma_func = config_chipset_for_dma(drive, 0);
514 if (dma_func != ide_dma_on)
515 goto no_dma_set;
516 } else {
517 goto fast_ata_pio;
518 }
519 } else if ((id->capability & 8) || (id->field_valid & 2)) {
520 fast_ata_pio:
521 dma_func = ide_dma_off_quietly;
522 no_dma_set:
523 (void) config_chipset_for_pio(drive, 5);
524 }
525
526 return HWIF(drive)->dmaproc(dma_func, drive);
527 }
528
529 /*
530 * sis5513_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
531 */
532 int sis5513_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
533 {
534 switch (func) {
535 case ide_dma_check:
536 config_drive_art_rwp(drive);
537 config_art_rwp_pio(drive, 5);
538 return config_drive_xfer_rate(drive);
539 default:
540 break;
541 }
542 return ide_dmaproc(func, drive); /* use standard DMA stuff */
543 }
544 #endif /* CONFIG_BLK_DEV_IDEDMA */
545
546 unsigned int __init pci_init_sis5513 (struct pci_dev *dev, const char *name)
547 {
548 struct pci_dev *host;
549 int i = 0;
550 byte latency = 0;
551
552 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
553
554 for (i = 0; i < ARRAY_SIZE (SiSHostChipInfo) && !host_dev; i++) {
555 host = pci_find_device (PCI_VENDOR_ID_SI,
556 SiSHostChipInfo[i].host_id,
557 NULL);
558 if (!host)
559 continue;
560
561 host_dev = host;
562 printk(SiSHostChipInfo[i].name);
563 printk("\n");
564 if (SiSHostChipInfo[i].flags & SIS5513_FLAG_LATENCY) {
565 if (latency != 0x10)
566 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
567 }
568 }
569
570 if (host_dev) {
571 byte reg52h = 0;
572
573 pci_read_config_byte(dev, 0x52, ®52h);
574 if (!(reg52h & 0x04)) {
575 /* set IDE controller to operate in Compabitility mode only */
576 pci_write_config_byte(dev, 0x52, reg52h|0x04);
577 }
578 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
579 if (!sis_proc) {
580 sis_proc = 1;
581 bmide_dev = dev;
582 sis_display_info = &sis_get_info;
583 }
584 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
585 }
586 return 0;
587 }
588
589 unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
590 {
591 byte reg48h = 0, ata66 = 0;
592 byte mask = hwif->channel ? 0x20 : 0x10;
593 pci_read_config_byte(hwif->pci_dev, 0x48, ®48h);
594
595 if (host_dev) {
596 switch(host_dev->device) {
597 case PCI_DEVICE_ID_SI_530:
598 case PCI_DEVICE_ID_SI_540:
599 case PCI_DEVICE_ID_SI_620:
600 case PCI_DEVICE_ID_SI_630:
601 case PCI_DEVICE_ID_SI_730:
602 ata66 = (reg48h & mask) ? 0 : 1;
603 default:
604 break;
605 }
606 }
607 return (ata66);
608 }
609
610 void __init ide_init_sis5513 (ide_hwif_t *hwif)
611 {
612
613 hwif->irq = hwif->channel ? 15 : 14;
614
615 hwif->tuneproc = &sis5513_tune_drive;
616 hwif->speedproc = &sis5513_tune_chipset;
617
618 if (!(hwif->dma_base))
619 return;
620
621 if (host_dev) {
622 switch(host_dev->device) {
623 #ifdef CONFIG_BLK_DEV_IDEDMA
624 case PCI_DEVICE_ID_SI_530:
625 case PCI_DEVICE_ID_SI_540:
626 case PCI_DEVICE_ID_SI_620:
627 case PCI_DEVICE_ID_SI_630:
628 case PCI_DEVICE_ID_SI_730:
629 case PCI_DEVICE_ID_SI_5600:
630 case PCI_DEVICE_ID_SI_5597:
631 case PCI_DEVICE_ID_SI_5591:
632 hwif->autodma = 1;
633 hwif->dmaproc = &sis5513_dmaproc;
634 break;
635 #endif /* CONFIG_BLK_DEV_IDEDMA */
636 default:
637 hwif->autodma = 0;
638 break;
639 }
640 }
641 return;
642 }
643
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.