1 /*
2 ** aic5800.h - Adaptec AIC-5800 PCI-IEEE1394 chip driver header file
3 ** Copyright (C)1999 Emanuel Pirker <epirker@edu.uni-klu.ac.at>
4 **
5 ** This program is free software; you can redistribute it and/or modify
6 ** it under the terms of the GNU General Public License as published by
7 ** the Free Software Foundation; either version 2 of the License, or
8 ** (at your option) any later version.
9 **
10 ** This program is distributed in the hope that it will be useful,
11 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ** GNU General Public License for more details.
14 **
15 ** You should have received a copy of the GNU General Public License
16 ** along with this program; if not, write to the Free Software
17 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 **
19 */
20
21 #ifndef AIC5800_H
22 #define AIC5800_H
23
24 #define AIC5800_DRIVER_NAME "aic5800"
25
26 #define MAX_AIC5800_CARDS 4
27 #define AIC5800_REGSPACE_SIZE 512
28 #define AIC5800_PBUF_SIZE 512
29
30 #define MAX_AT_PROGRAM_SIZE 10
31 #define AIC5800_ARFIFO_SIZE 128
32
33 struct dma_cmd {
34 u32 control;
35 u32 address;
36 u32 branchAddress;
37 u32 status;
38 };
39
40 struct aic5800 {
41 int id; /* sequential card number */
42
43 struct pci_dev *dev;
44
45 /* remapped memory spaces */
46 void *registers;
47
48 struct hpsb_host *host;
49
50 int phyid, isroot;
51
52 void *rcv_page;
53 void *pbuf;
54
55 struct dma_cmd *AT_program;
56 u32 *AT_status;
57 struct dma_cmd *AR_program;
58 u32 *AR_status;
59 int AR_active;
60
61 struct hpsb_packet *async_queue;
62 spinlock_t async_queue_lock;
63
64 unsigned long NumInterrupts, NumBusResets;
65 unsigned long TxPackets, RxPackets;
66 unsigned long TxErrors, RxErrors;
67 unsigned long TxRdy, ATError, HdrErr, TCodeErr, SendRej;
68
69 };
70
71
72 /*
73 * Register read and write helper functions.
74 */
75 inline static void reg_write(const struct aic5800 *aic, int offset, u32 data)
76 {
77 writel(data, aic->registers + offset);
78 }
79
80 inline static u32 reg_read(const struct aic5800 *aic, int offset)
81 {
82 return readl(aic->registers + offset);
83 }
84
85 inline static void reg_set_bits(const struct aic5800 *aic, int offset,
86 u32 mask)
87 {
88 reg_write(aic, offset, (reg_read(aic, offset) | mask));
89 }
90
91 inline static void reg_clear_bits(const struct aic5800 *aic, int offset,
92 u32 mask)
93 {
94 reg_write(aic, offset, (reg_read(aic, offset) & ~mask));
95 }
96
97
98 /* AIC-5800 Registers */
99
100 #define AT_ChannelControl 0x0
101 #define AT_ChannelStatus 0x4
102 #define AT_CommandPtr 0xC
103 #define AT_InterruptSelect 0x10
104 #define AT_BranchSelect 0x14
105 #define AT_WaitSelect 0x18
106
107 /* Asynchronous receive */
108 #define AR_ChannelControl 0x20
109 #define AR_ChannelStatus 0x24
110 #define AR_CommandPtr 0x2C
111
112 /* ITA */
113 #define ITA_ChannelControl 0x40
114 #define ITA_ChannelStatus 0x44
115 #define ITA_CommandPtr 0x4C
116
117 /* ITB */
118 #define ITB_ChannelControl 0x60
119 #define ITB_ChannelStatus 0x64
120 #define ITB_CommandPtr 0x6C
121
122 /* IRA */
123 #define IRA_ChannelControl 0x80
124 #define IRA_ChannelStatus 0x84
125 #define IRA_CommandPtr 0x8C
126
127 /* IRB */
128 #define IRB_ChannelControl 0xA0
129 #define IRB_ChannelStatus 0xA4
130 #define IRB_CommandPtr 0xAC
131
132 /* miscellaneous */
133 #define misc_Version 0x100
134 #define misc_Control 0x104
135 #define misc_NodeID 0x108
136 #define misc_Reset 0x10C
137 #define misc_PacketControl 0x110
138 #define misc_Diagnostic 0x114
139 #define misc_PhyControl 0x118
140 #define misc_ATRetries 0x11C
141 #define misc_SSNinterface 0x120
142 #define misc_CycleTimer 0x124
143
144 /* ITA */
145 #define ITA_EventCycle 0x130
146 #define ITA_Configuration 0x134
147 #define ITA_Bandwidth 0x138
148
149 /* ITB */
150 #define ITB_EventCycle 0x140
151 #define ITB_Configuration 0x144
152 #define ITB_Bandwidth 0x148
153
154 /* IRA */
155 #define IRA_EventCycle 0x150
156 #define IRA_Configuration 0x154
157
158 /* IRB */
159 #define IRB_EventCycle 0x160
160 #define IRB_Configuration 0x164
161
162 /* RSU */
163 #define RSU_Enable 0x170
164 #define RSU_Interrupt 0x174
165 #define RSU_TablePtr 0x178
166 #define RSU_InterruptSet 0x17C
167
168 /* misc */
169 #define misc_InterruptEvents 0x180
170 #define misc_InterruptMask 0x184
171 #define misc_InterruptClear 0x188
172 #define misc_CardBusEvent 0x1E0
173 #define misc_CardBusMask 0x1E4
174 #define misc_CardBusState 0x1E8
175 #define misc_CardBusForce 0x1EC
176 #define misc_SEEPCTL 0x1F0
177
178 /* Interrupts */
179 #define INT_DmaAT 1
180 #define INT_DmaAR (1<<1)
181 #define INT_DmaITA (1<<2)
182 #define INT_DmaITB (1<<3)
183 #define INT_DmaIRA (1<<4)
184 #define INT_DmaIRB (1<<5)
185 #define INT_PERResponse (1<<7)
186 #define INT_CycleEventITA (1<<8)
187 #define INT_CycleEventITB (1<<9)
188 #define INT_CycleEventIRA (1<<10)
189 #define INT_CycleEventIRB (1<<11)
190 #define INT_BusReset (1<<12)
191 #define INT_CmdReset (1<<13)
192 #define INT_PhyInt (1<<14)
193 #define INT_RcvData (1<<15)
194 #define INT_TxRdy (1<<16)
195 #define INT_CycleStart (1<<17)
196 #define INT_CycleSeconds (1<<18)
197 #define INT_CycleLost (1<<19)
198 #define INT_ATError (1<<20)
199 #define INT_SendRej (1<<21)
200 #define INT_HdrErr (1<<22)
201 #define INT_TCodeErr (1<<23)
202 #define INT_PRQUxferErr (1<<24)
203 #define INT_PWQUxferErr (1<<25)
204 #define INT_RSUxferErr (1<<26)
205 #define INT_RSDone (1<<27)
206 #define INT_PSOutOfRetries (1<<28)
207 #define INT_cycleTooLong (1<<29)
208
209 /* DB DMA constants */
210 #define DMA_CMD_OUTPUTMORE 0
211 #define DMA_CMD_OUTPUTLAST 0x10000000
212 #define DMA_CMD_INPUTMORE 0x20000000
213 #define DMA_CMD_INPUTLAST 0x30000000
214 #define DMA_CMD_STOREQUAD 0x40000000
215 #define DMA_CMD_LOADQUAD 0x50000000
216 #define DMA_CMD_NOP 0x60000000
217 #define DMA_CMD_STOP 0x70000000
218
219 #define DMA_KEY_STREAM0 0
220 #define DMA_KEY_STREAM1 (1<<24)
221 #define DMA_KEY_STREAM2 (2<<24)
222 #define DMA_KEY_STREAM3 (3<<24)
223 #define DMA_KEY_REGS (5<<24)
224 #define DMA_KEY_SYSTEM (6<<24)
225 #define DMA_KEY_DEVICE (7<<24)
226
227 #define DMA_INTR_NEVER 0
228 #define DMA_INTR_TRUE (1<<20)
229 #define DMA_INTR_FALSE (2<<20)
230 #define DMA_INTR_ALWAYS (3<<20)
231 #define DMA_WAIT_NEVER 0
232 #define DMA_WAIT_TRUE (1<<16)
233 #define DMA_WAIT_FALSE (2<<16)
234 #define DMA_WAIT_ALWAYS (3<<16)
235 #define DMA_BRANCH_NEVER 0
236 #define DMA_BRANCH_TRUE (1<<18)
237 #define DMA_BRANCH_FALSE (2<<18)
238 #define DMA_BRANCH_ALWAYS (3<<18)
239
240 #define DMA_SPEED_100 0
241 #define DMA_SPEED_200 (1<<16)
242 #define DMA_SPEED_400 (2<<16)
243
244 /* PHY access */
245 #define LINK_PHY_READ (1<<15)
246 #define LINK_PHY_WRITE (1<<14)
247 #define LINK_PHY_ADDR(addr) (addr<<8)
248 #define LINK_PHY_WDATA(data) (data)
249 #define LINK_PHY_RADDR(addr) (addr<<24)
250
251 quadlet_t aic5800_csr_rom[] = {
252 /* bus info block */
253 0x041ffb82, // length of bus info block, CRC
254 0x31333934, // 1394 designator
255 0xf005a000, // various capabilites
256 0x0000d189, // node_vendor_id, chip_id_hi
257 0x401010fc, // chip_id_lo
258 /* root directory */
259 0x00040e54, // length of root directory, CRC
260 0x030000d1, // module_vendor_id
261 0x0c008000, // various capabilities
262 0x8d000006, // offset of node unique id leaf
263 0xd1000001, // offset of unit directory
264 /* unit directory */
265 0x0003e60d, // length of unit directory, CRC
266 0x12000000, // unit_spec_id
267 0x13000000, // unit_sw_version
268 0xd4000004, // offset of unit dependent directory
269 /* node unique id leaf */
270 0x00026ba7, // length of leaf, CRC
271 0x0000d189, // node_vendor_id, chip_id_hi
272 0x401010fc, // chip_id_lo
273 /* unit dependent directory */
274 0x0002ae47, // length of directory, CRC
275 0x81000002, // offset of vendor name leaf
276 0x82000006, // offset of model name leaf
277 /* vendor name leaf */
278 0x000486a3, // length of leaf, CRC
279 0x00000000,
280 0x00000000,
281 0x41444150, // ADAP
282 0x54454300, // TEC
283 /* model name leaf */
284 0x0004f420, // length of leaf, CRC
285 0x00000000,
286 0x00000000,
287 0x4148412d, // AHA-
288 0x38393430 // 8940
289 };
290
291 #endif
292
293
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.