1 /*
2 * ohci1394.h - driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Gord Peters <GordPeters@smarttech.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #ifndef _OHCI1394_H
22 #define _OHCI1394_H
23
24 #include "ieee1394_types.h"
25
26 #define IEEE1394_USE_BOTTOM_HALVES 1
27
28 #define OHCI1394_DRIVER_NAME "ohci1394"
29
30 #define USE_DEVICE 0
31
32 #if USE_DEVICE
33
34 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV22
35 #define PCI_DEVICE_ID_TI_OHCI1394_LV22 0x8009
36 #endif
37
38 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV23
39 #define PCI_DEVICE_ID_TI_OHCI1394_LV23 0x8019
40 #endif
41
42 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV26
43 #define PCI_DEVICE_ID_TI_OHCI1394_LV26 0x8020
44 #endif
45
46 #ifndef PCI_DEVICE_ID_TI_OHCI1394_PCI4450
47 #define PCI_DEVICE_ID_TI_OHCI1394_PCI4450 0x8011
48 #endif
49
50 #ifndef PCI_DEVICE_ID_VIA_OHCI1394
51 #define PCI_DEVICE_ID_VIA_OHCI1394 0x3044
52 #endif
53
54 #ifndef PCI_VENDOR_ID_SONY
55 #define PCI_VENDOR_ID_SONY 0x104d
56 #endif
57
58 #ifndef PCI_DEVICE_ID_SONY_CXD3222
59 #define PCI_DEVICE_ID_SONY_CXD3222 0x8039
60 #endif
61
62 #ifndef PCI_DEVICE_ID_NEC_1394
63 #define PCI_DEVICE_ID_NEC_1394 0x00cd
64 #endif
65
66 #ifndef PCI_DEVICE_ID_NEC_UPD72862
67 #define PCI_DEVICE_ID_NEC_UPD72862 0x0063
68 #endif
69
70 #ifndef PCI_DEVICE_ID_NEC_UPD72870
71 #define PCI_DEVICE_ID_NEC_UPD72870 0x00cd
72 #endif
73
74 #ifndef PCI_DEVICE_ID_NEC_UPD72871
75 #define PCI_DEVICE_ID_NEC_UPD72871 0x00ce
76 #endif
77
78 #ifndef PCI_DEVICE_ID_APPLE_UNI_N_FW
79 #define PCI_DEVICE_ID_APPLE_UNI_N_FW 0x0018
80 #endif
81
82 #ifndef PCI_DEVICE_ID_ALI_OHCI1394_M5251
83 #define PCI_DEVICE_ID_ALI_OHCI1394_M5251 0x5251
84 #endif
85
86 #ifndef PCI_VENDOR_ID_LUCENT
87 #define PCI_VENDOR_ID_LUCENT 0x11c1
88 #endif
89
90 #ifndef PCI_DEVICE_ID_LUCENT_FW323
91 #define PCI_DEVICE_ID_LUCENT_FW323 0x5811
92 #endif
93
94 #endif /* USE_DEVICE */
95
96
97 #define MAX_OHCI1394_CARDS 4
98
99 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
100 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
101 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
102 #define OHCI1394_MAX_SELF_ID_ERRORS 16
103
104 #define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */
105 #define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */
106 #define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
107
108 #define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */
109 #define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */
110 #define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
111
112 #define IR_NUM_DESC 16 /* number of IR descriptors */
113 #define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */
114 #define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */
115
116 #define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */
117 #define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */
118
119 struct dma_cmd {
120 u32 control;
121 u32 address;
122 u32 branchAddress;
123 u32 status;
124 };
125
126 /*
127 * FIXME:
128 * It is important that a single at_dma_prg does not cross a page boundary
129 * The proper way to do it would be to do the check dynamically as the
130 * programs are inserted into the AT fifo.
131 */
132 struct at_dma_prg {
133 struct dma_cmd begin;
134 quadlet_t data[4];
135 struct dma_cmd end;
136 quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
137 };
138
139 /* DMA receive context */
140 struct dma_rcv_ctx {
141 void *ohci;
142 int ctx;
143 unsigned int num_desc;
144 unsigned int buf_size;
145 unsigned int split_buf_size;
146
147 /* dma block descriptors */
148 struct dma_cmd **prg_cpu;
149 dma_addr_t *prg_bus;
150
151 /* dma buffers */
152 quadlet_t **buf_cpu;
153 dma_addr_t *buf_bus;
154
155 unsigned int buf_ind;
156 unsigned int buf_offset;
157 quadlet_t *spb;
158 spinlock_t lock;
159 struct tq_struct task;
160 int ctrlClear;
161 int ctrlSet;
162 int cmdPtr;
163 };
164
165 /* DMA transmit context */
166 struct dma_trm_ctx {
167 void *ohci;
168 int ctx;
169 unsigned int num_desc;
170
171 /* dma block descriptors */
172 struct at_dma_prg **prg_cpu;
173 dma_addr_t *prg_bus;
174
175 unsigned int prg_ind;
176 unsigned int sent_ind;
177 int free_prgs;
178 quadlet_t *branchAddrPtr;
179
180 /* list of packets inserted in the AT FIFO */
181 struct hpsb_packet *fifo_first;
182 struct hpsb_packet *fifo_last;
183
184 /* list of pending packets to be inserted in the AT FIFO */
185 struct hpsb_packet *pending_first;
186 struct hpsb_packet *pending_last;
187
188 spinlock_t lock;
189 struct tq_struct task;
190 int ctrlClear;
191 int ctrlSet;
192 int cmdPtr;
193 };
194
195 /* video device template */
196 struct video_template {
197 void (*irq_handler) (int card, quadlet_t isoRecvEvent,
198 quadlet_t isoXmitEvent);
199 };
200
201
202 struct ti_ohci {
203 int id; /* sequential card number */
204
205 struct pci_dev *dev;
206
207 u32 state;
208
209 /* remapped memory spaces */
210 void *registers;
211
212 /* dma buffer for self-id packets */
213 quadlet_t *selfid_buf_cpu;
214 dma_addr_t selfid_buf_bus;
215
216 /* buffer for csr config rom */
217 quadlet_t *csr_config_rom_cpu;
218 dma_addr_t csr_config_rom_bus;
219
220 unsigned int max_packet_size;
221
222 /* async receive */
223 struct dma_rcv_ctx *ar_resp_context;
224 struct dma_rcv_ctx *ar_req_context;
225
226 /* async transmit */
227 struct dma_trm_ctx *at_resp_context;
228 struct dma_trm_ctx *at_req_context;
229
230 /* iso receive */
231 struct dma_rcv_ctx *ir_context;
232 spinlock_t IR_channel_lock;
233 int nb_iso_rcv_ctx;
234
235 /* iso transmit */
236 int nb_iso_xmit_ctx;
237
238 u64 ISO_channel_usage;
239
240 /* IEEE-1394 part follows */
241 struct hpsb_host *host;
242
243 int phyid, isroot;
244
245 spinlock_t phy_reg_lock;
246
247 int self_id_errors;
248 int NumBusResets;
249
250 /* video device */
251 struct video_template *video_tmpl;
252 };
253
254 inline static int cross_bound(unsigned long addr, unsigned int size)
255 {
256 int cross=0;
257 if (size>PAGE_SIZE) {
258 cross = size/PAGE_SIZE;
259 size -= cross*PAGE_SIZE;
260 }
261 if ((PAGE_SIZE-addr%PAGE_SIZE)<size)
262 cross++;
263 return cross;
264 }
265
266 /*
267 * Register read and write helper functions.
268 */
269 inline static void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
270 {
271 writel(data, ohci->registers + offset);
272 }
273
274 inline static u32 reg_read(const struct ti_ohci *ohci, int offset)
275 {
276 return readl(ohci->registers + offset);
277 }
278
279 /* This structure is not properly initialized ... it is taken from
280 the lynx_csr_rom written by Andreas ... Some fields in the root
281 directory and the module dependent info needs to be modified
282 I do not have the proper doc */
283 quadlet_t ohci_csr_rom[] = {
284 /* bus info block */
285 0x04040000, /* info/CRC length, CRC */
286 0x31333934, /* 1394 magic number */
287 0xf07da002, /* cyc_clk_acc = 125us, max_rec = 1024 */
288 0x00000000, /* vendor ID, chip ID high (written from card info) */
289 0x00000000, /* chip ID low (written from card info) */
290 /* root directory - FIXME */
291 0x00090000, /* CRC length, CRC */
292 0x03080028, /* vendor ID (Texas Instr.) */
293 0x81000009, /* offset to textual ID */
294 0x0c000200, /* node capabilities */
295 0x8d00000e, /* offset to unique ID */
296 0xc7000010, /* offset to module independent info */
297 0x04000000, /* module hardware version */
298 0x81000026, /* offset to textual ID */
299 0x09000000, /* node hardware version */
300 0x81000026, /* offset to textual ID */
301 /* module vendor ID textual */
302 0x00080000, /* CRC length, CRC */
303 0x00000000,
304 0x00000000,
305 0x54455841, /* "Texas Instruments" */
306 0x5320494e,
307 0x53545255,
308 0x4d454e54,
309 0x53000000,
310 /* node unique ID leaf */
311 0x00020000, /* CRC length, CRC */
312 0x08002856, /* vendor ID, chip ID high */
313 0x0000083E, /* chip ID low */
314 /* module dependent info - FIXME */
315 0x00060000, /* CRC length, CRC */
316 0xb8000006, /* ??? offset to module textual ID */
317 0x81000004, /* ??? textual descriptor */
318 0x00000000, /* SRAM size */
319 0x00000000, /* AUXRAM size */
320 0x00000000, /* AUX device */
321 /* module textual ID */
322 0x00050000, /* CRC length, CRC */
323 0x00000000,
324 0x00000000,
325 0x54534231, /* "TSB12LV22" */
326 0x324c5632,
327 0x32000000,
328 /* part number */
329 0x00060000, /* CRC length, CRC */
330 0x00000000,
331 0x00000000,
332 0x39383036, /* "9806000-0001" */
333 0x3030342d,
334 0x30303431,
335 0x20000001,
336 /* module hardware version textual */
337 0x00050000, /* CRC length, CRC */
338 0x00000000,
339 0x00000000,
340 0x5453424b, /* "TSBKOHCI403" */
341 0x4f484349,
342 0x34303300,
343 /* node hardware version textual */
344 0x00050000, /* CRC length, CRC */
345 0x00000000,
346 0x00000000,
347 0x54534234, /* "TSB41LV03" */
348 0x314c5630,
349 0x33000000
350 };
351
352
353 /* 2 KiloBytes of register space */
354 #define OHCI1394_REGISTER_SIZE 0x800
355
356 /* register map */
357 #define OHCI1394_Version 0x000
358 #define OHCI1394_GUID_ROM 0x004
359 #define OHCI1394_ATRetries 0x008
360 #define OHCI1394_CSRData 0x00C
361 #define OHCI1394_CSRCompareData 0x010
362 #define OHCI1394_CSRControl 0x014
363 #define OHCI1394_ConfigROMhdr 0x018
364 #define OHCI1394_BusID 0x01C
365 #define OHCI1394_BusOptions 0x020
366 #define OHCI1394_GUIDHi 0x024
367 #define OHCI1394_GUIDLo 0x028
368 #define OHCI1394_ConfigROMmap 0x034
369 #define OHCI1394_PostedWriteAddressLo 0x038
370 #define OHCI1394_PostedWriteAddressHi 0x03C
371 #define OHCI1394_VendorID 0x040
372 #define OHCI1394_HCControlSet 0x050
373 #define OHCI1394_HCControlClear 0x054
374 #define OHCI1394_SelfIDBuffer 0x064
375 #define OHCI1394_SelfIDCount 0x068
376 #define OHCI1394_IRMultiChanMaskHiSet 0x070
377 #define OHCI1394_IRMultiChanMaskHiClear 0x074
378 #define OHCI1394_IRMultiChanMaskLoSet 0x078
379 #define OHCI1394_IRMultiChanMaskLoClear 0x07C
380 #define OHCI1394_IntEventSet 0x080
381 #define OHCI1394_IntEventClear 0x084
382 #define OHCI1394_IntMaskSet 0x088
383 #define OHCI1394_IntMaskClear 0x08C
384 #define OHCI1394_IsoXmitIntEventSet 0x090
385 #define OHCI1394_IsoXmitIntEventClear 0x094
386 #define OHCI1394_IsoXmitIntMaskSet 0x098
387 #define OHCI1394_IsoXmitIntMaskClear 0x09C
388 #define OHCI1394_IsoRecvIntEventSet 0x0A0
389 #define OHCI1394_IsoRecvIntEventClear 0x0A4
390 #define OHCI1394_IsoRecvIntMaskSet 0x0A8
391 #define OHCI1394_IsoRecvIntMaskClear 0x0AC
392 #define OHCI1394_FairnessControl 0x0DC
393 #define OHCI1394_LinkControlSet 0x0E0
394 #define OHCI1394_LinkControlClear 0x0E4
395 #define OHCI1394_NodeID 0x0E8
396 #define OHCI1394_PhyControl 0x0EC
397 #define OHCI1394_IsochronousCycleTimer 0x0F0
398 #define OHCI1394_AsReqFilterHiSet 0x100
399 #define OHCI1394_AsReqFilterHiClear 0x104
400 #define OHCI1394_AsReqFilterLoSet 0x108
401 #define OHCI1394_AsReqFilterLoClear 0x10C
402 #define OHCI1394_PhyReqFilterHiSet 0x110
403 #define OHCI1394_PhyReqFilterHiClear 0x114
404 #define OHCI1394_PhyReqFilterLoSet 0x118
405 #define OHCI1394_PhyReqFilterLoClear 0x11C
406 #define OHCI1394_PhyUpperBound 0x120
407 #define OHCI1394_AsReqTrContextControlSet 0x180
408 #define OHCI1394_AsReqTrContextControlClear 0x184
409 #define OHCI1394_AsReqTrCommandPtr 0x18C
410 #define OHCI1394_AsRspTrContextControlSet 0x1A0
411 #define OHCI1394_AsRspTrContextControlClear 0x1A4
412 #define OHCI1394_AsRspTrCommandPtr 0x1AC
413 #define OHCI1394_AsReqRcvContextControlSet 0x1C0
414 #define OHCI1394_AsReqRcvContextControlClear 0x1C4
415 #define OHCI1394_AsReqRcvCommandPtr 0x1CC
416 #define OHCI1394_AsRspRcvContextControlSet 0x1E0
417 #define OHCI1394_AsRspRcvContextControlClear 0x1E4
418 #define OHCI1394_AsRspRcvCommandPtr 0x1EC
419
420 /* Isochronous transmit registers */
421 /* Add (32 * n) for context n */
422 #define OHCI1394_IsoXmitContextControlSet 0x200
423 #define OHCI1394_IsoXmitContextControlClear 0x204
424 #define OHCI1394_IsoXmitCommandPtr 0x20C
425
426 /* Isochronous receive registers */
427 /* Add (32 * n) for context n */
428 #define OHCI1394_IsoRcvContextControlSet 0x400
429 #define OHCI1394_IsoRcvContextControlClear 0x404
430 #define OHCI1394_IsoRcvCommandPtr 0x40C
431 #define OHCI1394_IsoRcvContextMatch 0x410
432
433 /* Interrupts Mask/Events */
434
435 #define OHCI1394_reqTxComplete 0x00000001
436 #define OHCI1394_respTxComplete 0x00000002
437 #define OHCI1394_ARRQ 0x00000004
438 #define OHCI1394_ARRS 0x00000008
439 #define OHCI1394_RQPkt 0x00000010
440 #define OHCI1394_RSPkt 0x00000020
441 #define OHCI1394_isochTx 0x00000040
442 #define OHCI1394_isochRx 0x00000080
443 #define OHCI1394_postedWriteErr 0x00000100
444 #define OHCI1394_lockRespErr 0x00000200
445 #define OHCI1394_selfIDComplete 0x00010000
446 #define OHCI1394_busReset 0x00020000
447 #define OHCI1394_phy 0x00080000
448 #define OHCI1394_cycleSynch 0x00100000
449 #define OHCI1394_cycle64Seconds 0x00200000
450 #define OHCI1394_cycleLost 0x00400000
451 #define OHCI1394_cycleInconsistent 0x00800000
452 #define OHCI1394_unrecoverableError 0x01000000
453 #define OHCI1394_cycleTooLong 0x02000000
454 #define OHCI1394_phyRegRcvd 0x04000000
455 #define OHCI1394_masterIntEnable 0x80000000
456
457 #define OUTPUT_MORE 0x00000000
458 #define OUTPUT_MORE_IMMEDIATE 0x02000000
459 #define OUTPUT_LAST 0x103c0000
460 #define OUTPUT_LAST_IMMEDIATE 0x123c0000
461
462 #define DMA_SPEED_100 0x0
463 #define DMA_SPEED_200 0x1
464 #define DMA_SPEED_400 0x2
465
466 #define OHCI1394_TCODE_PHY 0xE
467
468 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg);
469 struct ti_ohci *ohci1394_get_struct(int card_num);
470 int ohci1394_register_video(struct ti_ohci *ohci,
471 struct video_template *tmpl);
472 void ohci1394_unregister_video(struct ti_ohci *ohci,
473 struct video_template *tmpl);
474
475 #endif
476
477
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