1 /*
2 * macserial.h: Definitions for the Macintosh Z8530 serial driver.
3 *
4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
5 *
6 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 */
9 #ifndef _MACSERIAL_H
10 #define _MACSERIAL_H
11
12 #define NUM_ZSREGS 16
13
14 struct serial_struct {
15 int type;
16 int line;
17 int port;
18 int irq;
19 int flags;
20 int xmit_fifo_size;
21 int custom_divisor;
22 int baud_base;
23 unsigned short close_delay;
24 char reserved_char[2];
25 int hub6;
26 unsigned short closing_wait; /* time to wait before closing */
27 unsigned short closing_wait2; /* no longer used... */
28 int reserved[4];
29 };
30
31 /*
32 * For the close wait times, 0 means wait forever for serial port to
33 * flush its output. 65535 means don't wait at all.
34 */
35 #define ZILOG_CLOSING_WAIT_INF 0
36 #define ZILOG_CLOSING_WAIT_NONE 65535
37
38 /*
39 * Definitions for ZILOG_struct (and serial_struct) flags field
40 */
41 #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes
42 * on the callout port */
43 #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */
44 #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */
45 #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
46
47 #define ZILOG_SPD_MASK 0x0030
48 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */
49
50 #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */
51 #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */
52
53 #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */
54 #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */
55 #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
56 #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */
57 #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */
58
59 #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */
60 #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged
61 * users can set or reset */
62
63 /* Internal flags used only by kernel/chr_drv/serial.c */
64 #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */
65 #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */
66 #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
67 #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
68 #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */
69 #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */
70 #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */
71 #define ZILOG_SLEEPING 0x01000000 /* have shut it down for sleep */
72
73 /* Software state per channel */
74
75 #ifdef __KERNEL__
76 /*
77 * This is our internal structure for each serial port's state.
78 *
79 * Many fields are paralleled by the structure used by the serial_struct
80 * structure.
81 *
82 * For definitions of the flags field, see tty.h
83 */
84
85 struct mac_serial;
86
87 struct mac_zschannel {
88 volatile unsigned char* control;
89 volatile unsigned char* data;
90 spinlock_t lock;
91 /* Used for debugging */
92 struct mac_serial* parent;
93 };
94
95 struct mac_dma {
96 volatile struct dbdma_regs dma;
97 volatile unsigned short res_count;
98 volatile unsigned short command;
99 volatile unsigned int buf_addr;
100 };
101
102 struct mac_serial {
103 struct mac_serial *zs_next; /* For IRQ servicing chain */
104 struct mac_zschannel *zs_channel; /* Channel registers */
105 struct mac_zschannel *zs_chan_a; /* A side registers */
106 unsigned char read_reg_zero;
107 struct device_node* dev_node;
108
109 char soft_carrier; /* Use soft carrier on this channel */
110 char break_abort; /* Is serial console in, so process brk/abrt */
111 char kgdb_channel; /* Kgdb is running on this channel */
112 char is_cons; /* Is this our console. */
113 char is_cobalt_modem; /* is a gatwick-based cobalt modem */
114 char is_irda; /* is connected to an IrDA codec */
115 unsigned char tx_active; /* character is being xmitted */
116 unsigned char tx_stopped; /* output is suspended */
117
118 /* We need to know the current clock divisor
119 * to read the bps rate the chip has currently
120 * loaded.
121 */
122 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */
123 int zs_baud;
124
125 /* Current write register values */
126 unsigned char curregs[NUM_ZSREGS];
127
128 /* Values we need to set next opportunity */
129 unsigned char pendregs[NUM_ZSREGS];
130
131 char change_needed;
132
133 int magic;
134 int baud_base;
135 int port;
136 int irq;
137 int flags; /* defined in tty.h */
138 int type; /* UART type */
139 struct tty_struct *tty;
140 int read_status_mask;
141 int ignore_status_mask;
142 int timeout;
143 int xmit_fifo_size;
144 int custom_divisor;
145 int x_char; /* xon/xoff character */
146 int close_delay;
147 unsigned short closing_wait;
148 unsigned short closing_wait2;
149 unsigned long event;
150 unsigned long last_active;
151 int line;
152 int count; /* # of fd on device */
153 int blocked_open; /* # of blocked opens */
154 long session; /* Session of opening process */
155 long pgrp; /* pgrp of opening process */
156 unsigned char *xmit_buf;
157 int xmit_head;
158 int xmit_tail;
159 int xmit_cnt;
160 struct tq_struct tqueue;
161 struct tq_struct tqueue_hangup;
162 struct termios normal_termios;
163 struct termios callout_termios;
164 wait_queue_head_t open_wait;
165 wait_queue_head_t close_wait;
166
167 volatile struct dbdma_regs *tx_dma;
168 int tx_dma_irq;
169 volatile struct dbdma_cmd *tx_cmds;
170 volatile struct mac_dma *rx;
171 int rx_dma_irq;
172 volatile struct dbdma_cmd **rx_cmds;
173 unsigned char **rx_char_buf;
174 unsigned char **rx_flag_buf;
175 #define RX_BUF_SIZE 256
176 int rx_nbuf;
177 int rx_done_bytes;
178 int rx_ubuf;
179 int rx_fbuf;
180 #define RX_NO_FBUF (-1)
181 int rx_cbuf;
182 spinlock_t rx_dma_lock;
183 int has_dma;
184 int dma_initted;
185 void *dma_priv;
186 struct timer_list poll_dma_timer;
187 #define RX_DMA_TIMER (jiffies + 10*HZ/1000)
188 };
189
190
191 #define SERIAL_MAGIC 0x5301
192
193 /*
194 * The size of the serial xmit buffer is 1 page, or 4096 bytes
195 */
196 #define SERIAL_XMIT_SIZE 4096
197
198 /*
199 * Events are used to schedule things to happen at timer-interrupt
200 * time, instead of at rs interrupt time.
201 */
202 #define RS_EVENT_WRITE_WAKEUP 0
203
204 #endif /* __KERNEL__ */
205
206 /* Conversion routines to/from brg time constants from/to bits
207 * per second.
208 */
209 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
210 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
211
212 /* The Zilog register set */
213
214 #define FLAG 0x7e
215
216 /* Write Register 0 */
217 #define R0 0 /* Register selects */
218 #define R1 1
219 #define R2 2
220 #define R3 3
221 #define R4 4
222 #define R5 5
223 #define R6 6
224 #define R7 7
225 #define R8 8
226 #define R9 9
227 #define R10 10
228 #define R11 11
229 #define R12 12
230 #define R13 13
231 #define R14 14
232 #define R15 15
233
234 #define NULLCODE 0 /* Null Code */
235 #define POINT_HIGH 0x8 /* Select upper half of registers */
236 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
237 #define SEND_ABORT 0x18 /* HDLC Abort */
238 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
239 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
240 #define ERR_RES 0x30 /* Error Reset */
241 #define RES_H_IUS 0x38 /* Reset highest IUS */
242
243 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
244 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
245 #define RES_EOM_L 0xC0 /* Reset EOM latch */
246
247 /* Write Register 1 */
248
249 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
250 #define TxINT_ENAB 0x2 /* Tx Int Enable */
251 #define PAR_SPEC 0x4 /* Parity is special condition */
252
253 #define RxINT_DISAB 0 /* Rx Int Disable */
254 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
255 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
256 #define INT_ERR_Rx 0x18 /* Int on error only */
257
258 #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */
259 #define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */
260 #define WT_RDY_ENAB 0x80 /* Enable W/Req pin */
261
262 /* Write Register #2 (Interrupt Vector) */
263
264 /* Write Register 3 */
265
266 #define RxENABLE 0x1 /* Rx Enable */
267 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
268 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
269 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
270 #define ENT_HM 0x10 /* Enter Hunt Mode */
271 #define AUTO_ENAB 0x20 /* Auto Enables */
272 #define Rx5 0x0 /* Rx 5 Bits/Character */
273 #define Rx7 0x40 /* Rx 7 Bits/Character */
274 #define Rx6 0x80 /* Rx 6 Bits/Character */
275 #define Rx8 0xc0 /* Rx 8 Bits/Character */
276 #define RxNBITS_MASK 0xc0
277
278 /* Write Register 4 */
279
280 #define PAR_ENA 0x1 /* Parity Enable */
281 #define PAR_EVEN 0x2 /* Parity Even/Odd* */
282
283 #define SYNC_ENAB 0 /* Sync Modes Enable */
284 #define SB1 0x4 /* 1 stop bit/char */
285 #define SB15 0x8 /* 1.5 stop bits/char */
286 #define SB2 0xc /* 2 stop bits/char */
287 #define SB_MASK 0xc
288
289 #define MONSYNC 0 /* 8 Bit Sync character */
290 #define BISYNC 0x10 /* 16 bit sync character */
291 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
292 #define EXTSYNC 0x30 /* External Sync Mode */
293
294 #define X1CLK 0x0 /* x1 clock mode */
295 #define X16CLK 0x40 /* x16 clock mode */
296 #define X32CLK 0x80 /* x32 clock mode */
297 #define X64CLK 0xC0 /* x64 clock mode */
298 #define XCLK_MASK 0xC0
299
300 /* Write Register 5 */
301
302 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
303 #define RTS 0x2 /* RTS */
304 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
305 #define TxENAB 0x8 /* Tx Enable */
306 #define SND_BRK 0x10 /* Send Break */
307 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
308 #define Tx7 0x20 /* Tx 7 bits/character */
309 #define Tx6 0x40 /* Tx 6 bits/character */
310 #define Tx8 0x60 /* Tx 8 bits/character */
311 #define TxNBITS_MASK 0x60
312 #define DTR 0x80 /* DTR */
313
314 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
315
316 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
317
318 /* Write Register 7' (Some enhanced feature control) */
319 #define ENEXREAD 0x40 /* Enable read of some write registers */
320
321 /* Write Register 8 (transmit buffer) */
322
323 /* Write Register 9 (Master interrupt control) */
324 #define VIS 1 /* Vector Includes Status */
325 #define NV 2 /* No Vector */
326 #define DLC 4 /* Disable Lower Chain */
327 #define MIE 8 /* Master Interrupt Enable */
328 #define STATHI 0x10 /* Status high */
329 #define NORESET 0 /* No reset on write to R9 */
330 #define CHRB 0x40 /* Reset channel B */
331 #define CHRA 0x80 /* Reset channel A */
332 #define FHWRES 0xc0 /* Force hardware reset */
333
334 /* Write Register 10 (misc control bits) */
335 #define BIT6 1 /* 6 bit/8bit sync */
336 #define LOOPMODE 2 /* SDLC Loop mode */
337 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
338 #define MARKIDLE 8 /* Mark/flag on idle */
339 #define GAOP 0x10 /* Go active on poll */
340 #define NRZ 0 /* NRZ mode */
341 #define NRZI 0x20 /* NRZI mode */
342 #define FM1 0x40 /* FM1 (transition = 1) */
343 #define FM0 0x60 /* FM0 (transition = 0) */
344 #define CRCPS 0x80 /* CRC Preset I/O */
345
346 /* Write Register 11 (Clock Mode control) */
347 #define TRxCXT 0 /* TRxC = Xtal output */
348 #define TRxCTC 1 /* TRxC = Transmit clock */
349 #define TRxCBR 2 /* TRxC = BR Generator Output */
350 #define TRxCDP 3 /* TRxC = DPLL output */
351 #define TRxCOI 4 /* TRxC O/I */
352 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
353 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
354 #define TCBR 0x10 /* Transmit clock = BR Generator output */
355 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
356 #define RCRTxCP 0 /* Receive clock = RTxC pin */
357 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
358 #define RCBR 0x40 /* Receive clock = BR Generator output */
359 #define RCDPLL 0x60 /* Receive clock = DPLL output */
360 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */
361
362 /* Write Register 12 (lower byte of baud rate generator time constant) */
363
364 /* Write Register 13 (upper byte of baud rate generator time constant) */
365
366 /* Write Register 14 (Misc control bits) */
367 #define BRENABL 1 /* Baud rate generator enable */
368 #define BRSRC 2 /* Baud rate generator source */
369 #define DTRREQ 4 /* DTR/Request function */
370 #define AUTOECHO 8 /* Auto Echo */
371 #define LOOPBAK 0x10 /* Local loopback */
372 #define SEARCH 0x20 /* Enter search mode */
373 #define RMC 0x40 /* Reset missing clock */
374 #define DISDPLL 0x60 /* Disable DPLL */
375 #define SSBR 0x80 /* Set DPLL source = BR generator */
376 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */
377 #define SFMM 0xc0 /* Set FM mode */
378 #define SNRZI 0xe0 /* Set NRZI mode */
379
380 /* Write Register 15 (external/status interrupt control) */
381 #define EN85C30 1 /* Enable some 85c30-enhanced registers */
382 #define ZCIE 2 /* Zero count IE */
383 #define ENSTFIFO 4 /* Enable status FIFO (SDLC) */
384 #define DCDIE 8 /* DCD IE */
385 #define SYNCIE 0x10 /* Sync/hunt IE */
386 #define CTSIE 0x20 /* CTS IE */
387 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
388 #define BRKIE 0x80 /* Break/Abort IE */
389
390
391 /* Read Register 0 */
392 #define Rx_CH_AV 0x1 /* Rx Character Available */
393 #define ZCOUNT 0x2 /* Zero count */
394 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
395 #define DCD 0x8 /* DCD */
396 #define SYNC_HUNT 0x10 /* Sync/hunt */
397 #define CTS 0x20 /* CTS */
398 #define TxEOM 0x40 /* Tx underrun */
399 #define BRK_ABRT 0x80 /* Break/Abort */
400
401 /* Read Register 1 */
402 #define ALL_SNT 0x1 /* All sent */
403 /* Residue Data for 8 Rx bits/char programmed */
404 #define RES3 0x8 /* 0/3 */
405 #define RES4 0x4 /* 0/4 */
406 #define RES5 0xc /* 0/5 */
407 #define RES6 0x2 /* 0/6 */
408 #define RES7 0xa /* 0/7 */
409 #define RES8 0x6 /* 0/8 */
410 #define RES18 0xe /* 1/8 */
411 #define RES28 0x0 /* 2/8 */
412 /* Special Rx Condition Interrupts */
413 #define PAR_ERR 0x10 /* Parity error */
414 #define Rx_OVR 0x20 /* Rx Overrun Error */
415 #define FRM_ERR 0x40 /* CRC/Framing Error */
416 #define END_FR 0x80 /* End of Frame (SDLC) */
417
418 /* Read Register 2 (channel b only) - Interrupt vector */
419 #define CHB_Tx_EMPTY 0x00
420 #define CHB_EXT_STAT 0x02
421 #define CHB_Rx_AVAIL 0x04
422 #define CHB_SPECIAL 0x06
423 #define CHA_Tx_EMPTY 0x08
424 #define CHA_EXT_STAT 0x0a
425 #define CHA_Rx_AVAIL 0x0c
426 #define CHA_SPECIAL 0x0e
427 #define STATUS_MASK 0x06
428
429 /* Read Register 3 (interrupt pending register) ch a only */
430 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
431 #define CHBTxIP 0x2 /* Channel B Tx IP */
432 #define CHBRxIP 0x4 /* Channel B Rx IP */
433 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
434 #define CHATxIP 0x10 /* Channel A Tx IP */
435 #define CHARxIP 0x20 /* Channel A Rx IP */
436
437 /* Read Register 8 (receive data register) */
438
439 /* Read Register 10 (misc status bits) */
440 #define ONLOOP 2 /* On loop */
441 #define LOOPSEND 0x10 /* Loop sending */
442 #define CLK2MIS 0x40 /* Two clocks missing */
443 #define CLK1MIS 0x80 /* One clock missing */
444
445 /* Read Register 12 (lower byte of baud rate generator constant) */
446
447 /* Read Register 13 (upper byte of baud rate generator constant) */
448
449 /* Read Register 15 (value of WR 15) */
450
451 /* Misc macros */
452 #define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES))
453 #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \
454 garbage = read_zsdata(channel); \
455 garbage = read_zsdata(channel); \
456 garbage = read_zsdata(channel); \
457 } while(0)
458
459 #endif /* !(_MACSERIAL_H) */
460
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