1 /* Generic NS8390 register definitions. */
2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
3 under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
4 Some of these names and comments originated from the Crynwr
5 packet drivers, which are distributed under the GPL. */
6
7 #ifndef _8390_h
8 #define _8390_h
9
10 #include <linux/config.h>
11 #include <linux/if_ether.h>
12 #include <linux/ioport.h>
13 #include <linux/skbuff.h>
14
15 #define TX_2X_PAGES 12
16 #define TX_1X_PAGES 6
17
18 /* Should always use two Tx slots to get back-to-back transmits. */
19 #define EI_PINGPONG
20
21 #ifdef EI_PINGPONG
22 #define TX_PAGES TX_2X_PAGES
23 #else
24 #define TX_PAGES TX_1X_PAGES
25 #endif
26
27 #define ETHER_ADDR_LEN 6
28
29 /* The 8390 specific per-packet-header format. */
30 struct e8390_pkt_hdr {
31 unsigned char status; /* status */
32 unsigned char next; /* pointer to next packet. */
33 unsigned short count; /* header + packet length in bytes */
34 };
35
36 #ifdef notdef
37 extern int ei_debug;
38 #else
39 #define ei_debug 1
40 #endif
41
42 #ifndef HAVE_AUTOIRQ
43 /* From auto_irq.c */
44 extern void autoirq_setup(int waittime);
45 extern unsigned long autoirq_report(int waittime);
46 #endif
47
48 /* Currently unused - delete in v2.5.x after purging from drivers */
49 #define load_8390_module(driver) 0
50 #define unload_8390_module() do { } while (0)
51
52 extern int ethdev_init(struct net_device *dev);
53 extern void NS8390_init(struct net_device *dev, int startp);
54 extern int ei_open(struct net_device *dev);
55 extern int ei_close(struct net_device *dev);
56 extern void ei_interrupt(int irq, void *dev_id, struct pt_regs *regs);
57
58 /* Most of these entries should be in 'struct net_device' (or most of the
59 things in there should be here!) */
60 /* You have one of these per-board */
61 struct ei_device {
62 const char *name;
63 void (*reset_8390)(struct net_device *);
64 void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int);
65 void (*block_output)(struct net_device *, int, const unsigned char *, int);
66 void (*block_input)(struct net_device *, int, struct sk_buff *, int);
67 unsigned char mcfilter[8];
68 unsigned open:1;
69 unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */
70 unsigned bigendian:1; /* 16-bit big endian mode */
71 unsigned txing:1; /* Transmit Active */
72 unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
73 unsigned dmaing:1; /* Remote DMA Active */
74 unsigned char tx_start_page, rx_start_page, stop_page;
75 unsigned char current_page; /* Read pointer in buffer */
76 unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
77 unsigned char txqueue; /* Tx Packet buffer queue length. */
78 short tx1, tx2; /* Packet lengths for ping-pong tx. */
79 short lasttx; /* Alpha version consistency check. */
80 unsigned char reg0; /* Register '' in a WD8013 */
81 unsigned char reg5; /* Register '5' in a WD8013 */
82 unsigned char saved_irq; /* Original dev->irq value. */
83 struct net_device_stats stat; /* The new statistics table. */
84 u32 *reg_offset; /* Register mapping table */
85 spinlock_t page_lock; /* Page register locks */
86 unsigned long priv; /* Private field to store bus IDs etc. */
87 };
88
89 /* The maximum number of 8390 interrupt service routines called per IRQ. */
90 #define MAX_SERVICE 12
91
92 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
93 #define TX_TIMEOUT (20*HZ/100)
94
95 #define ei_status (*(struct ei_device *)(dev->priv))
96
97 /* Some generic ethernet register configurations. */
98 #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
99 #define E8390_RX_IRQ_MASK 0x5
100 #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
101 #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
102 #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
103 #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
104
105 /* Register accessed at EN_CMD, the 8390 base addr. */
106 #define E8390_STOP 0x01 /* Stop and reset the chip */
107 #define E8390_START 0x02 /* Start the chip, clear reset */
108 #define E8390_TRANS 0x04 /* Transmit a frame */
109 #define E8390_RREAD 0x08 /* Remote read */
110 #define E8390_RWRITE 0x10 /* Remote write */
111 #define E8390_NODMA 0x20 /* Remote DMA */
112 #define E8390_PAGE0 0x00 /* Select page chip registers */
113 #define E8390_PAGE1 0x40 /* using the two high-order bits */
114 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
115
116 /*
117 * Only generate indirect loads given a machine that needs them.
118 */
119
120 #if defined(CONFIG_MAC) || defined(CONFIG_AMIGA_PCMCIA) || \
121 defined(CONFIG_ARIADNE2) || defined(CONFIG_ARIADNE2_MODULE) || \
122 defined(CONFIG_HYDRA) || defined(CONFIG_HYDRA_MODULE)
123 #define EI_SHIFT(x) (ei_local->reg_offset[x])
124 #else
125 #define EI_SHIFT(x) (x)
126 #endif
127
128 #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
129 /* Page 0 register offsets. */
130 #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
131 #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
132 #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
133 #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
134 #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
135 #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
136 #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
137 #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
138 #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
139 #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
140 #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
141 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
142 #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
143 #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
144 #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
145 #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
146 #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
147 #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
148 #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
149 #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
150 #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
151 #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
152 #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
153 #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
154 #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
155 #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
156
157 /* Bits in EN0_ISR - Interrupt status register */
158 #define ENISR_RX 0x01 /* Receiver, no error */
159 #define ENISR_TX 0x02 /* Transmitter, no error */
160 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
161 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
162 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
163 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
164 #define ENISR_RDC 0x40 /* remote dma complete */
165 #define ENISR_RESET 0x80 /* Reset completed */
166 #define ENISR_ALL 0x3f /* Interrupts we will enable */
167
168 /* Bits in EN0_DCFG - Data config register */
169 #define ENDCFG_WTS 0x01 /* word transfer mode selection */
170 #define ENDCFG_BOS 0x02 /* byte order selection */
171
172 /* Page 1 register offsets. */
173 #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
174 #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
175 #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
176 #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
177 #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
178
179 /* Bits in received packet status byte and EN0_RSR*/
180 #define ENRSR_RXOK 0x01 /* Received a good packet */
181 #define ENRSR_CRC 0x02 /* CRC error */
182 #define ENRSR_FAE 0x04 /* frame alignment error */
183 #define ENRSR_FO 0x08 /* FIFO overrun */
184 #define ENRSR_MPA 0x10 /* missed pkt */
185 #define ENRSR_PHY 0x20 /* physical/multicast address */
186 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
187 #define ENRSR_DEF 0x80 /* deferring */
188
189 /* Transmitted packet status, EN0_TSR. */
190 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
191 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
192 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
193 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
194 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
195 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
196 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
197 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
198
199 #endif /* _8390_h */
200
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