1 /* $Id$
2 * vmelance.c: Ethernet driver for VME Lance cards on Baget/MIPS
3 * This code stealed and adopted from linux/drivers/net/atarilance.c
4 * See that for author info
5 *
6 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
7 */
8
9 /*
10 * Driver code for Baget/Lance taken from atarilance.c, which also
11 * works well in case of Besta. Most significant changes made here
12 * related with 16BIT-only access to A24 space.
13 */
14
15 static char *version = "bagetlance.c: v1.1 11/10/98\n";
16
17 #include <linux/module.h>
18
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/errno.h>
25 #include <linux/malloc.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28
29 #include <asm/irq.h>
30 #include <asm/bitops.h>
31 #include <asm/io.h>
32
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36
37 #include <asm/baget/baget.h>
38
39 #define BAGET_LANCE_IRQ BAGET_IRQ_MASK(0xdf)
40
41 /*
42 * Define following if you don't need 16BIT-only access to Lance memory
43 * (Normally BAGET needs it)
44 */
45 #undef NORMAL_MEM_ACCESS
46
47 /* Debug level:
48 * 0 = silent, print only serious errors
49 * 1 = normal, print error messages
50 * 2 = debug, print debug infos
51 * 3 = debug, print even more debug infos (packet data)
52 */
53
54 #define LANCE_DEBUG 1
55
56 #ifdef LANCE_DEBUG
57 static int lance_debug = LANCE_DEBUG;
58 #else
59 static int lance_debug = 1;
60 #endif
61 MODULE_PARM(lance_debug, "i");
62
63 /* Print debug messages on probing? */
64 #undef LANCE_DEBUG_PROBE
65
66 #define DPRINTK(n,a) \
67 do { \
68 if (lance_debug >= n) \
69 printk a; \
70 } while( 0 )
71
72 #ifdef LANCE_DEBUG_PROBE
73 # define PROBE_PRINT(a) printk a
74 #else
75 # define PROBE_PRINT(a)
76 #endif
77
78 /* These define the number of Rx and Tx buffers as log2. (Only powers
79 * of two are valid)
80 * Much more rx buffers (32) are reserved than tx buffers (8), since receiving
81 * is more time critical then sending and packets may have to remain in the
82 * board's memory when main memory is low.
83 */
84
85 /* Baget Lance has 64K on-board memory, so it looks we can't increase
86 buffer quantity (40*1.5K is about 64K) */
87
88 #define TX_LOG_RING_SIZE 3
89 #define RX_LOG_RING_SIZE 5
90
91 /* These are the derived values */
92
93 #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE)
94 #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5)
95 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
96
97 #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE)
98 #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5)
99 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
100
101 /* The LANCE Rx and Tx ring descriptors. */
102 struct lance_rx_head {
103 volatile unsigned short base; /* Low word of base addr */
104 #ifdef NORMAL_MEM_ACCESS
105 /* Following two fields are joined into one short to guarantee
106 16BIT access to Baget lance registers */
107 volatile unsigned char flag;
108 unsigned char base_hi; /* High word of base addr (unused) */
109 #else
110 /* Following macros are used as replecements to 8BIT fields */
111 #define GET_FLAG(h) (((h)->flag_base_hi >> 8) & 0xff)
112 #define SET_FLAG(h,f) (h)->flag_base_hi = ((h)->flag_base_hi & 0xff) | \
113 (((unsigned)(f)) << 8)
114 volatile unsigned short flag_base_hi;
115 #endif
116 volatile short buf_length; /* This length is 2s complement! */
117 volatile short msg_length; /* This length is "normal". */
118 };
119
120
121 struct lance_tx_head {
122 volatile unsigned short base; /* Low word of base addr */
123 #ifdef NORMAL_MEM_ACCESS
124 /* See comments above about 8BIT-access Baget A24-space problems */
125 volatile unsigned char flag;
126 unsigned char base_hi; /* High word of base addr (unused) */
127 #else
128 volatile unsigned short flag_base_hi;
129 #endif
130 volatile short length; /* Length is 2s complement! */
131 volatile short misc;
132 };
133
134 struct ringdesc {
135 volatile unsigned short adr_lo; /* Low 16 bits of address */
136 #ifdef NORMAL_MEM_ACCESS
137 /* See comments above about 8BIT-access Bage A24-space problems */
138 unsigned char len; /* Length bits */
139 unsigned char adr_hi; /* High 8 bits of address (unused) */
140 #else
141 volatile unsigned short len_adr_hi;
142 #endif
143 };
144
145 /* The LANCE initialization block, described in databook. */
146 struct lance_init_block {
147 unsigned short mode; /* Pre-set mode */
148 unsigned char hwaddr[6]; /* Physical ethernet address */
149 unsigned filter[2]; /* Multicast filter (unused). */
150 /* Receive and transmit ring base, along with length bits. */
151 struct ringdesc rx_ring;
152 struct ringdesc tx_ring;
153 };
154
155 /* The whole layout of the Lance shared memory */
156 struct lance_memory {
157 struct lance_init_block init;
158 struct lance_tx_head tx_head[TX_RING_SIZE];
159 struct lance_rx_head rx_head[RX_RING_SIZE];
160 char packet_area[0]; /* packet data follow after the
161 * init block and the ring
162 * descriptors and are located
163 * at runtime */
164 };
165
166 /* RieblCard specifics:
167 * The original TOS driver for these cards reserves the area from offset
168 * 0xee70 to 0xeebb for storing configuration data. Of interest to us is the
169 * Ethernet address there, and the magic for verifying the data's validity.
170 * The reserved area isn't touch by packet buffers. Furthermore, offset 0xfffe
171 * is reserved for the interrupt vector number.
172 */
173 #define RIEBL_RSVD_START 0xee70
174 #define RIEBL_RSVD_END 0xeec0
175 #define RIEBL_MAGIC 0x09051990
176 #define RIEBL_MAGIC_ADDR ((unsigned long *)(((char *)MEM) + 0xee8a))
177 #define RIEBL_HWADDR_ADDR ((unsigned char *)(((char *)MEM) + 0xee8e))
178 #define RIEBL_IVEC_ADDR ((unsigned short *)(((char *)MEM) + 0xfffe))
179
180 /* This is a default address for the old RieblCards without a battery
181 * that have no ethernet address at boot time. 00:00:36:04 is the
182 * prefix for Riebl cards, the 00:00 at the end is arbitrary.
183 */
184
185 static unsigned char OldRieblDefHwaddr[6] = {
186 0x00, 0x00, 0x36, 0x04, 0x00, 0x00
187 };
188
189 /* I/O registers of the Lance chip */
190
191 struct lance_ioreg {
192 /* base+0x0 */ volatile unsigned short data;
193 /* base+0x2 */ volatile unsigned short addr;
194 unsigned char _dummy1[3];
195 /* base+0x7 */ volatile unsigned char ivec;
196 unsigned char _dummy2[5];
197 /* base+0xd */ volatile unsigned char eeprom;
198 unsigned char _dummy3;
199 /* base+0xf */ volatile unsigned char mem;
200 };
201
202 /* Types of boards this driver supports */
203
204 enum lance_type {
205 OLD_RIEBL, /* old Riebl card without battery */
206 NEW_RIEBL, /* new Riebl card with battery */
207 PAM_CARD /* PAM card with EEPROM */
208 };
209
210 static char *lance_names[] = {
211 "Riebl-Card (without battery)",
212 "Riebl-Card (with battery)",
213 "PAM intern card"
214 };
215
216 /* The driver's private device structure */
217
218 struct lance_private {
219 enum lance_type cardtype;
220 struct lance_ioreg *iobase;
221 struct lance_memory *mem;
222 int cur_rx, cur_tx; /* The next free ring entry */
223 int dirty_tx; /* Ring entries to be freed. */
224 /* copy function */
225 void *(*memcpy_f)( void *, const void *, size_t );
226 struct net_device_stats stats;
227 /* These two must be longs for set_bit() */
228 long tx_full;
229 long lock;
230 };
231
232 /* I/O register access macros */
233
234 #define MEM lp->mem
235 #define DREG IO->data
236 #define AREG IO->addr
237 #define REGA(a) ( AREG = (a), DREG )
238
239 /* Definitions for packet buffer access: */
240 #define PKT_BUF_SZ 1544
241 /* Get the address of a packet buffer corresponding to a given buffer head */
242 #define PKTBUF_ADDR(head) (((unsigned char *)(MEM)) + (head)->base)
243
244 /* Possible memory/IO addresses for probing */
245
246 struct lance_addr {
247 unsigned long memaddr;
248 unsigned long ioaddr;
249 int slow_flag;
250 } lance_addr_list[] = {
251 { BAGET_LANCE_MEM_BASE, BAGET_LANCE_IO_BASE, 1 } /* Baget Lance */
252 };
253
254 #define N_LANCE_ADDR (sizeof(lance_addr_list)/sizeof(*lance_addr_list))
255
256
257 #define LANCE_HI_BASE (0xff & (BAGET_LANCE_MEM_BASE >> 16))
258
259 /* Definitions for the Lance */
260
261 /* tx_head flags */
262 #define TMD1_ENP 0x01 /* end of packet */
263 #define TMD1_STP 0x02 /* start of packet */
264 #define TMD1_DEF 0x04 /* deferred */
265 #define TMD1_ONE 0x08 /* one retry needed */
266 #define TMD1_MORE 0x10 /* more than one retry needed */
267 #define TMD1_ERR 0x40 /* error summary */
268 #define TMD1_OWN 0x80 /* ownership (set: chip owns) */
269
270 #define TMD1_OWN_CHIP TMD1_OWN
271 #define TMD1_OWN_HOST 0
272
273 /* tx_head misc field */
274 #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */
275 #define TMD3_RTRY 0x0400 /* failed after 16 retries */
276 #define TMD3_LCAR 0x0800 /* carrier lost */
277 #define TMD3_LCOL 0x1000 /* late collision */
278 #define TMD3_UFLO 0x4000 /* underflow (late memory) */
279 #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */
280
281 /* rx_head flags */
282 #define RMD1_ENP 0x01 /* end of packet */
283 #define RMD1_STP 0x02 /* start of packet */
284 #define RMD1_BUFF 0x04 /* buffer error */
285 #define RMD1_CRC 0x08 /* CRC error */
286 #define RMD1_OFLO 0x10 /* overflow */
287 #define RMD1_FRAM 0x20 /* framing error */
288 #define RMD1_ERR 0x40 /* error summary */
289 #define RMD1_OWN 0x80 /* ownership (set: ship owns) */
290
291 #define RMD1_OWN_CHIP RMD1_OWN
292 #define RMD1_OWN_HOST 0
293
294 /* register names */
295 #define CSR0 0 /* mode/status */
296 #define CSR1 1 /* init block addr (low) */
297 #define CSR2 2 /* init block addr (high) */
298 #define CSR3 3 /* misc */
299 #define CSR8 8 /* address filter */
300 #define CSR15 15 /* promiscuous mode */
301
302 /* CSR0 */
303 /* (R=readable, W=writeable, S=set on write, C=clear on write) */
304 #define CSR0_INIT 0x0001 /* initialize (RS) */
305 #define CSR0_STRT 0x0002 /* start (RS) */
306 #define CSR0_STOP 0x0004 /* stop (RS) */
307 #define CSR0_TDMD 0x0008 /* transmit demand (RS) */
308 #define CSR0_TXON 0x0010 /* transmitter on (R) */
309 #define CSR0_RXON 0x0020 /* receiver on (R) */
310 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */
311 #define CSR0_INTR 0x0080 /* interrupt active (R) */
312 #define CSR0_IDON 0x0100 /* initialization done (RC) */
313 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */
314 #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */
315 #define CSR0_MERR 0x0800 /* memory error (RC) */
316 #define CSR0_MISS 0x1000 /* missed frame (RC) */
317 #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */
318 #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */
319 #define CSR0_ERR 0x8000 /* error (RC) */
320
321 /* CSR3 */
322 #define CSR3_BCON 0x0001 /* byte control */
323 #define CSR3_ACON 0 // fixme: 0x0002 /* ALE control */
324 #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */
325
326
327
328 /***************************** Prototypes *****************************/
329
330 static int addr_accessible( volatile void *regp, int wordflag, int
331 writeflag );
332 static int lance_probe1( struct net_device *dev, struct lance_addr *init_rec );
333 static int lance_open( struct net_device *dev );
334 static void lance_init_ring( struct net_device *dev );
335 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev );
336 static void lance_interrupt( int irq, void *dev_id, struct pt_regs *fp );
337 static int lance_rx( struct net_device *dev );
338 static int lance_close( struct net_device *dev );
339 static struct net_device_stats *lance_get_stats( struct net_device *dev );
340 static void set_multicast_list( struct net_device *dev );
341 static int lance_set_mac_address( struct net_device *dev, void *addr );
342
343 /************************* End of Prototypes **************************/
344
345 /* Network traffic statistic (bytes) */
346
347 int lance_stat = 0;
348
349 static void update_lance_stat (int len) {
350 lance_stat += len;
351 }
352
353 /*
354 This function is used to access Baget/Lance memory to avoid
355 8/32BIT access to VAC A24 space
356 ALL memcpy calls was chenged to this function to avoid dbe problems
357 Don't confuse with function name -- it stays from original code
358 */
359
360 void *slow_memcpy( void *dst, const void *src, size_t len )
361
362 {
363 unsigned long to = (unsigned long)dst;
364 unsigned long from = (unsigned long)src;
365 unsigned long to_end = to +len;
366
367 /* Unaligned flags */
368
369 int odd_from = from & 1;
370 int odd_to = to & 1;
371 int odd_to_end = to_end & 1;
372
373 /* Align for 16BIT-access first */
374
375 register unsigned short *from_a = (unsigned short*) (from & ~1);
376 register unsigned short *to_a = (unsigned short*) (to & ~1);
377 register unsigned short *to_end_a = (unsigned short*) (to_end & ~1);
378
379 /* Caching values -- not in loop invariant */
380
381 register unsigned short from_v;
382 register unsigned short to_v;
383
384 /* Invariant is: from_a and to_a are pointers before or exactly to
385 currently copying byte */
386
387 if (odd_to) {
388 /* First byte unaligned case */
389 from_v = *from_a;
390 to_v = *to_a;
391
392 to_v &= ~0xff;
393 to_v |= 0xff & (from_v >> (odd_from ? 0 : 8));
394 *to_a++ = to_v;
395
396 if (odd_from) from_a++;
397 }
398 if (odd_from == odd_to) {
399 /* Same parity */
400 while (to_a + 7 < to_end_a) {
401 unsigned long dummy1, dummy2;
402 unsigned long reg1, reg2, reg3, reg4;
403
404 __asm__ __volatile__(
405 ".set\tnoreorder\n\t"
406 ".set\tnoat\n\t"
407 "lh\t%2,0(%1)\n\t"
408 "nop\n\t"
409 "lh\t%3,2(%1)\n\t"
410 "sh\t%2,0(%0)\n\t"
411 "lh\t%4,4(%1)\n\t"
412 "sh\t%3,2(%0)\n\t"
413 "lh\t%5,6(%1)\n\t"
414 "sh\t%4,4(%0)\n\t"
415 "lh\t%2,8(%1)\n\t"
416 "sh\t%5,6(%0)\n\t"
417 "lh\t%3,10(%1)\n\t"
418 "sh\t%2,8(%0)\n\t"
419 "lh\t%4,12(%1)\n\t"
420 "sh\t%3,10(%0)\n\t"
421 "lh\t%5,14(%1)\n\t"
422 "sh\t%4,12(%0)\n\t"
423 "nop\n\t"
424 "sh\t%5,14(%0)\n\t"
425 ".set\tat\n\t"
426 ".set\treorder"
427 :"=r" (dummy1), "=r" (dummy2),
428 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
429 :"" (to_a), "1" (from_a)
430 :"memory");
431
432 to_a += 8;
433 from_a += 8;
434
435 }
436 while (to_a < to_end_a) {
437 *to_a++ = *from_a++;
438 }
439 } else {
440 /* Different parity */
441 from_v = *from_a;
442 while (to_a < to_end_a) {
443 unsigned short from_v_next;
444 from_v_next = *++from_a;
445 *to_a++ = ((from_v & 0xff)<<8) | ((from_v_next>>8) & 0xff);
446 from_v = from_v_next;
447 }
448
449 }
450 if (odd_to_end) {
451 /* Last byte unaligned case */
452 to_v = *to_a;
453 from_v = *from_a;
454
455 to_v &= ~0xff00;
456 if (odd_from == odd_to) {
457 to_v |= from_v & 0xff00;
458 } else {
459 to_v |= (from_v<<8) & 0xff00;
460 }
461
462 *to_a = to_v;
463 }
464
465 update_lance_stat( len );
466
467 return( dst );
468 }
469
470
471 int __init bagetlance_probe( struct net_device *dev )
472
473 { int i;
474 static int found = 0;
475
476 SET_MODULE_OWNER(dev);
477
478 if (found)
479 /* Assume there's only one board possible... That seems true, since
480 * the Riebl/PAM board's address cannot be changed. */
481 return( -ENODEV );
482
483 for( i = 0; i < N_LANCE_ADDR; ++i ) {
484 if (lance_probe1( dev, &lance_addr_list[i] )) {
485 found = 1;
486 return( 0 );
487 }
488 }
489
490 return( -ENODEV );
491 }
492
493
494
495 /* Derived from hwreg_present() in vme/config.c: */
496
497 static int __init addr_accessible( volatile void *regp,
498 int wordflag,
499 int writeflag )
500 {
501 /* We have a fine function to do it */
502 extern int try_read(unsigned long, int);
503 return try_read((unsigned long)regp, sizeof(short)) != -1;
504 }
505
506
507
508 /* Original atari driver uses it */
509 #define IRQ_TYPE_PRIO SA_INTERRUPT
510 #define IRQ_SOURCE_TO_VECTOR(x) (x)
511
512 static int __init lance_probe1( struct net_device *dev,
513 struct lance_addr *init_rec )
514
515 { volatile unsigned short *memaddr =
516 (volatile unsigned short *)init_rec->memaddr;
517 volatile unsigned short *ioaddr =
518 (volatile unsigned short *)init_rec->ioaddr;
519 struct lance_private *lp;
520 struct lance_ioreg *IO;
521 int i;
522 static int did_version = 0;
523 unsigned short save1, save2;
524
525 PROBE_PRINT(( "Probing for Lance card at mem %#lx io %#lx\n",
526 (long)memaddr, (long)ioaddr ));
527
528 /* Test whether memory readable and writable */
529 PROBE_PRINT(( "lance_probe1: testing memory to be accessible\n" ));
530 if (!addr_accessible( memaddr, 1, 1 )) goto probe_fail;
531
532 if ((unsigned long)memaddr >= KSEG2) {
533 extern int kseg2_alloc_io (unsigned long addr, unsigned long size);
534 if (kseg2_alloc_io((unsigned long)memaddr, BAGET_LANCE_MEM_SIZE)) {
535 printk("bagetlance: unable map lance memory\n");
536 goto probe_fail;
537 }
538 }
539
540 /* Written values should come back... */
541 PROBE_PRINT(( "lance_probe1: testing memory to be writable (1)\n" ));
542 save1 = *memaddr;
543 *memaddr = 0x0001;
544 if (*memaddr != 0x0001) goto probe_fail;
545 PROBE_PRINT(( "lance_probe1: testing memory to be writable (2)\n" ));
546 *memaddr = 0x0000;
547 if (*memaddr != 0x0000) goto probe_fail;
548 *memaddr = save1;
549
550 /* First port should be readable and writable */
551 PROBE_PRINT(( "lance_probe1: testing ioport to be accessible\n" ));
552 if (!addr_accessible( ioaddr, 1, 1 )) goto probe_fail;
553
554 /* and written values should be readable */
555 PROBE_PRINT(( "lance_probe1: testing ioport to be writeable\n" ));
556 save2 = ioaddr[1];
557 ioaddr[1] = 0x0001;
558 if (ioaddr[1] != 0x0001) goto probe_fail;
559
560 /* The CSR0_INIT bit should not be readable */
561 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (1)\n" ));
562 save1 = ioaddr[0];
563 ioaddr[1] = CSR0;
564 ioaddr[0] = CSR0_INIT | CSR0_STOP;
565 if (ioaddr[0] != CSR0_STOP) {
566 ioaddr[0] = save1;
567 ioaddr[1] = save2;
568 goto probe_fail;
569 }
570 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (2)\n" ));
571 ioaddr[0] = CSR0_STOP;
572 if (ioaddr[0] != CSR0_STOP) {
573 ioaddr[0] = save1;
574 ioaddr[1] = save2;
575 goto probe_fail;
576 }
577
578 /* Now ok... */
579 PROBE_PRINT(( "lance_probe1: Lance card detected\n" ));
580 goto probe_ok;
581
582 probe_fail:
583 return( 0 );
584
585 probe_ok:
586 init_etherdev( dev, sizeof(struct lance_private) );
587 if (!dev->priv)
588 dev->priv = kmalloc( sizeof(struct lance_private), GFP_KERNEL );
589 lp = (struct lance_private *)dev->priv;
590 MEM = (struct lance_memory *)memaddr;
591 IO = lp->iobase = (struct lance_ioreg *)ioaddr;
592 dev->base_addr = (unsigned long)ioaddr; /* informational only */
593 lp->memcpy_f = init_rec->slow_flag ? slow_memcpy : memcpy;
594
595 REGA( CSR0 ) = CSR0_STOP;
596
597 /* Now test for type: If the eeprom I/O port is readable, it is a
598 * PAM card */
599 if (addr_accessible( &(IO->eeprom), 0, 0 )) {
600 /* Switch back to Ram */
601 i = IO->mem;
602 lp->cardtype = PAM_CARD;
603 }
604 #ifdef NORMAL_MEM_ACCESS
605 else if (*RIEBL_MAGIC_ADDR == RIEBL_MAGIC) {
606 #else
607 else if (({
608 unsigned short *a = (unsigned short*)RIEBL_MAGIC_ADDR;
609 (((int)a[0]) << 16) + ((int)a[1]) == RIEBL_MAGIC;
610 })) {
611 #endif
612 lp->cardtype = NEW_RIEBL;
613 }
614 else
615 lp->cardtype = OLD_RIEBL;
616
617 if (lp->cardtype == PAM_CARD ||
618 memaddr == (unsigned short *)0xffe00000) {
619 /* PAMs card and Riebl on ST use level 5 autovector */
620 request_irq(BAGET_LANCE_IRQ, lance_interrupt, IRQ_TYPE_PRIO,
621 "PAM/Riebl-ST Ethernet", dev);
622 dev->irq = (unsigned short)BAGET_LANCE_IRQ;
623 }
624 else {
625 /* For VME-RieblCards, request a free VME int;
626 * (This must be unsigned long, since dev->irq is short and the
627 * IRQ_MACHSPEC bit would be cut off...)
628 */
629 unsigned long irq = BAGET_LANCE_IRQ;
630 if (!irq) {
631 printk( "Lance: request for VME interrupt failed\n" );
632 return( 0 );
633 }
634 request_irq(irq, lance_interrupt, IRQ_TYPE_PRIO,
635 "Riebl-VME Ethernet", dev);
636 dev->irq = irq;
637 }
638
639 printk("%s: %s at io %#lx, mem %#lx, irq %d%s, hwaddr ",
640 dev->name, lance_names[lp->cardtype],
641 (unsigned long)ioaddr,
642 (unsigned long)memaddr,
643 dev->irq,
644 init_rec->slow_flag ? " (slow memcpy)" : "" );
645
646 /* Get the ethernet address */
647 switch( lp->cardtype ) {
648 case OLD_RIEBL:
649 /* No ethernet address! (Set some default address) */
650 slow_memcpy( dev->dev_addr, OldRieblDefHwaddr, 6 );
651 break;
652 case NEW_RIEBL:
653 lp->memcpy_f( dev->dev_addr, RIEBL_HWADDR_ADDR, 6 );
654 break;
655 case PAM_CARD:
656 i = IO->eeprom;
657 for( i = 0; i < 6; ++i )
658 dev->dev_addr[i] =
659 ((((unsigned short *)MEM)[i*2] & 0x0f) << 4) |
660 ((((unsigned short *)MEM)[i*2+1] & 0x0f));
661 i = IO->mem;
662 break;
663 }
664 for( i = 0; i < 6; ++i )
665 printk( "%02x%s", dev->dev_addr[i], (i < 5) ? ":" : "\n" );
666 if (lp->cardtype == OLD_RIEBL) {
667 printk( "%s: Warning: This is a default ethernet address!\n",
668 dev->name );
669 printk( " Use \"ifconfig hw ether ...\" to set the address.\n" );
670 }
671
672 MEM->init.mode = 0x0000; /* Disable Rx and Tx. */
673
674 {
675 unsigned char hwaddr[6];
676 for( i = 0; i < 6; i++ )
677 hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
678 slow_memcpy(MEM->init.hwaddr, hwaddr, sizeof(hwaddr));
679 }
680
681 MEM->init.filter[0] = 0x00000000;
682 MEM->init.filter[1] = 0x00000000;
683 MEM->init.rx_ring.adr_lo = offsetof( struct lance_memory, rx_head );
684
685 #ifdef NORMAL_MEM_ACCESS
686 MEM->init.rx_ring.adr_hi = LANCE_HI_BASE;
687 MEM->init.rx_ring.len = RX_RING_LEN_BITS;
688 #else
689 MEM->init.rx_ring.len_adr_hi =
690 ((unsigned)RX_RING_LEN_BITS << 8) | LANCE_HI_BASE;
691 #endif
692
693
694 MEM->init.tx_ring.adr_lo = offsetof( struct lance_memory, tx_head );
695
696 #ifdef NORMAL_MEM_ACCESS
697 MEM->init.tx_ring.adr_hi = LANCE_HI_BASE;
698 MEM->init.tx_ring.len = TX_RING_LEN_BITS;
699 #else
700 MEM->init.tx_ring.len_adr_hi =
701 ((unsigned)TX_RING_LEN_BITS<<8) | LANCE_HI_BASE;
702 #endif
703
704 if (lp->cardtype == PAM_CARD)
705 IO->ivec = IRQ_SOURCE_TO_VECTOR(dev->irq);
706 else
707 *RIEBL_IVEC_ADDR = IRQ_SOURCE_TO_VECTOR(dev->irq);
708
709 if (did_version++ == 0)
710 DPRINTK( 1, ( version ));
711
712 /* The LANCE-specific entries in the device structure. */
713 dev->open = &lance_open;
714 dev->hard_start_xmit = &lance_start_xmit;
715 dev->stop = &lance_close;
716 dev->get_stats = &lance_get_stats;
717 dev->set_multicast_list = &set_multicast_list;
718 dev->set_mac_address = &lance_set_mac_address;
719 dev->start = 0;
720
721 memset( &lp->stats, 0, sizeof(lp->stats) );
722
723 return( 1 );
724 }
725
726
727 static int lance_open( struct net_device *dev )
728
729 { struct lance_private *lp = (struct lance_private *)dev->priv;
730 struct lance_ioreg *IO = lp->iobase;
731 int i;
732
733 DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
734
735 lance_init_ring(dev);
736 /* Re-initialize the LANCE, and start it when done. */
737
738 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
739 REGA( CSR2 ) = 0;
740 REGA( CSR1 ) = 0;
741 REGA( CSR0 ) = CSR0_INIT;
742 /* From now on, AREG is kept to point to CSR0 */
743
744 i = 1000000;
745 while (--i > 0)
746 if (DREG & CSR0_IDON)
747 break;
748 if (i < 0 || (DREG & CSR0_ERR)) {
749 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
750 dev->name, i, DREG ));
751 DREG = CSR0_STOP;
752 return( -EIO );
753 }
754 DREG = CSR0_IDON;
755 DREG = CSR0_STRT;
756 DREG = CSR0_INEA;
757
758 dev->tbusy = 0;
759 dev->interrupt = 0;
760 dev->start = 1;
761
762 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
763 return( 0 );
764 }
765
766
767 /* Initialize the LANCE Rx and Tx rings. */
768
769 static void lance_init_ring( struct net_device *dev )
770
771 { struct lance_private *lp = (struct lance_private *)dev->priv;
772 int i;
773 unsigned offset;
774
775 lp->lock = 0;
776 lp->tx_full = 0;
777 lp->cur_rx = lp->cur_tx = 0;
778 lp->dirty_tx = 0;
779
780 offset = offsetof( struct lance_memory, packet_area );
781
782 /* If the packet buffer at offset 'o' would conflict with the reserved area
783 * of RieblCards, advance it */
784 #define CHECK_OFFSET(o) \
785 do { \
786 if (lp->cardtype == OLD_RIEBL || lp->cardtype == NEW_RIEBL) { \
787 if (((o) < RIEBL_RSVD_START) ? (o)+PKT_BUF_SZ > RIEBL_RSVD_START \
788 : (o) < RIEBL_RSVD_END) \
789 (o) = RIEBL_RSVD_END; \
790 } \
791 } while(0)
792
793 for( i = 0; i < TX_RING_SIZE; i++ ) {
794 CHECK_OFFSET(offset);
795 MEM->tx_head[i].base = offset;
796 #ifdef NORMAL_MEM_ACCESS
797 MEM->tx_head[i].flag = TMD1_OWN_HOST;
798 MEM->tx_head[i].base_hi = LANCE_HI_BASE;
799 #else
800 MEM->tx_head[i].flag_base_hi =
801 (TMD1_OWN_HOST<<8) | LANCE_HI_BASE;
802 #endif
803 MEM->tx_head[i].length = 0;
804 MEM->tx_head[i].misc = 0;
805 offset += PKT_BUF_SZ;
806 }
807
808 for( i = 0; i < RX_RING_SIZE; i++ ) {
809 CHECK_OFFSET(offset);
810 MEM->rx_head[i].base = offset;
811 #ifdef NORMAL_MEM_ACCESS
812 MEM->rx_head[i].flag = TMD1_OWN_CHIP;
813 MEM->rx_head[i].base_hi = LANCE_HI_BASE;
814 #else
815 MEM->rx_head[i].flag_base_hi =
816 (TMD1_OWN_CHIP<<8) | LANCE_HI_BASE;
817 #endif
818 MEM->rx_head[i].buf_length = -PKT_BUF_SZ;
819 MEM->rx_head[i].msg_length = 0;
820 offset += PKT_BUF_SZ;
821 }
822 }
823
824
825 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev )
826
827 { struct lance_private *lp = (struct lance_private *)dev->priv;
828 struct lance_ioreg *IO = lp->iobase;
829 int entry, len;
830 struct lance_tx_head *head;
831 unsigned long flags;
832
833 /* Transmitter timeout, serious problems. */
834 if (dev->tbusy) {
835 int tickssofar = jiffies - dev->trans_start;
836 if (tickssofar < 20)
837 return( 1 );
838 AREG = CSR0;
839 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
840 dev->name, DREG ));
841 DREG = CSR0_STOP;
842 /*
843 * Always set BSWP after a STOP as STOP puts it back into
844 * little endian mode.
845 */
846 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
847 lp->stats.tx_errors++;
848 #ifndef final_version
849 { int i;
850 DPRINTK( 2, ( "Ring data: dirty_tx %d cur_tx %d%s cur_rx %d\n",
851 lp->dirty_tx, lp->cur_tx,
852 lp->tx_full ? " (full)" : "",
853 lp->cur_rx ));
854 for( i = 0 ; i < RX_RING_SIZE; i++ )
855 DPRINTK( 2, ( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
856 i, MEM->rx_head[i].base,
857 -MEM->rx_head[i].buf_length,
858 MEM->rx_head[i].msg_length ));
859 for( i = 0 ; i < TX_RING_SIZE; i++ )
860 DPRINTK( 2, ( "tx #%d: base=%04x len=%04x misc=%04x\n",
861 i, MEM->tx_head[i].base,
862 -MEM->tx_head[i].length,
863 MEM->tx_head[i].misc ));
864 }
865 #endif
866 lance_init_ring(dev);
867 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
868
869 dev->tbusy = 0;
870 dev->trans_start = jiffies;
871
872 return( 0 );
873 }
874
875 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
876 dev->name, DREG ));
877
878 /* Block a timer-based transmit from overlapping. This could better be
879 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
880 if (test_and_set_bit( 0, (void*)&dev->tbusy ) != 0) {
881 DPRINTK( 0, ( "%s: Transmitter access conflict.\n", dev->name ));
882 return 1;
883 }
884
885 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
886 DPRINTK( 0, ( "%s: tx queue lock!.\n", dev->name ));
887 /* don't clear dev->tbusy flag. */
888 return 1;
889 }
890
891 /* Fill in a Tx ring entry */
892 if (lance_debug >= 3) {
893 u_char *p;
894 int i;
895 printk( "%s: TX pkt type 0x%04x from ", dev->name,
896 ((u_short *)skb->data)[6]);
897 for( p = &((u_char *)skb->data)[6], i = 0; i < 6; i++ )
898 printk("%02x%s", *p++, i != 5 ? ":" : "" );
899 printk(" to ");
900 for( p = (u_char *)skb->data, i = 0; i < 6; i++ )
901 printk("%02x%s", *p++, i != 5 ? ":" : "" );
902 printk(" data at 0x%08x len %d\n", (int)skb->data,
903 (int)skb->len );
904 }
905
906 /* We're not prepared for the int until the last flags are set/reset. And
907 * the int may happen already after setting the OWN_CHIP... */
908 save_flags(flags);
909 cli();
910
911 /* Mask to ring buffer boundary. */
912 entry = lp->cur_tx & TX_RING_MOD_MASK;
913 head = &(MEM->tx_head[entry]);
914
915 /* Caution: the write order is important here, set the "ownership" bits
916 * last.
917 */
918
919 /* The old LANCE chips doesn't automatically pad buffers to min. size. */
920 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
921 /* PAM-Card has a bug: Can only send packets with even number of bytes! */
922 if (lp->cardtype == PAM_CARD && (len & 1))
923 ++len;
924
925 head->length = -len;
926 head->misc = 0;
927 lp->memcpy_f( PKTBUF_ADDR(head), (void *)skb->data, skb->len );
928 #ifdef NORMAL_MEM_ACCESS
929 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
930 #else
931 SET_FLAG(head,(TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP));
932 #endif
933 dev_kfree_skb( skb );
934 lp->cur_tx++;
935 lp->stats.tx_bytes += skb->len;
936 while( lp->cur_tx >= TX_RING_SIZE && lp->dirty_tx >= TX_RING_SIZE ) {
937 lp->cur_tx -= TX_RING_SIZE;
938 lp->dirty_tx -= TX_RING_SIZE;
939 }
940
941 /* Trigger an immediate send poll. */
942 DREG = CSR0_INEA | CSR0_TDMD;
943 dev->trans_start = jiffies;
944
945 lp->lock = 0;
946 #ifdef NORMAL_MEM_ACCESS
947 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
948 #else
949 if ((GET_FLAG(&MEM->tx_head[(entry+1) & TX_RING_MOD_MASK]) & TMD1_OWN) ==
950 #endif
951 TMD1_OWN_HOST)
952 dev->tbusy = 0;
953 else
954 lp->tx_full = 1;
955 restore_flags(flags);
956
957 return 0;
958 }
959
960 /* The LANCE interrupt handler. */
961
962 static void lance_interrupt( int irq, void *dev_id, struct pt_regs *fp)
963 {
964 struct net_device *dev = dev_id;
965 struct lance_private *lp;
966 struct lance_ioreg *IO;
967 int csr0, boguscnt = 10;
968
969 if (dev == NULL) {
970 DPRINTK( 1, ( "lance_interrupt(): interrupt for unknown device.\n" ));
971 return;
972 }
973
974 lp = (struct lance_private *)dev->priv;
975 IO = lp->iobase;
976 AREG = CSR0;
977
978 if (dev->interrupt) {
979 DPRINTK( 1, ( "Re-entering CAUSE=%08x STATUS=%08x\n",
980 read_32bit_cp0_register(CP0_CAUSE),
981 read_32bit_cp0_register(CP0_STATUS) ));
982 panic("lance: interrupt handler reentered !");
983 }
984
985 dev->interrupt = 1;
986
987 while( ((csr0 = DREG) & (CSR0_ERR | CSR0_TINT | CSR0_RINT)) &&
988 --boguscnt >= 0) {
989 /* Acknowledge all of the current interrupt sources ASAP. */
990 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP |
991 CSR0_TDMD | CSR0_INEA);
992
993 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n",
994 dev->name, csr0, DREG ));
995
996 if (csr0 & CSR0_RINT) /* Rx interrupt */
997 lance_rx( dev );
998
999 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */
1000 int dirty_tx = lp->dirty_tx;
1001
1002 while( dirty_tx < lp->cur_tx) {
1003 int entry = dirty_tx & TX_RING_MOD_MASK;
1004 #ifdef NORMAL_MEM_ACCESS
1005 int status = MEM->tx_head[entry].flag;
1006 #else
1007 int status = GET_FLAG(&MEM->tx_head[entry]);
1008 #endif
1009 if (status & TMD1_OWN_CHIP)
1010 break; /* It still hasn't been Txed */
1011
1012 #ifdef NORMAL_MEM_ACCESS
1013 MEM->tx_head[entry].flag = 0;
1014 #else
1015 SET_FLAG(&MEM->tx_head[entry],0);
1016 #endif
1017
1018 if (status & TMD1_ERR) {
1019 /* There was an major error, log it. */
1020 int err_status = MEM->tx_head[entry].misc;
1021 lp->stats.tx_errors++;
1022 if (err_status & TMD3_RTRY) lp->stats.tx_aborted_errors++;
1023 if (err_status & TMD3_LCAR) lp->stats.tx_carrier_errors++;
1024 if (err_status & TMD3_LCOL) lp->stats.tx_window_errors++;
1025 if (err_status & TMD3_UFLO) {
1026 /* Ackk! On FIFO errors the Tx unit is turned off! */
1027 lp->stats.tx_fifo_errors++;
1028 /* Remove this verbosity later! */
1029 DPRINTK( 1, ( "%s: Tx FIFO error! Status %04x\n",
1030 dev->name, csr0 ));
1031 /* Restart the chip. */
1032 DREG = CSR0_STRT;
1033 }
1034 } else {
1035 if (status & (TMD1_MORE | TMD1_ONE | TMD1_DEF))
1036 lp->stats.collisions++;
1037 lp->stats.tx_packets++;
1038 }
1039 dirty_tx++;
1040 }
1041
1042 #ifndef final_version
1043 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1044 DPRINTK( 0, ( "out-of-sync dirty pointer,"
1045 " %d vs. %d, full=%d.\n",
1046 dirty_tx, lp->cur_tx, lp->tx_full ));
1047 dirty_tx += TX_RING_SIZE;
1048 }
1049 #endif
1050
1051 if (lp->tx_full && dev->tbusy
1052 && dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1053 /* The ring is no longer full, clear tbusy. */
1054 lp->tx_full = 0;
1055 dev->tbusy = 0;
1056 mark_bh( NET_BH );
1057 }
1058
1059 lp->dirty_tx = dirty_tx;
1060 }
1061
1062 /* Log misc errors. */
1063 if (csr0 & CSR0_BABL) lp->stats.tx_errors++; /* Tx babble. */
1064 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */
1065 if (csr0 & CSR0_MERR) {
1066 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
1067 "status %04x.\n", dev->name, csr0 ));
1068 /* Restart the chip. */
1069 DREG = CSR0_STRT;
1070 }
1071 }
1072
1073 /* Clear any other interrupt, and set interrupt enable. */
1074 DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
1075 CSR0_IDON | CSR0_INEA;
1076
1077 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
1078 dev->name, DREG ));
1079 dev->interrupt = 0;
1080 return;
1081 }
1082
1083
1084 static int lance_rx( struct net_device *dev )
1085
1086 { struct lance_private *lp = (struct lance_private *)dev->priv;
1087 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1088 int i;
1089
1090 #ifdef NORMAL_MEM_ACCESS
1091 DPRINTK( 2, ( "%s: rx int, flag=%04x\n", dev->name,
1092 MEM->rx_head[entry].flag ));
1093 #else
1094 DPRINTK( 2, ( "%s: rx int, flag=%04x\n", dev->name,
1095 GET_FLAG(&MEM->rx_head[entry]) ));
1096 #endif
1097
1098 /* If we own the next entry, it's a new packet. Send it up. */
1099 #ifdef NORMAL_MEM_ACCESS
1100 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
1101 #else
1102 while( (GET_FLAG(&MEM->rx_head[entry]) & RMD1_OWN) == RMD1_OWN_HOST ) {
1103 #endif
1104 struct lance_rx_head *head = &(MEM->rx_head[entry]);
1105 #ifdef NORMAL_MEM_ACCESS
1106 int status = head->flag;
1107 #else
1108 int status = GET_FLAG(head);
1109 #endif
1110
1111 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */
1112 /* There is a tricky error noted by John Murphy,
1113 <murf@perftech.com> to Russ Nelson: Even with full-sized
1114 buffers it's possible for a jabber packet to use two
1115 buffers, with only the last correctly noting the error. */
1116 if (status & RMD1_ENP) /* Only count a general error at the */
1117 lp->stats.rx_errors++; /* end of a packet.*/
1118 if (status & RMD1_FRAM) lp->stats.rx_frame_errors++;
1119 if (status & RMD1_OFLO) lp->stats.rx_over_errors++;
1120 if (status & RMD1_CRC) lp->stats.rx_crc_errors++;
1121 if (status & RMD1_BUFF) lp->stats.rx_fifo_errors++;
1122 #ifdef NORMAL_MEM_ACCESS
1123 head->flag &= (RMD1_ENP|RMD1_STP);
1124 #else
1125 SET_FLAG(head,GET_FLAG(head) & (RMD1_ENP|RMD1_STP));
1126 #endif
1127 } else {
1128 /* Malloc up new buffer, compatible with net-3. */
1129 short pkt_len = head->msg_length & 0xfff;
1130 struct sk_buff *skb;
1131
1132 if (pkt_len < 60) {
1133 printk( "%s: Runt packet!\n", dev->name );
1134 lp->stats.rx_errors++;
1135 }
1136 else {
1137 skb = dev_alloc_skb( pkt_len+2 );
1138 if (skb == NULL) {
1139 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n",
1140 dev->name ));
1141 for( i = 0; i < RX_RING_SIZE; i++ )
1142 #ifdef NORMAL_MEM_ACCESS
1143 if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag &
1144 #else
1145 if (GET_FLAG(&MEM->rx_head[(entry+i) & \
1146 RX_RING_MOD_MASK]) &
1147 #endif
1148 RMD1_OWN_CHIP)
1149 break;
1150
1151 if (i > RX_RING_SIZE - 2) {
1152 lp->stats.rx_dropped++;
1153 #ifdef NORMAL_MEM_ACCESS
1154 head->flag |= RMD1_OWN_CHIP;
1155 #else
1156 SET_FLAG(head,GET_FLAG(head) | RMD1_OWN_CHIP);
1157 #endif
1158 lp->cur_rx++;
1159 }
1160 break;
1161 }
1162
1163 if (lance_debug >= 3) {
1164 u_char *data = PKTBUF_ADDR(head), *p;
1165 printk( "%s: RX pkt type 0x%04x from ", dev->name,
1166 ((u_short *)data)[6]);
1167 for( p = &data[6], i = 0; i < 6; i++ )
1168 printk("%02x%s", *p++, i != 5 ? ":" : "" );
1169 printk(" to ");
1170 for( p = data, i = 0; i < 6; i++ )
1171 printk("%02x%s", *p++, i != 5 ? ":" : "" );
1172 printk(" data %02x %02x %02x %02x %02x %02x %02x %02x "
1173 "len %d\n",
1174 data[15], data[16], data[17], data[18],
1175 data[19], data[20], data[21], data[22],
1176 pkt_len );
1177 }
1178
1179 skb->dev = dev;
1180 skb_reserve( skb, 2 ); /* 16 byte align */
1181 skb_put( skb, pkt_len ); /* Make room */
1182 lp->memcpy_f( skb->data, PKTBUF_ADDR(head), pkt_len );
1183 skb->protocol = eth_type_trans( skb, dev );
1184 netif_rx( skb );
1185 lp->stats.rx_packets++;
1186 lp->stats.rx_bytes += skb->len;
1187 }
1188 }
1189
1190 #ifdef NORMAL_MEM_ACCESS
1191 head->flag |= RMD1_OWN_CHIP;
1192 #else
1193 SET_FLAG(head,GET_FLAG(head) | RMD1_OWN_CHIP);
1194 #endif
1195 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1196 }
1197 lp->cur_rx &= RX_RING_MOD_MASK;
1198
1199 /* From lance.c (Donald Becker): */
1200 /* We should check that at least two ring entries are free. If not,
1201 we should free one and mark stats->rx_dropped++. */
1202
1203 return 0;
1204 }
1205
1206
1207 static int lance_close( struct net_device *dev )
1208
1209 { struct lance_private *lp = (struct lance_private *)dev->priv;
1210 struct lance_ioreg *IO = lp->iobase;
1211
1212 dev->start = 0;
1213 dev->tbusy = 1;
1214
1215 AREG = CSR0;
1216
1217 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
1218 dev->name, DREG ));
1219
1220 /* We stop the LANCE here -- it occasionally polls
1221 memory if we don't. */
1222 DREG = CSR0_STOP;
1223
1224 return 0;
1225 }
1226
1227
1228 static struct net_device_stats *lance_get_stats( struct net_device *dev )
1229
1230 {
1231 struct lance_private *lp = (struct lance_private *)dev->priv;
1232 return &lp->stats;
1233 }
1234
1235
1236 /* Set or clear the multicast filter for this adaptor.
1237 num_addrs == -1 Promiscuous mode, receive all packets
1238 num_addrs == 0 Normal mode, clear multicast list
1239 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1240 best-effort filtering.
1241 */
1242
1243 static void set_multicast_list( struct net_device *dev )
1244
1245 { struct lance_private *lp = (struct lance_private *)dev->priv;
1246 struct lance_ioreg *IO = lp->iobase;
1247
1248 if (!dev->start)
1249 /* Only possible if board is already started */
1250 return;
1251
1252 /* We take the simple way out and always enable promiscuous mode. */
1253 DREG = CSR0_STOP; /* Temporarily stop the lance. */
1254
1255 if (dev->flags & IFF_PROMISC) {
1256 /* Log any net taps. */
1257 DPRINTK( 1, ( "%s: Promiscuous mode enabled.\n", dev->name ));
1258 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
1259 } else {
1260 short multicast_table[4];
1261 int num_addrs = dev->mc_count;
1262 int i;
1263 /* We don't use the multicast table, but rely on upper-layer
1264 * filtering. */
1265 memset( multicast_table, (num_addrs == 0) ? 0 : -1,
1266 sizeof(multicast_table) );
1267 for( i = 0; i < 4; i++ )
1268 REGA( CSR8+i ) = multicast_table[i];
1269 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
1270 }
1271
1272 /*
1273 * Always set BSWP after a STOP as STOP puts it back into
1274 * little endian mode.
1275 */
1276 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
1277
1278 /* Resume normal operation and reset AREG to CSR0 */
1279 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
1280 }
1281
1282
1283 /* This is needed for old RieblCards and possible for new RieblCards */
1284
1285 static int lance_set_mac_address( struct net_device *dev, void *addr )
1286
1287 { struct lance_private *lp = (struct lance_private *)dev->priv;
1288 struct sockaddr *saddr = addr;
1289 int i;
1290
1291 if (lp->cardtype != OLD_RIEBL && lp->cardtype != NEW_RIEBL)
1292 return( -EOPNOTSUPP );
1293
1294 if (dev->start) {
1295 /* Only possible while card isn't started */
1296 DPRINTK( 1, ( "%s: hwaddr can be set only while card isn't open.\n",
1297 dev->name ));
1298 return( -EIO );
1299 }
1300
1301 slow_memcpy( dev->dev_addr, saddr->sa_data, dev->addr_len );
1302
1303 {
1304 unsigned char hwaddr[6];
1305 for( i = 0; i < 6; i++ )
1306 hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
1307 slow_memcpy(MEM->init.hwaddr, hwaddr, sizeof(hwaddr));
1308 }
1309
1310 lp->memcpy_f( RIEBL_HWADDR_ADDR, dev->dev_addr, 6 );
1311 /* set also the magic for future sessions */
1312 #ifdef NORMAL_MEM_ACCESS
1313 *RIEBL_MAGIC_ADDR = RIEBL_MAGIC;
1314 #else
1315 {
1316 unsigned long magic = RIEBL_MAGIC;
1317 slow_memcpy(RIEBL_MAGIC_ADDR, &magic, sizeof(*RIEBL_MAGIC_ADDR));
1318 }
1319 #endif
1320 return( 0 );
1321 }
1322
1323
1324 #ifdef MODULE
1325 static struct net_device bagetlance_dev;
1326
1327 int init_module(void)
1328
1329 { int err;
1330
1331 bagetlance_dev.init = bagetlance_probe;
1332 if ((err = register_netdev( &bagetlance_dev ))) {
1333 if (err == -EIO) {
1334 printk( "No Vme Lance board found. Module not loaded.\n");
1335 }
1336 return( err );
1337 }
1338 return( 0 );
1339 }
1340
1341 void cleanup_module(void)
1342
1343 {
1344 unregister_netdev( &bagetlance_dev );
1345 }
1346
1347 #endif /* MODULE */
1348
1349 /*
1350 * Local variables:
1351 * c-indent-level: 4
1352 * tab-width: 4
1353 * End:
1354 */
1355
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