1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22
23 ---------------------------------------------------------------------
24
25 Linux kernel-specific changes:
26
27 LK1.1.2 (jgarzik):
28 * Merge becker version 1.09 (4/08/2000)
29
30 LK1.1.3:
31 * Major bugfix to 1.09 driver (Francis Romieu)
32
33 LK1.1.4 (jgarzik):
34 * Merge becker test version 1.09 (5/29/2000)
35
36 LK1.1.5:
37 * Fix locking (jgarzik)
38 * Limit 83c175 probe to ethernet-class PCI devices (rgooch)
39
40 */
41
42 /* These identify the driver base version and may not be removed. */
43 static const char version[] =
44 "epic100.c:v1.09 5/29/2000 Written by Donald Becker <becker@scyld.com>\n";
45 static const char version2[] =
46 " http://www.scyld.com/network/epic100.html\n";
47 static const char version3[] =
48 " (unofficial 2.4.x kernel port, version 1.1.5, September 7, 2000)\n";
49
50 /* The user-configurable values.
51 These may be modified when a driver module is loaded.*/
52
53 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56
57 /* Used to pass the full-duplex flag, etc. */
58 #define MAX_UNITS 8 /* More are supported, limit only on options */
59 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
60 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
61
62 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
63 Setting to > 1518 effectively disables this feature. */
64 static int rx_copybreak = 0;
65
66 /* Operational parameters that are set at compile time. */
67
68 /* Keep the ring sizes a power of two for operational efficiency.
69 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
70 Making the Tx ring too large decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73 #define TX_RING_SIZE 16
74 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
75 #define RX_RING_SIZE 32
76
77 /* Operational parameters that usually are not changed. */
78 /* Time in jiffies before concluding the transmitter is hung. */
79 #define TX_TIMEOUT (2*HZ)
80
81 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
82
83 /* Bytes transferred to chip before transmission starts. */
84 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
85 #define TX_FIFO_THRESH 256
86 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
87
88 #if !defined(__OPTIMIZE__)
89 #warning You must compile this file with the correct options!
90 #warning See the last lines of the source file.
91 #error You must compile this driver with "-O".
92 #endif
93
94 #include <linux/version.h>
95 #include <linux/module.h>
96 #if LINUX_VERSION_CODE < 0x20300 && defined(MODVERSIONS)
97 #include <linux/modversions.h>
98 #endif
99
100 #include <linux/kernel.h>
101 #include <linux/string.h>
102 #include <linux/timer.h>
103 #include <linux/errno.h>
104 #include <linux/ioport.h>
105 #include <linux/malloc.h>
106 #include <linux/interrupt.h>
107 #include <linux/pci.h>
108 #include <linux/delay.h>
109 #include <linux/netdevice.h>
110 #include <linux/etherdevice.h>
111 #include <linux/skbuff.h>
112 #include <linux/init.h>
113 #include <linux/spinlock.h>
114 #include <asm/bitops.h>
115 #include <asm/io.h>
116
117 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
118 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
119 MODULE_PARM(debug, "i");
120 MODULE_PARM(max_interrupt_work, "i");
121 MODULE_PARM(rx_copybreak, "i");
122 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
123 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
124
125 /*
126 Theory of Operation
127
128 I. Board Compatibility
129
130 This device driver is designed for the SMC "EPIC/100", the SMC
131 single-chip Ethernet controllers for PCI. This chip is used on
132 the SMC EtherPower II boards.
133
134 II. Board-specific settings
135
136 PCI bus devices are configured by the system at boot time, so no jumpers
137 need to be set on the board. The system BIOS will assign the
138 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
139 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
140 interrupt lines.
141
142 III. Driver operation
143
144 IIIa. Ring buffers
145
146 IVb. References
147
148 http://www.smsc.com/main/datasheets/83c171.pdf
149 http://www.smsc.com/main/datasheets/83c175.pdf
150 http://scyld.com/expert/NWay.html
151 http://www.national.com/pf/DP/DP83840A.html
152
153 IVc. Errata
154
155 */
156
157
158 enum pci_id_flags_bits {
159 /* Set PCI command register bits before calling probe1(). */
160 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
161 /* Read and map the single following PCI BAR. */
162 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
163 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
164 };
165
166 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
167
168 #define EPIC_TOTAL_SIZE 0x100
169 #ifdef USE_IO_OPS
170 #define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_IO|PCI_ADDR0
171 #else
172 #define EPIC_IOTYPE PCI_USES_MASTER|PCI_USES_MEM|PCI_ADDR1
173 #endif
174
175 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
176
177 typedef enum {
178 SMSC_83C170_0,
179 SMSC_83C170,
180 SMSC_83C175,
181 } chip_t;
182
183
184 struct epic_chip_info {
185 const char *name;
186 enum pci_id_flags_bits pci_flags;
187 int io_size; /* Needed for I/O region check or ioremap(). */
188 int drv_flags; /* Driver use, intended as capability flags. */
189 };
190
191
192 /* indexed by chip_t */
193 static struct epic_chip_info epic_chip_info[] __devinitdata = {
194 { "SMSC EPIC/100 83c170",
195 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },
196 { "SMSC EPIC/100 83c170",
197 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR },
198 { "SMSC EPIC/C 83c175",
199 EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | MII_PWRDWN },
200 };
201
202
203 static struct pci_device_id epic_pci_tbl[] __devinitdata = {
204 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
205 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
206 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
207 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
208 { 0,}
209 };
210 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
211
212
213 #ifndef USE_IO_OPS
214 #undef inb
215 #undef inw
216 #undef inl
217 #undef outb
218 #undef outw
219 #undef outl
220 #define inb readb
221 #define inw readw
222 #define inl readl
223 #define outb writeb
224 #define outw writew
225 #define outl writel
226 #endif
227
228 /* Offsets to registers, using the (ugh) SMC names. */
229 enum epic_registers {
230 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
231 PCIBurstCnt=0x18,
232 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
233 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
234 LAN0=64, /* MAC address. */
235 MC0=80, /* Multicast filter table. */
236 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
237 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
238 };
239
240 /* Interrupt register bits, using my own meaningful names. */
241 enum IntrStatus {
242 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
243 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
244 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
245 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
246 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
247 };
248 enum CommandBits {
249 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
250 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
251 };
252
253 static u16 media2miictl[16] = {
254 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
255 0, 0, 0, 0, 0, 0, 0, 0 };
256
257 /* The EPIC100 Rx and Tx buffer descriptors. */
258
259 struct epic_tx_desc {
260 u32 txstatus;
261 u32 bufaddr;
262 u32 buflength;
263 u32 next;
264 };
265
266 struct epic_rx_desc {
267 u32 rxstatus;
268 u32 bufaddr;
269 u32 buflength;
270 u32 next;
271 };
272
273 enum desc_status_bits {
274 DescOwn=0x8000,
275 };
276
277
278 struct epic_private {
279 /* Tx and Rx rings first so that they remain paragraph aligned. */
280 struct epic_rx_desc rx_ring[RX_RING_SIZE];
281 struct epic_tx_desc tx_ring[TX_RING_SIZE];
282 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
283 struct sk_buff* tx_skbuff[TX_RING_SIZE];
284 /* The addresses of receive-in-place skbuffs. */
285 struct sk_buff* rx_skbuff[RX_RING_SIZE];
286
287 /* Ring pointers. */
288 spinlock_t lock; /* Group with Tx control cache line. */
289 unsigned int cur_tx, dirty_tx;
290 struct descriptor *last_tx_desc;
291
292 unsigned int cur_rx, dirty_rx;
293 unsigned int rx_buf_sz; /* Based on MTU+slack. */
294 struct descriptor *last_rx_desc;
295 long last_rx_time; /* Last Rx, in jiffies. */
296
297 struct pci_dev *pci_dev; /* PCI bus location. */
298 int chip_flags;
299
300 struct net_device_stats stats;
301 struct timer_list timer; /* Media selection timer. */
302 int tx_threshold;
303 unsigned char mc_filter[8];
304 signed char phys[4]; /* MII device addresses. */
305 u16 advertising; /* NWay media advertisement */
306 int mii_phy_cnt;
307 unsigned int tx_full:1; /* The Tx queue is full. */
308 unsigned int full_duplex:1; /* Current duplex setting. */
309 unsigned int force_fd:1; /* Full-duplex operation requested. */
310 unsigned int default_port:4; /* Last dev->if_port value. */
311 unsigned int media2:4; /* Secondary monitored media port. */
312 unsigned int medialock:1; /* Don't sense media type. */
313 unsigned int mediasense:1; /* Media sensing in progress. */
314 };
315
316 static int epic_open(struct net_device *dev);
317 static int read_eeprom(long ioaddr, int location);
318 static int mdio_read(long ioaddr, int phy_id, int location);
319 static void mdio_write(long ioaddr, int phy_id, int location, int value);
320 static void epic_restart(struct net_device *dev);
321 static void epic_timer(unsigned long data);
322 static void epic_tx_timeout(struct net_device *dev);
323 static void epic_init_ring(struct net_device *dev);
324 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
325 static int epic_rx(struct net_device *dev);
326 static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
327 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
328 static int epic_close(struct net_device *dev);
329 static struct net_device_stats *epic_get_stats(struct net_device *dev);
330 static void set_rx_mode(struct net_device *dev);
331
332
333
334 static int __devinit epic_init_one (struct pci_dev *pdev,
335 const struct pci_device_id *ent)
336 {
337 static int card_idx = -1;
338 static int printed_version = 0;
339 struct net_device *dev;
340 struct epic_private *ep;
341 int i, option = 0, duplex = 0;
342 struct epic_chip_info *ci = &epic_chip_info[ent->driver_data];
343 long ioaddr;
344 int chip_idx = (int) ent->driver_data;
345
346 card_idx++;
347
348 if (!printed_version++)
349 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
350 version, version2, version3);
351
352 if ((pci_resource_len(pdev, 0) < ci->io_size) ||
353 (pci_resource_len(pdev, 1) < ci->io_size)) {
354 printk (KERN_ERR "card %d: no PCI region space\n", card_idx);
355 return -ENODEV;
356 }
357
358 i = pci_enable_device(pdev);
359 if (i)
360 return i;
361
362 pci_set_master(pdev);
363
364 dev = init_etherdev(NULL, sizeof (*ep));
365 if (!dev) {
366 printk (KERN_ERR "card %d: no memory for eth device\n", card_idx);
367 return -ENOMEM;
368 }
369
370 /* request 100% of both regions 0 and 1, just to make
371 * sure noone else steals our regions while we are talking
372 * to them */
373 if (!request_region (pci_resource_start (pdev, 0),
374 pci_resource_len (pdev, 0), dev->name)) {
375 printk (KERN_ERR "epic100 %d: I/O region busy\n", card_idx);
376 goto err_out_free_netdev;
377 }
378 if (!request_mem_region (pci_resource_start (pdev, 1),
379 pci_resource_len (pdev, 1), dev->name)) {
380 printk (KERN_ERR "epic100 %d: I/O region busy\n", card_idx);
381 goto err_out_free_pio;
382 }
383
384 #ifdef USE_IO_OPS
385 ioaddr = pci_resource_start (pdev, 0);
386 #else
387 ioaddr = pci_resource_start (pdev, 1);
388 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
389 if (!ioaddr) {
390 printk (KERN_ERR "epic100 %d: ioremap failed\n", card_idx);
391 goto err_out_free_mmio;
392 }
393 #endif
394
395 if (dev->mem_start) {
396 option = dev->mem_start;
397 duplex = (dev->mem_start & 16) ? 1 : 0;
398 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
399 if (options[card_idx] >= 0)
400 option = options[card_idx];
401 if (full_duplex[card_idx] >= 0)
402 duplex = full_duplex[card_idx];
403 }
404
405 pdev->driver_data = dev;
406
407 dev->base_addr = ioaddr;
408 dev->irq = pdev->irq;
409
410 ep = dev->priv;
411 ep->pci_dev = pdev;
412 ep->chip_flags = ci->drv_flags;
413 spin_lock_init (&ep->lock);
414
415 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
416 dev->name, ci->name, ioaddr, dev->irq);
417
418 /* Bring the chip out of low-power mode. */
419 outl(0x4200, ioaddr + GENCTL);
420 /* Magic?! If we don't set this bit the MII interface won't work. */
421 outl(0x0008, ioaddr + TEST1);
422
423 /* Turn on the MII transceiver. */
424 outl(0x12, ioaddr + MIICfg);
425 if (chip_idx == 1)
426 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
427 outl(0x0200, ioaddr + GENCTL);
428
429 /* This could also be read from the EEPROM. */
430 for (i = 0; i < 3; i++)
431 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
432
433 for (i = 0; i < 5; i++)
434 printk("%2.2x:", dev->dev_addr[i]);
435 printk("%2.2x.\n", dev->dev_addr[i]);
436
437 if (debug > 2) {
438 printk(KERN_DEBUG "%s: EEPROM contents\n", dev->name);
439 for (i = 0; i < 64; i++)
440 printk(" %4.4x%s", read_eeprom(ioaddr, i),
441 i % 16 == 15 ? "\n" : "");
442 }
443
444 /* Find the connected MII xcvrs.
445 Doing this in open() would allow detecting external xcvrs later, but
446 takes much time and no cards have external MII. */
447 {
448 int phy, phy_idx = 0;
449 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
450 int mii_status = mdio_read(ioaddr, phy, 1);
451 if (mii_status != 0xffff && mii_status != 0x0000) {
452 ep->phys[phy_idx++] = phy;
453 printk(KERN_INFO "%s: MII transceiver #%d control "
454 "%4.4x status %4.4x.\n",
455 dev->name, phy, mdio_read(ioaddr, phy, 0), mii_status);
456 }
457 }
458 ep->mii_phy_cnt = phy_idx;
459 if (phy_idx != 0) {
460 phy = ep->phys[0];
461 ep->advertising = mdio_read(ioaddr, phy, 4);
462 printk( KERN_INFO "%s: Autonegotiation advertising %4.4x link "
463 "partner %4.4x.\n",
464 dev->name, ep->advertising, mdio_read(ioaddr, phy, 5));
465 } else if ( ! (ep->chip_flags & NO_MII)) {
466 printk(KERN_WARNING "%s: ***WARNING***: No MII transceiver found!\n",
467 dev->name);
468 /* Use the known PHY address of the EPII. */
469 ep->phys[0] = 3;
470 }
471 }
472
473 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
474 if (ep->chip_flags & MII_PWRDWN)
475 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
476 outl(0x0008, ioaddr + GENCTL);
477
478 /* The lower four bits are the media type. */
479 ep->force_fd = duplex;
480 dev->if_port = ep->default_port = option;
481 if (ep->default_port)
482 ep->medialock = 1;
483
484 /* The Epic-specific entries in the device structure. */
485 dev->open = &epic_open;
486 dev->hard_start_xmit = &epic_start_xmit;
487 dev->stop = &epic_close;
488 dev->get_stats = &epic_get_stats;
489 dev->set_multicast_list = &set_rx_mode;
490 dev->do_ioctl = &mii_ioctl;
491 dev->watchdog_timeo = TX_TIMEOUT;
492 dev->tx_timeout = &epic_tx_timeout;
493
494 return 0;
495
496 #ifndef USE_IO_OPS
497 err_out_free_mmio:
498 release_mem_region (pci_resource_start (pdev, 1),
499 pci_resource_len (pdev, 1));
500 #endif
501 err_out_free_pio:
502 release_region (pci_resource_start (pdev, 0),
503 pci_resource_len (pdev, 0));
504 err_out_free_netdev:
505 unregister_netdev(dev);
506 kfree(dev);
507 return -ENODEV;
508 }
509
510 /* Serial EEPROM section. */
511
512 /* EEPROM_Ctrl bits. */
513 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
514 #define EE_CS 0x02 /* EEPROM chip select. */
515 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
516 #define EE_WRITE_0 0x01
517 #define EE_WRITE_1 0x09
518 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
519 #define EE_ENB (0x0001 | EE_CS)
520
521 /* Delay between EEPROM clock transitions.
522 No extra delay is needed with 33Mhz PCI, but 66Mhz is untested.
523 */
524
525 #define eeprom_delay() inl(ee_addr)
526
527 /* The EEPROM commands include the alway-set leading bit. */
528 #define EE_WRITE_CMD (5 << 6)
529 #define EE_READ64_CMD (6 << 6)
530 #define EE_READ256_CMD (6 << 8)
531 #define EE_ERASE_CMD (7 << 6)
532
533 static int read_eeprom(long ioaddr, int location)
534 {
535 int i;
536 int retval = 0;
537 long ee_addr = ioaddr + EECTL;
538 int read_cmd = location |
539 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
540
541 outl(EE_ENB & ~EE_CS, ee_addr);
542 outl(EE_ENB, ee_addr);
543
544 /* Shift the read command bits out. */
545 for (i = 12; i >= 0; i--) {
546 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
547 outl(EE_ENB | dataval, ee_addr);
548 eeprom_delay();
549 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
550 eeprom_delay();
551 }
552 outl(EE_ENB, ee_addr);
553
554 for (i = 16; i > 0; i--) {
555 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
556 eeprom_delay();
557 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
558 outl(EE_ENB, ee_addr);
559 eeprom_delay();
560 }
561
562 /* Terminate the EEPROM access. */
563 outl(EE_ENB & ~EE_CS, ee_addr);
564 return retval;
565 }
566
567 #define MII_READOP 1
568 #define MII_WRITEOP 2
569 static int mdio_read(long ioaddr, int phy_id, int location)
570 {
571 int i;
572
573 outl((phy_id << 9) | (location << 4) | MII_READOP, ioaddr + MIICtrl);
574 /* Typical operation takes < 50 ticks. */
575 for (i = 4000; i > 0; i--)
576 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0)
577 return inw(ioaddr + MIIData);
578 return 0xffff;
579 }
580
581 static void mdio_write(long ioaddr, int phy_id, int location, int value)
582 {
583 int i;
584
585 outw(value, ioaddr + MIIData);
586 outl((phy_id << 9) | (location << 4) | MII_WRITEOP, ioaddr + MIICtrl);
587 for (i = 10000; i > 0; i--) {
588 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
589 break;
590 }
591 return;
592 }
593
594
595 static int epic_open(struct net_device *dev)
596 {
597 struct epic_private *ep = (struct epic_private *)dev->priv;
598 long ioaddr = dev->base_addr;
599 int i;
600 int retval;
601
602 ep->full_duplex = ep->force_fd;
603
604 /* Soft reset the chip. */
605 outl(0x4001, ioaddr + GENCTL);
606
607 MOD_INC_USE_COUNT;
608
609 if ((retval = request_irq(dev->irq, &epic_interrupt, SA_SHIRQ, dev->name, dev))) {
610 MOD_DEC_USE_COUNT;
611 return retval;
612 }
613
614 epic_init_ring(dev);
615
616 outl(0x4000, ioaddr + GENCTL);
617 /* This next magic! line by Ken Yamaguchi.. ?? */
618 outl(0x0008, ioaddr + TEST1);
619
620 /* Pull the chip out of low-power mode, enable interrupts, and set for
621 PCI read multiple. The MIIcfg setting and strange write order are
622 required by the details of which bits are reset and the transceiver
623 wiring on the Ositech CardBus card.
624 */
625 outl(0x12, ioaddr + MIICfg);
626 if (ep->chip_flags & MII_PWRDWN)
627 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
628
629 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
630 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
631 inl(ioaddr + GENCTL);
632 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
633 #else
634 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
635 inl(ioaddr + GENCTL);
636 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
637 #endif
638
639 for (i = 0; i < 3; i++)
640 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
641
642 ep->tx_threshold = TX_FIFO_THRESH;
643 outl(ep->tx_threshold, ioaddr + TxThresh);
644
645 if (media2miictl[dev->if_port & 15]) {
646 if (ep->mii_phy_cnt)
647 mdio_write(ioaddr, ep->phys[0], 0, media2miictl[dev->if_port&15]);
648 if (dev->if_port == 1) {
649 if (debug > 1)
650 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
651 "status %4.4x.\n",
652 dev->name, mdio_read(ioaddr, ep->phys[0], 1));
653 outl(0x13, ioaddr + MIICfg);
654 }
655 } else {
656 int mii_reg5 = mdio_read(ioaddr, ep->phys[0], 5);
657 if (mii_reg5 != 0xffff) {
658 if ((mii_reg5 & 0x0100) || (mii_reg5 & 0x01C0) == 0x0040)
659 ep->full_duplex = 1;
660 else if (! (mii_reg5 & 0x4000))
661 mdio_write(ioaddr, ep->phys[0], 0, 0x1200);
662 if (debug > 1)
663 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
664 " register read of %4.4x.\n", dev->name,
665 ep->full_duplex ? "full" : "half",
666 ep->phys[0], mii_reg5);
667 }
668 }
669
670 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
671 outl(virt_to_bus(ep->rx_ring), ioaddr + PRxCDAR);
672 outl(virt_to_bus(ep->tx_ring), ioaddr + PTxCDAR);
673
674 /* Start the chip's Rx process. */
675 set_rx_mode(dev);
676 outl(StartRx | RxQueued, ioaddr + COMMAND);
677
678 netif_start_queue(dev);
679
680 /* Enable interrupts by setting the interrupt mask. */
681 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
682 | CntFull | TxUnderrun | TxDone | TxEmpty
683 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
684 ioaddr + INTMASK);
685
686 if (debug > 1)
687 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
688 "%s-duplex.\n",
689 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
690 ep->full_duplex ? "full" : "half");
691
692 /* Set the timer to switch to check for link beat and perhaps switch
693 to an alternate media type. */
694 init_timer(&ep->timer);
695 ep->timer.expires = jiffies + 3*HZ;
696 ep->timer.data = (unsigned long)dev;
697 ep->timer.function = &epic_timer; /* timer handler */
698 add_timer(&ep->timer);
699
700 return 0;
701 }
702
703 /* Reset the chip to recover from a PCI transaction error.
704 This may occur at interrupt time. */
705 static void epic_pause(struct net_device *dev)
706 {
707 long ioaddr = dev->base_addr;
708 struct epic_private *ep = (struct epic_private *)dev->priv;
709
710 netif_stop_queue (dev);
711
712 /* Disable interrupts by clearing the interrupt mask. */
713 outl(0x00000000, ioaddr + INTMASK);
714 /* Stop the chip's Tx and Rx DMA processes. */
715 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
716
717 /* Update the error counts. */
718 if (inw(ioaddr + COMMAND) != 0xffff) {
719 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
720 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
721 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
722 }
723
724 /* Remove the packets on the Rx queue. */
725 epic_rx(dev);
726 }
727
728 static void epic_restart(struct net_device *dev)
729 {
730 long ioaddr = dev->base_addr;
731 struct epic_private *ep = (struct epic_private *)dev->priv;
732 int i;
733
734 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
735 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
736 /* Soft reset the chip. */
737 outl(0x0001, ioaddr + GENCTL);
738
739 udelay(1);
740 /* Duplicate code from epic_open(). */
741 outl(0x0008, ioaddr + TEST1);
742
743 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
744 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
745 #else
746 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
747 #endif
748 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
749 if (ep->chip_flags & MII_PWRDWN)
750 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
751
752 for (i = 0; i < 3; i++)
753 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
754
755 ep->tx_threshold = TX_FIFO_THRESH;
756 outl(ep->tx_threshold, ioaddr + TxThresh);
757 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
758 outl(virt_to_bus(&ep->rx_ring[ep->cur_rx%RX_RING_SIZE]), ioaddr + PRxCDAR);
759 outl(virt_to_bus(&ep->tx_ring[ep->dirty_tx%TX_RING_SIZE]),
760 ioaddr + PTxCDAR);
761
762 /* Start the chip's Rx process. */
763 set_rx_mode(dev);
764 outl(StartRx | RxQueued, ioaddr + COMMAND);
765
766 /* Enable interrupts by setting the interrupt mask. */
767 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
768 | CntFull | TxUnderrun | TxDone | TxEmpty
769 | RxError | RxOverflow | RxFull | RxHeader | RxDone,
770 ioaddr + INTMASK);
771 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
772 " interrupt %4.4x.\n",
773 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
774 (int)inl(ioaddr + INTSTAT));
775 return;
776 }
777
778 static void epic_timer(unsigned long data)
779 {
780 struct net_device *dev = (struct net_device *)data;
781 struct epic_private *ep = (struct epic_private *)dev->priv;
782 long ioaddr = dev->base_addr;
783 int next_tick = 60*HZ;
784 int mii_reg5 = ep->mii_phy_cnt ? mdio_read(ioaddr, ep->phys[0], 5) : 0;
785 int negotiated = mii_reg5 & ep->advertising;
786 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
787
788 if (debug > 3) {
789 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
790 dev->name, (int)inl(ioaddr + TxSTAT));
791 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
792 "IntStatus %4.4x RxStatus %4.4x.\n",
793 dev->name, (int)inl(ioaddr + INTMASK),
794 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
795 }
796
797 if (! ep->force_fd) {
798 if (ep->full_duplex != duplex) {
799 ep->full_duplex = duplex;
800 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
801 " partner capability of %4.4x.\n", dev->name,
802 ep->full_duplex ? "full" : "half", ep->phys[0], mii_reg5);
803 outl(ep->full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
804 }
805 }
806
807 ep->timer.expires = jiffies + next_tick;
808 add_timer(&ep->timer);
809 }
810
811 static void epic_tx_timeout(struct net_device *dev)
812 {
813 struct epic_private *ep = (struct epic_private *)dev->priv;
814 long ioaddr = dev->base_addr;
815
816 if (debug > 0) {
817 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
818 "Tx status %4.4x.\n",
819 dev->name, (int)inw(ioaddr + TxSTAT));
820 if (debug > 1) {
821 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
822 dev->name, ep->dirty_tx, ep->cur_tx);
823 }
824 }
825 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
826 ep->stats.tx_fifo_errors++;
827 outl(RestartTx, ioaddr + COMMAND);
828 } else {
829 epic_restart(dev);
830 outl(TxQueued, dev->base_addr + COMMAND);
831 }
832
833 dev->trans_start = jiffies;
834 ep->stats.tx_errors++;
835 return;
836 }
837
838 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
839 static void epic_init_ring(struct net_device *dev)
840 {
841 struct epic_private *ep = (struct epic_private *)dev->priv;
842 int i;
843
844 ep->tx_full = 0;
845 ep->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
846 ep->dirty_tx = ep->cur_tx = 0;
847 ep->cur_rx = ep->dirty_rx = 0;
848 ep->last_rx_time = jiffies;
849 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
850
851 /* Initialize all Rx descriptors. */
852 for (i = 0; i < RX_RING_SIZE; i++) {
853 ep->rx_ring[i].rxstatus = 0;
854 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
855 ep->rx_ring[i].next = virt_to_le32desc(&ep->rx_ring[i+1]);
856 ep->rx_skbuff[i] = 0;
857 }
858 /* Mark the last entry as wrapping the ring. */
859 ep->rx_ring[i-1].next = virt_to_le32desc(&ep->rx_ring[0]);
860
861 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
862 for (i = 0; i < RX_RING_SIZE; i++) {
863 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
864 ep->rx_skbuff[i] = skb;
865 if (skb == NULL)
866 break;
867 skb->dev = dev; /* Mark as being used by this device. */
868 skb_reserve(skb, 2); /* 16 byte align the IP header. */
869 ep->rx_ring[i].bufaddr = virt_to_le32desc(skb->tail);
870 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
871 }
872 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
873
874 /* The Tx buffer descriptor is filled in as needed, but we
875 do need to clear the ownership bit. */
876 for (i = 0; i < TX_RING_SIZE; i++) {
877 ep->tx_skbuff[i] = 0;
878 ep->tx_ring[i].txstatus = 0x0000;
879 ep->tx_ring[i].next = virt_to_le32desc(&ep->tx_ring[i+1]);
880 }
881 ep->tx_ring[i-1].next = virt_to_le32desc(&ep->tx_ring[0]);
882 return;
883 }
884
885 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
886 {
887 struct epic_private *ep = (struct epic_private *)dev->priv;
888 int entry, free_count;
889 u32 ctrl_word;
890
891 /* Caution: the write order is important here, set the field with the
892 "ownership" bit last. */
893 spin_lock_irq(&ep->lock);
894
895 /* Calculate the next Tx descriptor entry. */
896 free_count = ep->cur_tx - ep->dirty_tx;
897 entry = ep->cur_tx % TX_RING_SIZE;
898
899 ep->tx_skbuff[entry] = skb;
900 ep->tx_ring[entry].bufaddr = virt_to_le32desc(skb->data);
901
902 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
903 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
904 } else if (free_count == TX_QUEUE_LEN/2) {
905 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
906 } else if (free_count < TX_QUEUE_LEN - 1) {
907 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
908 } else {
909 /* Leave room for an additional entry. */
910 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
911 ep->tx_full = 1;
912 }
913 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
914 ep->tx_ring[entry].txstatus =
915 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
916 | cpu_to_le32(DescOwn);
917
918 ep->cur_tx++;
919 if (ep->tx_full)
920 netif_stop_queue(dev);
921
922 spin_unlock_irq(&ep->lock);
923
924 /* Trigger an immediate transmit demand. */
925 outl(TxQueued, dev->base_addr + COMMAND);
926
927 dev->trans_start = jiffies;
928 if (debug > 4)
929 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
930 "flag %2.2x Tx status %8.8x.\n",
931 dev->name, (int)skb->len, entry, ctrl_word,
932 (int)inl(dev->base_addr + TxSTAT));
933
934 return 0;
935 }
936
937 /* The interrupt handler does all of the Rx thread work and cleans up
938 after the Tx thread. */
939 static void epic_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
940 {
941 struct net_device *dev = (struct net_device *)dev_instance;
942 struct epic_private *ep = (struct epic_private *)dev->priv;
943 long ioaddr = dev->base_addr;
944 int status, boguscnt = max_interrupt_work;
945
946 spin_lock(&ep->lock);
947
948 do {
949 status = inl(ioaddr + INTSTAT);
950 /* Acknowledge all of the current interrupt sources ASAP. */
951 outl(status & 0x00007fff, ioaddr + INTSTAT);
952
953 if (debug > 4)
954 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
955 "intstat=%#8.8x.\n",
956 dev->name, status, (int)inl(ioaddr + INTSTAT));
957
958 if ((status & IntrSummary) == 0)
959 break;
960
961 if (status & (RxDone | RxStarted | RxEarlyWarn | RxOverflow))
962 epic_rx(dev);
963
964 if (status & (TxEmpty | TxDone)) {
965 unsigned int dirty_tx, cur_tx;
966
967 /* Note: if this lock becomes a problem we can narrow the locked
968 region at the cost of occasionally grabbing the lock more
969 times. */
970 cur_tx = ep->cur_tx;
971 dirty_tx = ep->dirty_tx;
972 for (; cur_tx - dirty_tx > 0; dirty_tx++) {
973 int entry = dirty_tx % TX_RING_SIZE;
974 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
975
976 if (txstatus & DescOwn)
977 break; /* It still hasn't been Txed */
978
979 if ( ! (txstatus & 0x0001)) {
980 /* There was an major error, log it. */
981 #ifndef final_version
982 if (debug > 1)
983 printk("%s: Transmit error, Tx status %8.8x.\n",
984 dev->name, txstatus);
985 #endif
986 ep->stats.tx_errors++;
987 if (txstatus & 0x1050) ep->stats.tx_aborted_errors++;
988 if (txstatus & 0x0008) ep->stats.tx_carrier_errors++;
989 if (txstatus & 0x0040) ep->stats.tx_window_errors++;
990 if (txstatus & 0x0010) ep->stats.tx_fifo_errors++;
991 #ifdef ETHER_STATS
992 if (txstatus & 0x1000) ep->stats.collisions16++;
993 #endif
994 } else {
995 #ifdef ETHER_STATS
996 if ((txstatus & 0x0002) != 0) ep->stats.tx_deferred++;
997 #endif
998 ep->stats.collisions += (txstatus >> 8) & 15;
999 ep->stats.tx_packets++;
1000 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1001 }
1002
1003 /* Free the original skb. */
1004 dev_kfree_skb_irq(ep->tx_skbuff[entry]);
1005 ep->tx_skbuff[entry] = 0;
1006 }
1007
1008 #ifndef final_version
1009 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1010 printk("%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1011 dev->name, dirty_tx, cur_tx, ep->tx_full);
1012 dirty_tx += TX_RING_SIZE;
1013 }
1014 #endif
1015 ep->dirty_tx = dirty_tx;
1016 if (ep->tx_full
1017 && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1018 /* The ring is no longer full, clear tbusy. */
1019 ep->tx_full = 0;
1020 netif_wake_queue(dev);
1021 }
1022 }
1023
1024 /* Check uncommon events all at once. */
1025 if (status & (CntFull | TxUnderrun | RxOverflow | RxFull |
1026 PCIBusErr170 | PCIBusErr175)) {
1027 if (status == 0xffffffff) /* Chip failed or removed (CardBus). */
1028 break;
1029 /* Always update the error counts to avoid overhead later. */
1030 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1031 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1032 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1033
1034 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1035 ep->stats.tx_fifo_errors++;
1036 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1037 /* Restart the transmit process. */
1038 outl(RestartTx, ioaddr + COMMAND);
1039 }
1040 if (status & RxOverflow) { /* Missed a Rx frame. */
1041 ep->stats.rx_errors++;
1042 }
1043 if (status & (RxOverflow | RxFull))
1044 outw(RxQueued, ioaddr + COMMAND);
1045 if (status & PCIBusErr170) {
1046 printk(KERN_ERR "%s: PCI Bus Error! EPIC status %4.4x.\n",
1047 dev->name, status);
1048 epic_pause(dev);
1049 epic_restart(dev);
1050 }
1051 /* Clear all error sources. */
1052 outl(status & 0x7f18, ioaddr + INTSTAT);
1053 }
1054 if (--boguscnt < 0) {
1055 printk(KERN_ERR "%s: Too much work at interrupt, "
1056 "IntrStatus=0x%8.8x.\n",
1057 dev->name, status);
1058 /* Clear all interrupt sources. */
1059 outl(0x0001ffff, ioaddr + INTSTAT);
1060 break;
1061 }
1062 } while (1);
1063
1064 if (debug > 3)
1065 printk(KERN_DEBUG "%s: exiting interrupt, intr_status=%#4.4x.\n",
1066 dev->name, status);
1067
1068 spin_unlock(&ep->lock);
1069 }
1070
1071 static int epic_rx(struct net_device *dev)
1072 {
1073 struct epic_private *ep = (struct epic_private *)dev->priv;
1074 int entry = ep->cur_rx % RX_RING_SIZE;
1075 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1076 int work_done = 0;
1077
1078 if (debug > 4)
1079 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1080 ep->rx_ring[entry].rxstatus);
1081 /* If we own the next entry, it's a new packet. Send it up. */
1082 while (!(le32_to_cpu(ep->rx_ring[entry].rxstatus) & DescOwn)) {
1083 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1084
1085 if (debug > 4)
1086 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1087 if (--rx_work_limit < 0)
1088 break;
1089 if (status & 0x2006) {
1090 if (debug > 2)
1091 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1092 dev->name, status);
1093 if (status & 0x2000) {
1094 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1095 "multiple buffers, status %4.4x!\n", dev->name, status);
1096 ep->stats.rx_length_errors++;
1097 } else if (status & 0x0006)
1098 /* Rx Frame errors are counted in hardware. */
1099 ep->stats.rx_errors++;
1100 } else {
1101 /* Malloc up new buffer, compatible with net-2e. */
1102 /* Omit the four octet CRC from the length. */
1103 short pkt_len = (status >> 16) - 4;
1104 struct sk_buff *skb;
1105
1106 if (pkt_len > PKT_BUF_SZ - 4) {
1107 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1108 "%d bytes.\n",
1109 dev->name, pkt_len, status);
1110 pkt_len = 1514;
1111 }
1112 /* Check if the packet is long enough to accept without copying
1113 to a minimally-sized skbuff. */
1114 if (pkt_len < rx_copybreak
1115 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1116 skb->dev = dev;
1117 skb_reserve(skb, 2); /* 16 byte align the IP header */
1118 #if 1 /* HAS_IP_COPYSUM */
1119 eth_copy_and_sum(skb, ep->rx_skbuff[entry]->tail, pkt_len, 0);
1120 skb_put(skb, pkt_len);
1121 #else
1122 memcpy(skb_put(skb, pkt_len), ep->rx_skbuff[entry]->tail,
1123 pkt_len);
1124 #endif
1125 } else {
1126 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1127 ep->rx_skbuff[entry] = NULL;
1128 }
1129 skb->protocol = eth_type_trans(skb, dev);
1130 netif_rx(skb);
1131 ep->stats.rx_packets++;
1132 ep->stats.rx_bytes += pkt_len;
1133 }
1134 work_done++;
1135 entry = (++ep->cur_rx) % RX_RING_SIZE;
1136 }
1137
1138 /* Refill the Rx ring buffers. */
1139 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1140 entry = ep->dirty_rx % RX_RING_SIZE;
1141 if (ep->rx_skbuff[entry] == NULL) {
1142 struct sk_buff *skb;
1143 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1144 if (skb == NULL)
1145 break;
1146 skb->dev = dev; /* Mark as being used by this device. */
1147 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1148 ep->rx_ring[entry].bufaddr = virt_to_le32desc(skb->tail);
1149 work_done++;
1150 }
1151 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1152 }
1153 return work_done;
1154 }
1155
1156 static int epic_close(struct net_device *dev)
1157 {
1158 long ioaddr = dev->base_addr;
1159 struct epic_private *ep = (struct epic_private *)dev->priv;
1160 int i;
1161
1162 netif_stop_queue(dev);
1163
1164 if (debug > 1)
1165 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1166 dev->name, (int)inl(ioaddr + INTSTAT));
1167
1168 del_timer_sync(&ep->timer);
1169 epic_pause(dev);
1170 free_irq(dev->irq, dev);
1171
1172 /* Free all the skbuffs in the Rx queue. */
1173 for (i = 0; i < RX_RING_SIZE; i++) {
1174 struct sk_buff *skb = ep->rx_skbuff[i];
1175 ep->rx_skbuff[i] = 0;
1176 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1177 ep->rx_ring[i].buflength = 0;
1178 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1179 if (skb) {
1180 dev_kfree_skb(skb);
1181 }
1182 }
1183 for (i = 0; i < TX_RING_SIZE; i++) {
1184 if (ep->tx_skbuff[i])
1185 dev_kfree_skb(ep->tx_skbuff[i]);
1186 ep->tx_skbuff[i] = 0;
1187 }
1188
1189 /* Green! Leave the chip in low-power mode. */
1190 outl(0x0008, ioaddr + GENCTL);
1191
1192 MOD_DEC_USE_COUNT;
1193 return 0;
1194 }
1195
1196 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1197 {
1198 struct epic_private *ep = (struct epic_private *)dev->priv;
1199 long ioaddr = dev->base_addr;
1200
1201 if (netif_running(dev)) {
1202 /* Update the error counts. */
1203 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1204 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1205 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1206 }
1207
1208 return &ep->stats;
1209 }
1210
1211 /* Set or clear the multicast filter for this adaptor.
1212 Note that we only use exclusion around actually queueing the
1213 new frame, not around filling ep->setup_frame. This is non-deterministic
1214 when re-entered but still correct. */
1215
1216 /* The little-endian AUTODIN II ethernet CRC calculation.
1217 N.B. Do not use for bulk data, use a table-based routine instead.
1218 This is common code and should be moved to net/core/crc.c */
1219 static unsigned const ethernet_polynomial_le = 0xedb88320U;
1220 static inline unsigned ether_crc_le(int length, unsigned char *data)
1221 {
1222 unsigned int crc = 0xffffffff; /* Initial value. */
1223 while(--length >= 0) {
1224 unsigned char current_octet = *data++;
1225 int bit;
1226 for (bit = 8; --bit >= 0; current_octet >>= 1) {
1227 if ((crc ^ current_octet) & 1) {
1228 crc >>= 1;
1229 crc ^= ethernet_polynomial_le;
1230 } else
1231 crc >>= 1;
1232 }
1233 }
1234 return crc;
1235 }
1236
1237 static void set_rx_mode(struct net_device *dev)
1238 {
1239 long ioaddr = dev->base_addr;
1240 struct epic_private *ep = (struct epic_private *)dev->priv;
1241 unsigned char mc_filter[8]; /* Multicast hash filter */
1242 int i;
1243
1244 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1245 outl(0x002C, ioaddr + RxCtrl);
1246 /* Unconditionally log net taps. */
1247 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1248 memset(mc_filter, 0xff, sizeof(mc_filter));
1249 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1250 /* There is apparently a chip bug, so the multicast filter
1251 is never enabled. */
1252 /* Too many to filter perfectly -- accept all multicasts. */
1253 memset(mc_filter, 0xff, sizeof(mc_filter));
1254 outl(0x000C, ioaddr + RxCtrl);
1255 } else if (dev->mc_count == 0) {
1256 outl(0x0004, ioaddr + RxCtrl);
1257 return;
1258 } else { /* Never executed, for now. */
1259 struct dev_mc_list *mclist;
1260
1261 memset(mc_filter, 0, sizeof(mc_filter));
1262 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1263 i++, mclist = mclist->next)
1264 set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f,
1265 mc_filter);
1266 }
1267 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1268 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1269 for (i = 0; i < 4; i++)
1270 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1271 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1272 }
1273 return;
1274 }
1275
1276 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1277 {
1278 long ioaddr = dev->base_addr;
1279 u16 *data = (u16 *)&rq->ifr_data;
1280
1281 switch(cmd) {
1282 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1283 data[0] = ((struct epic_private *)dev->priv)->phys[0] & 0x1f;
1284 /* Fall Through */
1285 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1286 if (! netif_running(dev)) {
1287 outl(0x0200, ioaddr + GENCTL);
1288 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1289 }
1290 data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f);
1291 if (! netif_running(dev)) {
1292 #ifdef notdef /* Leave on if the ioctl() is used. */
1293 outl(0x0008, ioaddr + GENCTL);
1294 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1295 #endif
1296 }
1297 return 0;
1298 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1299 if (!capable(CAP_NET_ADMIN))
1300 return -EPERM;
1301 if (! netif_running(dev)) {
1302 outl(0x0200, ioaddr + GENCTL);
1303 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1304 }
1305 mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1306 if (! netif_running(dev)) {
1307 #ifdef notdef /* Leave on if the ioctl() is used. */
1308 outl(0x0008, ioaddr + GENCTL);
1309 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1310 #endif
1311 }
1312 return 0;
1313 default:
1314 return -EOPNOTSUPP;
1315 }
1316 }
1317
1318
1319 static void __devexit epic_remove_one (struct pci_dev *pdev)
1320 {
1321 struct net_device *dev = pdev->driver_data;
1322
1323 unregister_netdev(dev);
1324 #ifndef USE_IO_OPS
1325 iounmap ((void*) dev->base_addr);
1326 #endif
1327 release_mem_region (pci_resource_start (pdev, 1),
1328 pci_resource_len (pdev, 1));
1329 release_region (pci_resource_start (pdev, 0),
1330 pci_resource_len (pdev, 0));
1331 kfree(dev);
1332 }
1333
1334
1335 static void epic_suspend (struct pci_dev *pdev)
1336 {
1337 struct net_device *dev = pdev->driver_data;
1338 long ioaddr = dev->base_addr;
1339
1340 epic_pause(dev);
1341 /* Put the chip into low-power mode. */
1342 outl(0x0008, ioaddr + GENCTL);
1343 }
1344
1345
1346 static void epic_resume (struct pci_dev *pdev)
1347 {
1348 struct net_device *dev = pdev->driver_data;
1349
1350 epic_restart (dev);
1351 }
1352
1353
1354 static struct pci_driver epic_driver = {
1355 name: "epic100",
1356 id_table: epic_pci_tbl,
1357 probe: epic_init_one,
1358 remove: epic_remove_one,
1359 suspend: epic_suspend,
1360 resume: epic_resume,
1361 };
1362
1363
1364 static int __init epic_init (void)
1365 {
1366 return pci_module_init (&epic_driver);
1367 }
1368
1369
1370 static void __exit epic_cleanup (void)
1371 {
1372 pci_unregister_driver (&epic_driver);
1373 }
1374
1375
1376 module_init(epic_init);
1377 module_exit(epic_cleanup);
1378
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