1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
7 *
8 * Copyright (C) 1999, 2000 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000 by Silicon Graphics, Inc.
10 *
11 * Reporting bugs:
12 *
13 * If you find problems with this drivers, then if possible do the
14 * following. Hook up a terminal to the MSC port, send an NMI to the CPUs
15 * by typing ^Tnmi (where ^T stands for <CTRL>-T). You'll see something
16 * like:
17 * 1A 000:
18 * 1A 000: *** NMI while in Kernel and no NMI vector installed on node 0
19 * 1A 000: *** Error EPC: 0xffffffff800265e4 (0xffffffff800265e4)
20 * 1A 000: *** Press ENTER to continue.
21 *
22 * Next enter the command ``lw i:0x86000f0 0x18'' and include this
23 * commands output which will look like below with your bugreport.
24 *
25 * 1A 000: POD MSC Dex> lw i:0x86000f0 0x18
26 * 1A 000: 92000000086000f0: 0021f28c 00000000 00000000 00000000
27 * 1A 000: 9200000008600100: a5000000 01cde000 00000000 000004e0
28 * 1A 000: 9200000008600110: 00000650 00000000 00110b15 00000000
29 * 1A 000: 9200000008600120: 006d0005 77bbca0a a5000000 01ce0000
30 * 1A 000: 9200000008600130: 80000500 00000500 00002538 05690008
31 * 1A 000: 9200000008600140: 00000000 00000000 000003e1 0000786d
32 *
33 * To do:
34 *
35 * - Handle allocation failures in ioc3_alloc_skb() more gracefully.
36 * - Handle allocation failures in ioc3_init_rings().
37 * - Use prefetching for large packets. What is a good lower limit for
38 * prefetching?
39 * - We're probably allocating a bit too much memory.
40 * - Workarounds for various PHYs.
41 * - Proper autonegotiation.
42 * - What exactly is net_device_stats.tx_dropped supposed to count?
43 * - Use hardware checksums.
44 * - Convert to using the PCI infrastructure / IOC3 meta driver.
45 */
46 #include <linux/init.h>
47 #include <linux/delay.h>
48 #include <linux/kernel.h>
49 #include <linux/mm.h>
50 #include <linux/errno.h>
51 #include <linux/module.h>
52 #include <linux/pci.h>
53
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57
58 #include <asm/byteorder.h>
59 #include <asm/io.h>
60 #include <asm/pgtable.h>
61 #include <asm/sn/types.h>
62 #include <asm/sn/sn0/addrs.h>
63 #include <asm/sn/sn0/hubni.h>
64 #include <asm/sn/sn0/hubio.h>
65 #include <asm/sn/klconfig.h>
66 #include <asm/sn/ioc3.h>
67 #include <asm/sn/sn0/ip27.h>
68 #include <asm/pci/bridge.h>
69
70 /* 32 RX buffers. This is tunable in the range of 16 <= x < 512. */
71 #define RX_BUFFS 64
72
73 /* Private ioctls that de facto are well known and used for examply
74 by mii-tool. */
75 #define SIOCGMIIPHY (SIOCDEVPRIVATE) /* Read from current PHY */
76 #define SIOCGMIIREG (SIOCDEVPRIVATE+1) /* Read any PHY register */
77 #define SIOCSMIIREG (SIOCDEVPRIVATE+2) /* Write any PHY register */
78
79 /* These exist in other drivers; we don't use them at this time. */
80 #define SIOCGPARAMS (SIOCDEVPRIVATE+3) /* Read operational parameters */
81 #define SIOCSPARAMS (SIOCDEVPRIVATE+4) /* Set operational parameters */
82
83 /* Private per NIC data of the driver. */
84 struct ioc3_private {
85 struct ioc3 *regs;
86 int phy;
87 unsigned long *rxr; /* pointer to receiver ring */
88 struct ioc3_etxd *txr;
89 struct sk_buff *rx_skbs[512];
90 struct sk_buff *tx_skbs[128];
91 struct net_device_stats stats;
92 int rx_ci; /* RX consumer index */
93 int rx_pi; /* RX producer index */
94 int tx_ci; /* TX consumer index */
95 int tx_pi; /* TX producer index */
96 int txqlen;
97 u32 emcr, ehar_h, ehar_l;
98 struct timer_list negtimer;
99 spinlock_t ioc3_lock;
100 };
101
102 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
103 static void ioc3_set_multicast_list(struct net_device *dev);
104 static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
105 static void ioc3_timeout(struct net_device *dev);
106 static inline unsigned int ioc3_hash(const unsigned char *addr);
107 static inline void ioc3_stop(struct net_device *dev);
108 static void ioc3_init(struct net_device *dev);
109
110 static const char ioc3_str[] = "IOC3 Ethernet";
111
112 /* We use this to acquire receive skb's that we can DMA directly into. */
113 #define ALIGNED_RX_SKB_ADDR(addr) \
114 ((((unsigned long)(addr) + (128 - 1)) & ~(128 - 1)) - (unsigned long)(addr))
115
116 #define ioc3_alloc_skb(__length, __gfp_flags) \
117 ({ struct sk_buff *__skb; \
118 __skb = alloc_skb((__length) + 128, (__gfp_flags)); \
119 if (__skb) { \
120 int __offset = ALIGNED_RX_SKB_ADDR(__skb->data); \
121 if(__offset) \
122 skb_reserve(__skb, __offset); \
123 } \
124 __skb; \
125 })
126
127 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
128 1644 while it's actually 1664. This one was nasty to track down ... */
129 #define RX_OFFSET 10
130 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + 128)
131
132 /* DMA barrier to separate cached and uncached accesses. */
133 #define BARRIER() \
134 __asm__("sync" ::: "memory")
135
136
137 #define IOC3_SIZE 0x100000
138
139 #define ioc3_r(reg) \
140 ({ \
141 u32 __res; \
142 __res = ioc3->reg; \
143 __res; \
144 })
145
146 #define ioc3_w(reg,val) \
147 do { \
148 (ioc3->reg = (val)); \
149 } while(0)
150
151 static inline u32
152 mcr_pack(u32 pulse, u32 sample)
153 {
154 return (pulse << 10) | (sample << 2);
155 }
156
157 static int
158 nic_wait(struct ioc3 *ioc3)
159 {
160 u32 mcr;
161
162 do {
163 mcr = ioc3_r(mcr);
164 } while (!(mcr & 2));
165
166 return mcr & 1;
167 }
168
169 static int
170 nic_reset(struct ioc3 *ioc3)
171 {
172 int presence;
173
174 ioc3_w(mcr, mcr_pack(500, 65));
175 presence = nic_wait(ioc3);
176
177 ioc3_w(mcr, mcr_pack(0, 500));
178 nic_wait(ioc3);
179
180 return presence;
181 }
182
183 static inline int
184 nic_read_bit(struct ioc3 *ioc3)
185 {
186 int result;
187
188 ioc3_w(mcr, mcr_pack(6, 13));
189 result = nic_wait(ioc3);
190 ioc3_w(mcr, mcr_pack(0, 100));
191 nic_wait(ioc3);
192
193 return result;
194 }
195
196 static inline void
197 nic_write_bit(struct ioc3 *ioc3, int bit)
198 {
199 if (bit)
200 ioc3_w(mcr, mcr_pack(6, 110));
201 else
202 ioc3_w(mcr, mcr_pack(80, 30));
203
204 nic_wait(ioc3);
205 }
206
207 /*
208 * Read a byte from an iButton device
209 */
210 static u32
211 nic_read_byte(struct ioc3 *ioc3)
212 {
213 u32 result = 0;
214 int i;
215
216 for (i = 0; i < 8; i++)
217 result = (result >> 1) | (nic_read_bit(ioc3) << 7);
218
219 return result;
220 }
221
222 /*
223 * Write a byte to an iButton device
224 */
225 static void
226 nic_write_byte(struct ioc3 *ioc3, int byte)
227 {
228 int i, bit;
229
230 for (i = 8; i; i--) {
231 bit = byte & 1;
232 byte >>= 1;
233
234 nic_write_bit(ioc3, bit);
235 }
236 }
237
238 static u64
239 nic_find(struct ioc3 *ioc3, int *last)
240 {
241 int a, b, index, disc;
242 u64 address = 0;
243
244 nic_reset(ioc3);
245 /* Search ROM. */
246 nic_write_byte(ioc3, 0xf0);
247
248 /* Algorithm from ``Book of iButton Standards''. */
249 for (index = 0, disc = 0; index < 64; index++) {
250 a = nic_read_bit(ioc3);
251 b = nic_read_bit(ioc3);
252
253 if (a && b) {
254 printk("NIC search failed (not fatal).\n");
255 *last = 0;
256 return 0;
257 }
258
259 if (!a && !b) {
260 if (index == *last) {
261 address |= 1UL << index;
262 } else if (index > *last) {
263 address &= ~(1UL << index);
264 disc = index;
265 } else if ((address & (1UL << index)) == 0)
266 disc = index;
267 nic_write_bit(ioc3, address & (1UL << index));
268 continue;
269 } else {
270 if (a)
271 address |= 1UL << index;
272 else
273 address &= ~(1UL << index);
274 nic_write_bit(ioc3, a);
275 continue;
276 }
277 }
278
279 *last = disc;
280
281 return address;
282 }
283
284 static int nic_init(struct ioc3 *ioc3)
285 {
286 const char *type;
287 u8 crc;
288 u8 serial[6];
289 int save = 0, i;
290
291 type = "unknown";
292
293 while (1) {
294 u64 reg;
295 reg = nic_find(ioc3, &save);
296
297 switch (reg & 0xff) {
298 case 0x91:
299 type = "DS1981U";
300 break;
301 default:
302 if (save == 0) {
303 /* Let the caller try again. */
304 return -1;
305 }
306 continue;
307 }
308
309 nic_reset(ioc3);
310
311 /* Match ROM. */
312 nic_write_byte(ioc3, 0x55);
313 for (i = 0; i < 8; i++)
314 nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
315
316 reg >>= 8; /* Shift out type. */
317 for (i = 0; i < 6; i++) {
318 serial[i] = reg & 0xff;
319 reg >>= 8;
320 }
321 crc = reg & 0xff;
322 break;
323 }
324
325 printk("Found %s NIC", type);
326 if (type != "unknown") {
327 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
328 " CRC %02x", serial[0], serial[1], serial[2],
329 serial[3], serial[4], serial[5], crc);
330 }
331 printk(".\n");
332
333 return 0;
334 }
335
336 /*
337 * Read the NIC (Number-In-a-Can) device.
338 */
339 static void ioc3_get_eaddr(struct net_device *dev, struct ioc3 *ioc3)
340 {
341 u8 nic[14];
342 int i;
343 int tries = 2; /* There may be some problem with the battery? */
344
345 ioc3_w(gpcr_s, (1 << 21));
346
347 while (tries--) {
348 if (!nic_init(ioc3))
349 break;
350 udelay(500);
351 }
352
353 if (tries < 0) {
354 printk("Failed to read MAC address\n");
355 return;
356 }
357
358 /* Read Memory. */
359 nic_write_byte(ioc3, 0xf0);
360 nic_write_byte(ioc3, 0x00);
361 nic_write_byte(ioc3, 0x00);
362
363 for (i = 13; i >= 0; i--)
364 nic[i] = nic_read_byte(ioc3);
365
366 printk("Ethernet address is ");
367 for (i = 2; i < 8; i++) {
368 dev->dev_addr[i - 2] = nic[i];
369 printk("%02x", nic[i]);
370 if (i < 7)
371 printk(":");
372 }
373 printk(".\n");
374 }
375
376 /* Caller must hold the ioc3_lock ever for MII readers. This is also
377 used to protect the transmitter side but it's low contention. */
378 static u16 mii_read(struct ioc3 *ioc3, int phy, int reg)
379 {
380 while (ioc3->micr & MICR_BUSY);
381 ioc3->micr = (phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG;
382 while (ioc3->micr & MICR_BUSY);
383
384 return ioc3->midr_r & MIDR_DATA_MASK;
385 }
386
387 static void mii_write(struct ioc3 *ioc3, int phy, int reg, u16 data)
388 {
389 while (ioc3->micr & MICR_BUSY);
390 ioc3->midr_w = data;
391 ioc3->micr = (phy << MICR_PHYADDR_SHIFT) | reg;
392 while (ioc3->micr & MICR_BUSY);
393 }
394
395 static int ioc3_mii_init(struct net_device *dev, struct ioc3_private *ip,
396 struct ioc3 *ioc3);
397
398 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
399 {
400 struct ioc3_private *ip = (struct ioc3_private *) dev->priv;
401 struct ioc3 *ioc3 = ip->regs;
402
403 ip->stats.collisions += (ioc3->etcdc & ETCDC_COLLCNT_MASK);
404 return &ip->stats;
405 }
406
407 static inline void
408 ioc3_rx(struct net_device *dev, struct ioc3_private *ip, struct ioc3 *ioc3)
409 {
410 struct sk_buff *skb, *new_skb;
411 int rx_entry, n_entry, len;
412 struct ioc3_erxbuf *rxb;
413 unsigned long *rxr;
414 u32 w0, err;
415
416 rxr = (unsigned long *) ip->rxr; /* Ring base */
417 rx_entry = ip->rx_ci; /* RX consume index */
418 n_entry = ip->rx_pi;
419
420 skb = ip->rx_skbs[rx_entry];
421 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
422 w0 = rxb->w0;
423
424 while (w0 & ERXBUF_V) {
425 err = rxb->err; /* It's valid ... */
426 if (err & ERXBUF_GOODPKT) {
427 len = (w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff;
428 skb_trim(skb, len);
429 skb->protocol = eth_type_trans(skb, dev);
430 netif_rx(skb);
431
432 ip->rx_skbs[rx_entry] = NULL; /* Poison */
433
434 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
435 if (!new_skb) {
436 /* Ouch, drop packet and just recycle packet
437 to keep the ring filled. */
438 ip->stats.rx_dropped++;
439 new_skb = skb;
440 goto next;
441 }
442
443 new_skb->dev = dev;
444
445 /* Because we reserve afterwards. */
446 skb_put(new_skb, (1664 + RX_OFFSET));
447 rxb = (struct ioc3_erxbuf *) new_skb->data;
448 skb_reserve(new_skb, RX_OFFSET);
449
450 ip->stats.rx_packets++; /* Statistics */
451 ip->stats.rx_bytes += len;
452 } else {
453 /* The frame is invalid and the skb never
454 reached the network layer so we can just
455 recycle it. */
456 new_skb = skb;
457 ip->stats.rx_errors++;
458 }
459 if (err & ERXBUF_CRCERR) /* Statistics */
460 ip->stats.rx_crc_errors++;
461 if (err & ERXBUF_FRAMERR)
462 ip->stats.rx_frame_errors++;
463 next:
464 ip->rx_skbs[n_entry] = new_skb;
465 rxr[n_entry] = (0xa5UL << 56) |
466 ((unsigned long) rxb & TO_PHYS_MASK);
467 rxb->w0 = 0; /* Clear valid flag */
468 n_entry = (n_entry + 1) & 511; /* Update erpir */
469
470 /* Now go on to the next ring entry. */
471 rx_entry = (rx_entry + 1) & 511;
472 skb = ip->rx_skbs[rx_entry];
473 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
474 w0 = rxb->w0;
475 }
476 ioc3->erpir = (n_entry << 3) | ERPIR_ARM;
477 ip->rx_pi = n_entry;
478 ip->rx_ci = rx_entry;
479 }
480
481 static inline void
482 ioc3_tx(struct net_device *dev, struct ioc3_private *ip, struct ioc3 *ioc3)
483 {
484 unsigned long packets, bytes;
485 int tx_entry, o_entry;
486 struct sk_buff *skb;
487 u32 etcir;
488
489 spin_lock(&ip->ioc3_lock);
490 etcir = ioc3->etcir;
491
492 tx_entry = (etcir >> 7) & 127;
493 o_entry = ip->tx_ci;
494 packets = 0;
495 bytes = 0;
496
497 while (o_entry != tx_entry) {
498 packets++;
499 skb = ip->tx_skbs[o_entry];
500 bytes += skb->len;
501 dev_kfree_skb_irq(skb);
502 ip->tx_skbs[o_entry] = NULL;
503
504 o_entry = (o_entry + 1) & 127; /* Next */
505
506 etcir = ioc3->etcir; /* More pkts sent? */
507 tx_entry = (etcir >> 7) & 127;
508 }
509
510 ip->stats.tx_packets += packets;
511 ip->stats.tx_bytes += bytes;
512 ip->txqlen -= packets;
513
514 if (ip->txqlen < 128)
515 netif_wake_queue(dev);
516
517 ip->tx_ci = o_entry;
518 spin_unlock(&ip->ioc3_lock);
519 }
520
521 /*
522 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
523 * software problems, so we should try to recover
524 * more gracefully if this ever happens. In theory we might be flooded
525 * with such error interrupts if something really goes wrong, so we might
526 * also consider to take the interface down.
527 */
528 static void
529 ioc3_error(struct net_device *dev, struct ioc3_private *ip,
530 struct ioc3 *ioc3, u32 eisr)
531 {
532 if (eisr & EISR_RXOFLO) {
533 printk(KERN_ERR "%s: RX overflow.\n", dev->name);
534 }
535 if (eisr & EISR_RXBUFOFLO) {
536 printk(KERN_ERR "%s: RX buffer overflow.\n", dev->name);
537 }
538 if (eisr & EISR_RXMEMERR) {
539 printk(KERN_ERR "%s: RX PCI error.\n", dev->name);
540 }
541 if (eisr & EISR_RXPARERR) {
542 printk(KERN_ERR "%s: RX SSRAM parity error.\n", dev->name);
543 }
544 if (eisr & EISR_TXBUFUFLO) {
545 printk(KERN_ERR "%s: TX buffer underflow.\n", dev->name);
546 }
547 if (eisr & EISR_TXMEMERR) {
548 printk(KERN_ERR "%s: TX PCI error.\n", dev->name);
549 }
550
551 ioc3_stop(dev);
552 ioc3_init(dev);
553 ioc3_mii_init(dev, ip, ioc3);
554
555 dev->trans_start = jiffies;
556 netif_wake_queue(dev);
557 }
558
559 /* The interrupt handler does all of the Rx thread work and cleans up
560 after the Tx thread. */
561 static void ioc3_interrupt(int irq, void *_dev, struct pt_regs *regs)
562 {
563 struct net_device *dev = (struct net_device *)_dev;
564 struct ioc3_private *ip = dev->priv;
565 struct ioc3 *ioc3 = ip->regs;
566 const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
567 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
568 EISR_TXEXPLICIT | EISR_TXMEMERR;
569 u32 eisr;
570
571 eisr = ioc3->eisr & enabled;
572
573 while (eisr) {
574 ioc3->eisr = eisr;
575 ioc3->eisr; /* Flush */
576
577 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
578 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
579 ioc3_error(dev, ip, ioc3, eisr);
580 if (eisr & EISR_RXTIMERINT)
581 ioc3_rx(dev, ip, ioc3);
582 if (eisr & EISR_TXEXPLICIT)
583 ioc3_tx(dev, ip, ioc3);
584
585 eisr = ioc3->eisr & enabled;
586 }
587 }
588
589 static void negotiate(unsigned long data)
590 {
591 struct net_device *dev = (struct net_device *) data;
592 struct ioc3_private *ip = (struct ioc3_private *) dev->priv;
593 struct ioc3 *ioc3 = ip->regs;
594
595 mod_timer(&ip->negtimer, jiffies + 20 * HZ);
596 }
597
598 static int ioc3_mii_init(struct net_device *dev, struct ioc3_private *ip,
599 struct ioc3 *ioc3)
600 {
601 u16 word, mii0;
602 int i, phy;
603
604 spin_lock_irq(&ip->ioc3_lock);
605 phy = -1;
606 for (i = 0; i < 32; i++) {
607 word = mii_read(ioc3, i, 2);
608 if ((word != 0xffff) && (word != 0x0000)) {
609 phy = i;
610 break; /* Found a PHY */
611 }
612 }
613 if (phy == -1) {
614 spin_unlock_irq(&ip->ioc3_lock);
615 return -ENODEV;
616 }
617 ip->phy = phy;
618
619 /* Autonegotiate 100mbit and fullduplex. */
620 mii0 = mii_read(ioc3, ip->phy, 0);
621 mii_write(ioc3, ip->phy, 0, mii0 | 0x3100);
622
623 ip->negtimer.function = &negotiate;
624 ip->negtimer.data = (unsigned long) dev;
625 mod_timer(&ip->negtimer, jiffies); /* Run it now */
626
627 spin_unlock_irq(&ip->ioc3_lock);
628
629 return 0;
630 }
631
632 static inline void
633 ioc3_clean_rx_ring(struct ioc3_private *ip)
634 {
635 struct sk_buff *skb;
636 int i;
637
638 for (i = ip->rx_ci; i & 15; i++) {
639 ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
640 ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
641 }
642 ip->rx_pi &= 511;
643 ip->rx_ci &= 511;
644
645 for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
646 struct ioc3_erxbuf *rxb;
647 skb = ip->rx_skbs[i];
648 rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
649 rxb->w0 = 0;
650 }
651 }
652
653 static inline void
654 ioc3_clean_tx_ring(struct ioc3_private *ip)
655 {
656 struct sk_buff *skb;
657 int i;
658
659 for (i=0; i < 128; i++) {
660 skb = ip->tx_skbs[i];
661 if (skb) {
662 ip->tx_skbs[i] = NULL;
663 dev_kfree_skb_any(skb);
664 }
665 ip->txr[i].cmd = 0;
666 }
667 ip->tx_pi = 0;
668 ip->tx_ci = 0;
669 }
670
671 static void
672 ioc3_free_rings(struct ioc3_private *ip)
673 {
674 struct sk_buff *skb;
675 int rx_entry, n_entry;
676
677 if (ip->txr) {
678 ioc3_clean_tx_ring(ip);
679 free_pages((unsigned long)ip->txr, 2);
680 ip->txr = NULL;
681 }
682
683 if (ip->rxr) {
684 n_entry = ip->rx_ci;
685 rx_entry = ip->rx_pi;
686
687 while (n_entry != rx_entry) {
688 skb = ip->rx_skbs[n_entry];
689 if (skb)
690 dev_kfree_skb_any(skb);
691
692 n_entry = (n_entry + 1) & 511;
693 }
694 free_page((unsigned long)ip->rxr);
695 ip->rxr = NULL;
696 }
697 }
698
699 static void
700 ioc3_alloc_rings(struct net_device *dev, struct ioc3_private *ip,
701 struct ioc3 *ioc3)
702 {
703 struct ioc3_erxbuf *rxb;
704 unsigned long *rxr;
705 int i;
706
707 if (ip->rxr == NULL) {
708 /* Allocate and initialize rx ring. 4kb = 512 entries */
709 ip->rxr = (unsigned long *) get_free_page(GFP_KERNEL|GFP_ATOMIC);
710 rxr = (unsigned long *) ip->rxr;
711
712 /* Now the rx buffers. The RX ring may be larger but
713 we only allocate 16 buffers for now. Need to tune
714 this for performance and memory later. */
715 for (i = 0; i < RX_BUFFS; i++) {
716 struct sk_buff *skb;
717
718 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
719 if (!skb) {
720 show_free_areas();
721 continue;
722 }
723
724 ip->rx_skbs[i] = skb;
725 skb->dev = dev;
726
727 /* Because we reserve afterwards. */
728 skb_put(skb, (1664 + RX_OFFSET));
729 rxb = (struct ioc3_erxbuf *) skb->data;
730 rxr[i] = (0xa5UL << 56)
731 | ((unsigned long) rxb & TO_PHYS_MASK);
732 skb_reserve(skb, RX_OFFSET);
733 }
734 ip->rx_ci = 0;
735 ip->rx_pi = RX_BUFFS;
736 }
737
738 if (ip->txr == NULL) {
739 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
740 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL|GFP_ATOMIC, 2);
741 ip->tx_pi = 0;
742 ip->tx_ci = 0;
743 }
744 }
745
746 static void
747 ioc3_init_rings(struct net_device *dev, struct ioc3_private *ip,
748 struct ioc3 *ioc3)
749 {
750 unsigned long ring;
751
752 ioc3_free_rings(ip);
753 ioc3_alloc_rings(dev, ip, ioc3);
754
755 ioc3_clean_rx_ring(ip);
756 ioc3_clean_tx_ring(ip);
757
758 /* Now the rx ring base, consume & produce registers. */
759 ring = (0xa5UL << 56) | ((unsigned long)ip->rxr & TO_PHYS_MASK);
760 ioc3->erbr_h = ring >> 32;
761 ioc3->erbr_l = ring & 0xffffffff;
762 ioc3->ercir = (ip->rx_ci << 3);
763 ioc3->erpir = (ip->rx_pi << 3) | ERPIR_ARM;
764
765 ring = (0xa5UL << 56) | ((unsigned long)ip->txr & TO_PHYS_MASK);
766
767 ip->txqlen = 0; /* nothing queued */
768
769 /* Now the tx ring base, consume & produce registers. */
770 ioc3->etbr_h = ring >> 32;
771 ioc3->etbr_l = ring & 0xffffffff;
772 ioc3->etpir = (ip->tx_pi << 7);
773 ioc3->etcir = (ip->tx_ci << 7);
774 ioc3->etcir; /* Flush */
775 }
776
777 static inline void
778 ioc3_ssram_disc(struct ioc3_private *ip)
779 {
780 struct ioc3 *ioc3 = ip->regs;
781 volatile u32 *ssram0 = &ioc3->ssram[0x0000];
782 volatile u32 *ssram1 = &ioc3->ssram[0x4000];
783 unsigned int pattern = 0x5555;
784
785 /* Assume the larger size SSRAM and enable parity checking */
786 ioc3->emcr |= (EMCR_BUFSIZ | EMCR_RAMPAR);
787
788 *ssram0 = pattern;
789 *ssram1 = ~pattern & IOC3_SSRAM_DM;
790
791 if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
792 (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
793 /* set ssram size to 64 KB */
794 ip->emcr = EMCR_RAMPAR;
795 ioc3->emcr &= ~EMCR_BUFSIZ;
796 } else {
797 ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
798 }
799 }
800
801 static void ioc3_init(struct net_device *dev)
802 {
803 struct ioc3_private *ip = dev->priv;
804 struct ioc3 *ioc3 = ip->regs;
805
806 ioc3->emcr = EMCR_RST; /* Reset */
807 ioc3->emcr; /* flush WB */
808 udelay(4); /* Give it time ... */
809 ioc3->emcr = 0;
810 ioc3->emcr;
811
812 /* Misc registers */
813 ioc3->erbar = 0;
814 ioc3->etcsr = (17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21;
815 ioc3->etcdc; /* Clear on read */
816 ioc3->ercsr = 15; /* RX low watermark */
817 ioc3->ertr = 0; /* Interrupt immediately */
818 ioc3->emar_h = (dev->dev_addr[5] << 8) | dev->dev_addr[4];
819 ioc3->emar_l = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
820 (dev->dev_addr[1] << 8) | dev->dev_addr[0];
821 ioc3->ehar_h = ip->ehar_h;
822 ioc3->ehar_l = ip->ehar_l;
823 ioc3->ersr = 42; /* XXX should be random */
824
825 ioc3_init_rings(dev, ip, ioc3);
826
827 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
828 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN;
829 ioc3->emcr = ip->emcr;
830 ioc3->eier = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
831 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
832 EISR_TXEXPLICIT | EISR_TXMEMERR;
833 ioc3->eier;
834 }
835
836 static inline void ioc3_stop(struct net_device *dev)
837 {
838 struct ioc3_private *ip = dev->priv;
839 struct ioc3 *ioc3 = ip->regs;
840
841 ioc3->emcr = 0; /* Shutup */
842 ioc3->eier = 0; /* Disable interrupts */
843 ioc3->eier; /* Flush */
844 }
845
846 static int
847 ioc3_open(struct net_device *dev)
848 {
849 struct ioc3_private *ip;
850
851 if (request_irq(dev->irq, ioc3_interrupt, 0, ioc3_str, dev)) {
852 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
853
854 return -EAGAIN;
855 }
856
857 ip = (struct ioc3_private *) dev->priv;
858
859 ip->ehar_h = 0;
860 ip->ehar_l = 0;
861 ioc3_init(dev);
862
863 netif_start_queue(dev);
864
865 MOD_INC_USE_COUNT;
866
867 return 0;
868 }
869
870 static int
871 ioc3_close(struct net_device *dev)
872 {
873 struct ioc3_private *ip = dev->priv;
874
875 del_timer(&ip->negtimer);
876 netif_stop_queue(dev);
877
878 ioc3_stop(dev); /* Flush */
879 free_irq(dev->irq, dev);
880
881 ioc3_free_rings(ip);
882
883 MOD_DEC_USE_COUNT;
884
885 return 0;
886 }
887
888 static int ioc3_pci_init(struct pci_dev *pdev)
889 {
890 u16 mii0, mii_status, mii2, mii3, mii4;
891 struct net_device *dev = NULL; // XXX
892 struct ioc3_private *ip;
893 struct ioc3 *ioc3;
894 unsigned long ioc3_base, ioc3_size;
895 u32 vendor, model, rev;
896 int phy;
897
898 dev = init_etherdev(0, sizeof(struct ioc3_private));
899
900 if (!dev)
901 return -ENOMEM;
902
903 ip = dev->priv;
904 memset(ip, 0, sizeof(*ip));
905
906 /*
907 * This probably needs to be register_netdevice, or call
908 * init_etherdev so that it calls register_netdevice. Quick
909 * hack for now.
910 */
911 netif_device_attach(dev);
912
913 dev->irq = pdev->irq;
914
915 ioc3_base = pdev->resource[0].start;
916 ioc3_size = pdev->resource[0].end - ioc3_base;
917 ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
918 ip->regs = ioc3;
919
920 spin_lock_init(&ip->ioc3_lock);
921
922 ioc3_stop(dev);
923 ip->emcr = 0;
924 ioc3_init(dev);
925
926 init_timer(&ip->negtimer);
927 ioc3_mii_init(dev, ip, ioc3);
928
929 phy = ip->phy;
930 if (phy == -1) {
931 printk(KERN_CRIT"%s: Didn't find a PHY, goodbye.\n", dev->name);
932 ioc3_stop(dev);
933 free_irq(dev->irq, dev);
934 ioc3_free_rings(ip);
935
936 return -ENODEV;
937 }
938
939 mii0 = mii_read(ioc3, phy, 0);
940 mii_status = mii_read(ioc3, phy, 1);
941 mii2 = mii_read(ioc3, phy, 2);
942 mii3 = mii_read(ioc3, phy, 3);
943 mii4 = mii_read(ioc3, phy, 4);
944 vendor = (mii2 << 12) | (mii3 >> 4);
945 model = (mii3 >> 4) & 0x3f;
946 rev = mii3 & 0xf;
947 printk(KERN_INFO"Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
948 phy, vendor, model, rev);
949 printk(KERN_INFO "%s: MII transceiver found at MDIO address "
950 "%d, config %4.4x status %4.4x.\n",
951 dev->name, phy, mii0, mii_status);
952
953 ioc3_ssram_disc(ip);
954 printk("IOC3 SSRAM has %d kbyte.\n", ip->emcr & EMCR_BUFSIZ ? 128 : 64);
955
956 ioc3_get_eaddr(dev, ioc3);
957
958 /* The IOC3-specific entries in the device structure. */
959 dev->open = ioc3_open;
960 dev->hard_start_xmit = ioc3_start_xmit;
961 dev->tx_timeout = ioc3_timeout;
962 dev->watchdog_timeo = 5 * HZ;
963 dev->stop = ioc3_close;
964 dev->get_stats = ioc3_get_stats;
965 dev->do_ioctl = ioc3_ioctl;
966 dev->set_multicast_list = ioc3_set_multicast_list;
967
968 return 0;
969 }
970
971 static int __init ioc3_probe(void)
972 {
973 static int called = 0;
974 int cards = 0;
975
976 if (called)
977 return -ENODEV;
978 called = 1;
979
980 if (pci_present()) {
981 struct pci_dev *pdev = NULL;
982
983 while ((pdev = pci_find_device(PCI_VENDOR_ID_SGI,
984 PCI_DEVICE_ID_SGI_IOC3, pdev))) {
985 if (ioc3_pci_init(pdev))
986 return -ENOMEM;
987 cards++;
988 }
989 }
990
991 return cards ? -ENODEV : 0;
992 }
993
994 static void __exit ioc3_cleanup_module(void)
995 {
996 /* Later, when we really support modules. */
997 }
998
999 static int
1000 ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1001 {
1002 unsigned long data;
1003 struct ioc3_private *ip = dev->priv;
1004 struct ioc3 *ioc3 = ip->regs;
1005 unsigned int len;
1006 struct ioc3_etxd *desc;
1007 int produce;
1008
1009 spin_lock_irq(&ip->ioc3_lock);
1010
1011 data = (unsigned long) skb->data;
1012 len = skb->len;
1013
1014 produce = ip->tx_pi;
1015 desc = &ip->txr[produce];
1016
1017 if (len <= 104) {
1018 /* Short packet, let's copy it directly into the ring. */
1019 memcpy(desc->data, skb->data, skb->len);
1020 if (len < ETH_ZLEN) {
1021 /* Very short packet, pad with zeros at the end. */
1022 memset(desc->data + len, 0, ETH_ZLEN - len);
1023 len = ETH_ZLEN;
1024 }
1025 desc->cmd = len | ETXD_INTWHENDONE | ETXD_D0V;
1026 desc->bufcnt = len;
1027 } else if ((data ^ (data + len)) & 0x4000) {
1028 unsigned long b2, s1, s2;
1029
1030 b2 = (data | 0x3fffUL) + 1UL;
1031 s1 = b2 - data;
1032 s2 = data + len - b2;
1033
1034 desc->cmd = len | ETXD_INTWHENDONE | ETXD_B1V | ETXD_B2V;
1035 desc->bufcnt = (s1 << ETXD_B1CNT_SHIFT) |
1036 (s2 << ETXD_B2CNT_SHIFT);
1037 desc->p1 = (0xa5UL << 56) | (data & TO_PHYS_MASK);
1038 desc->p2 = (0xa5UL << 56) | (data & TO_PHYS_MASK);
1039 } else {
1040 /* Normal sized packet that doesn't cross a page boundary. */
1041 desc->cmd = len | ETXD_INTWHENDONE | ETXD_B1V;
1042 desc->bufcnt = len << ETXD_B1CNT_SHIFT;
1043 desc->p1 = (0xa5UL << 56) | (data & TO_PHYS_MASK);
1044 }
1045
1046 BARRIER();
1047
1048 dev->trans_start = jiffies;
1049 ip->tx_skbs[produce] = skb; /* Remember skb */
1050 produce = (produce + 1) & 127;
1051 ip->tx_pi = produce;
1052 ioc3->etpir = produce << 7; /* Fire ... */
1053
1054 ip->txqlen++;
1055
1056 if (ip->txqlen > 127)
1057 netif_stop_queue(dev);
1058
1059 spin_unlock_irq(&ip->ioc3_lock);
1060
1061 return 0;
1062 }
1063
1064 static void ioc3_timeout(struct net_device *dev)
1065 {
1066 struct ioc3_private *ip = dev->priv;
1067 struct ioc3 *ioc3 = ip->regs;
1068
1069 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
1070
1071 ioc3_stop(dev);
1072 ioc3_init(dev);
1073 ioc3_mii_init(dev, ip, ioc3);
1074
1075 dev->trans_start = jiffies;
1076 netif_wake_queue(dev);
1077 }
1078
1079 /*
1080 * Given a multicast ethernet address, this routine calculates the
1081 * address's bit index in the logical address filter mask
1082 */
1083 #define CRC_MASK 0xEDB88320
1084
1085 static inline unsigned int
1086 ioc3_hash(const unsigned char *addr)
1087 {
1088 unsigned int temp = 0;
1089 unsigned char byte;
1090 unsigned int crc;
1091 int bits, len;
1092
1093 len = ETH_ALEN;
1094 for (crc = ~0; --len >= 0; addr++) {
1095 byte = *addr;
1096 for (bits = 8; --bits >= 0; ) {
1097 if ((byte ^ crc) & 1)
1098 crc = (crc >> 1) ^ CRC_MASK;
1099 else
1100 crc >>= 1;
1101 byte >>= 1;
1102 }
1103 }
1104
1105 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1106 for (bits = 6; --bits >= 0; ) {
1107 temp <<= 1;
1108 temp |= (crc & 0x1);
1109 crc >>= 1;
1110 }
1111
1112 return temp;
1113 }
1114
1115 /* Provide ioctl() calls to examine the MII xcvr state. */
1116 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1117 {
1118 struct ioc3_private *ip = (struct ioc3_private *) dev->priv;
1119 u16 *data = (u16 *)&rq->ifr_data;
1120 struct ioc3 *ioc3 = ip->regs;
1121 int phy = ip->phy;
1122
1123 switch (cmd) {
1124 case SIOCGMIIPHY: /* Get the address of the PHY in use. */
1125 if (phy == -1)
1126 return -ENODEV;
1127 data[0] = phy;
1128 return 0;
1129
1130 case SIOCGMIIREG: /* Read any PHY register. */
1131 spin_lock_irq(&ip->ioc3_lock);
1132 data[3] = mii_read(ioc3, data[0], data[1]);
1133 spin_unlock_irq(&ip->ioc3_lock);
1134 return 0;
1135
1136 case SIOCSMIIREG: /* Write any PHY register. */
1137 if (!capable(CAP_NET_ADMIN))
1138 return -EPERM;
1139 spin_lock_irq(&ip->ioc3_lock);
1140 mii_write(ioc3, data[0], data[1], data[2]);
1141 spin_unlock_irq(&ip->ioc3_lock);
1142 return 0;
1143
1144 default:
1145 return -EOPNOTSUPP;
1146 }
1147
1148 return -EOPNOTSUPP;
1149 }
1150
1151 static void ioc3_set_multicast_list(struct net_device *dev)
1152 {
1153 struct dev_mc_list *dmi = dev->mc_list;
1154 struct ioc3_private *ip = dev->priv;
1155 struct ioc3 *ioc3 = ip->regs;
1156 char *addr = dmi->dmi_addr;
1157 u64 ehar = 0;
1158 int i;
1159
1160 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1161 /* Unconditionally log net taps. */
1162 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1163 ip->emcr |= EMCR_PROMISC;
1164 ioc3->emcr = ip->emcr;
1165 ioc3->emcr;
1166 } else {
1167 ip->emcr &= ~EMCR_PROMISC;
1168 ioc3->emcr = ip->emcr; /* Clear promiscuous. */
1169 ioc3->emcr;
1170
1171 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1172 /* Too many for hashing to make sense or we want all
1173 multicast packets anyway, so skip computing all the
1174 hashes and just accept all packets. */
1175 ip->ehar_h = 0xffffffff;
1176 ip->ehar_l = 0xffffffff;
1177 } else {
1178 for (i = 0; i < dev->mc_count; i++) {
1179 dmi = dmi->next;
1180
1181 if (!(*addr & 1))
1182 continue;
1183
1184 ehar |= (1UL << ioc3_hash(addr));
1185 }
1186 ip->ehar_h = ehar >> 32;
1187 ip->ehar_l = ehar & 0xffffffff;
1188 }
1189 ioc3->ehar_h = ip->ehar_h;
1190 ioc3->ehar_l = ip->ehar_l;
1191 }
1192 }
1193
1194 #ifdef MODULE
1195 MODULE_AUTHOR("Ralf Baechle <ralf@oss.sgi.com>");
1196 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1197 #endif /* MODULE */
1198
1199 module_init(ioc3_probe);
1200 module_exit(ioc3_cleanup_module);
1201
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