1 /*
2 * Driver for the Macintosh 68K onboard MACE controller with PSC
3 * driven DMA. The MACE driver code is derived from mace.c. The
4 * Mac68k theory of operation is courtesy of the MacBSD wizards.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Copyright (C) 1996 Paul Mackerras.
12 * Copyright (C) 1998 Alan Cox <alan@redhat.com>
13 */
14
15
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/delay.h>
20 #include <linux/string.h>
21 #include <linux/timer.h>
22 #include <asm/io.h>
23 #include <asm/pgtable.h>
24 #include <asm/irq.h>
25 #include <asm/macintosh.h>
26 #include <asm/macints.h>
27 #include <asm/mac_psc.h>
28 #include "mace.h"
29
30 #define N_RX_RING 8
31 #define N_TX_RING 2
32 #define MAX_TX_ACTIVE 1
33 #define NCMDS_TX 1 /* dma commands per element in tx ring */
34 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
35 #define TX_TIMEOUT HZ /* 1 second */
36
37 /* Bits in transmit DMA status */
38 #define TX_DMA_ERR 0x80
39
40 /* The MACE is simply wired down on a Mac68K box */
41
42 #define MACE_BASE (void *)(0x50F1C000)
43 #define MACE_PROM (void *)(0x50F08001)
44
45 struct mace68k_data
46 {
47 volatile struct mace *mace;
48 volatile unsigned char *tx_ring;
49 volatile unsigned char *rx_ring;
50 int dma_intr;
51 unsigned char maccc;
52 struct net_device_stats stats;
53 struct timer_list tx_timeout;
54 int timeout_active;
55 int rx_slot, rx_done;
56 int tx_slot, tx_count;
57 };
58
59 struct mace_frame
60 {
61 u16 len;
62 u16 status;
63 u16 rntpc;
64 u16 rcvcc;
65 u32 pad1;
66 u32 pad2;
67 u8 data[1];
68 /* And frame continues.. */
69 };
70
71 #define PRIV_BYTES sizeof(struct mace68k_data)
72
73 extern void psc_debug_dump(void);
74
75 static int mace68k_open(struct net_device *dev);
76 static int mace68k_close(struct net_device *dev);
77 static int mace68k_xmit_start(struct sk_buff *skb, struct net_device *dev);
78 static struct net_device_stats *mace68k_stats(struct net_device *dev);
79 static void mace68k_set_multicast(struct net_device *dev);
80 static void mace68k_reset(struct net_device *dev);
81 static int mace68k_set_address(struct net_device *dev, void *addr);
82 static void mace68k_interrupt(int irq, void *dev_id, struct pt_regs *regs);
83 static void mace68k_dma_intr(int irq, void *dev_id, struct pt_regs *regs);
84 static void mace68k_set_timeout(struct net_device *dev);
85 static void mace68k_tx_timeout(unsigned long data);
86
87 /*
88 * PSC DMA engine control. As you'd expect on a macintosh its
89 * more like a lawnmower engine supplied without instructions
90 *
91 * The basic theory of operation appears to be as follows.
92 *
93 * There are two sets of receive DMA registers and two sets
94 * of transmit DMA registers. Instead of the more traditional
95 * "ring buffer" approach the Mac68K DMA engine expects you
96 * to be loading one chain while the other runs, and then
97 * to flip register set. Each entry in the chain is a fixed
98 * length.
99 */
100
101 /*
102 * Load a receive DMA channel with a base address and ring length
103 */
104
105 static void psc_load_rxdma_base(int set, void *base)
106 {
107 psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
108 psc_write_long(PSC_ENETRD_ADDR + set, (u32)base);
109 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
110 psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
111 }
112
113 /*
114 * Reset the receive DMA subsystem
115 */
116
117 static void mace68k_rxdma_reset(struct net_device *dev)
118 {
119 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
120 volatile struct mace *mace = mp->mace;
121 u8 mcc = mace->maccc;
122
123 /*
124 * Turn off receive
125 */
126
127 mcc&=~ENRCV;
128 mace->maccc=mcc;
129
130 /*
131 * Program the DMA
132 */
133
134 psc_write_word(PSC_ENETRD_CTL, 0x8800);
135 psc_load_rxdma_base(0x0, (void *)virt_to_bus(mp->rx_ring));
136 psc_write_word(PSC_ENETRD_CTL, 0x0400);
137
138 psc_write_word(PSC_ENETRD_CTL, 0x8800);
139 psc_load_rxdma_base(0x10, (void *)virt_to_bus(mp->rx_ring));
140 psc_write_word(PSC_ENETRD_CTL, 0x0400);
141
142 mace->maccc=mcc|ENRCV;
143
144 #if 0
145 psc_write_word(PSC_ENETRD_CTL, 0x9800);
146 psc_write_word(PSC_ENETRD_CTL+0x10, 0x9800);
147 #endif
148 }
149
150 /*
151 * Reset the transmit DMA subsystem
152 */
153
154 static void mace68k_txdma_reset(struct net_device *dev)
155 {
156 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
157 volatile struct mace *mace = mp->mace;
158 u8 mcc = mace->maccc;
159
160 psc_write_word(PSC_ENETWR_CTL,0x8800);
161
162 mace->maccc = mcc&~ENXMT;
163 psc_write_word(PSC_ENETWR_CTL,0x0400);
164 mace->maccc = mcc;
165 }
166
167 /*
168 * Disable DMA
169 */
170
171 static void mace68k_dma_off(struct net_device *dev)
172 {
173 psc_write_word(PSC_ENETRD_CTL, 0x8800);
174 psc_write_word(PSC_ENETRD_CTL, 0x1000);
175 psc_write_word(PSC_ENETRD_CMD, 0x1100);
176 psc_write_word(PSC_ENETRD_CMD+0x10, 0x1100);
177
178 psc_write_word(PSC_ENETWR_CTL, 0x8800);
179 psc_write_word(PSC_ENETWR_CTL, 0x1000);
180 psc_write_word(PSC_ENETWR_CMD, 0x1100);
181 psc_write_word(PSC_ENETWR_CMD+0x10, 0x1100);
182 }
183
184 /* Bit-reverse one byte of an ethernet hardware address. */
185
186 static int bitrev(int b)
187 {
188 int d = 0, i;
189
190 for (i = 0; i < 8; ++i, b >>= 1)
191 d = (d << 1) | (b & 1);
192 return d;
193 }
194
195 /*
196 * Not really much of a probe. The hardware table tells us if this
197 * model of Macintrash has a MACE (AV macintoshes)
198 */
199
200 int mace68k_probe(struct net_device *unused)
201 {
202 int j;
203 static int once=0;
204 struct mace68k_data *mp;
205 unsigned char *addr;
206 struct net_device *dev;
207 unsigned char checksum = 0;
208
209 /*
210 * There can be only one...
211 */
212
213 if (once) return -ENODEV;
214
215 once = 1;
216
217 if (macintosh_config->ether_type != MAC_ETHER_MACE) return -ENODEV;
218
219 printk("MACE ethernet should be present ");
220
221 dev = init_etherdev(0, PRIV_BYTES);
222 if(dev==NULL)
223 {
224 printk("no free memory.\n");
225 return -ENOMEM;
226 }
227 mp = (struct mace68k_data *) dev->priv;
228 dev->base_addr = (u32)MACE_BASE;
229 mp->mace = (volatile struct mace *) MACE_BASE;
230
231 printk("at 0x%p", mp->mace);
232
233 /*
234 * 16K RX ring and 4K TX ring should do nicely
235 */
236
237 mp->rx_ring=(void *)__get_free_pages(GFP_KERNEL, 2);
238 mp->tx_ring=(void *)__get_free_page(GFP_KERNEL);
239
240 printk(".");
241
242 if(mp->tx_ring==NULL || mp->rx_ring==NULL)
243 {
244 if(mp->tx_ring)
245 free_page((u32)mp->tx_ring);
246 // if(mp->rx_ring)
247 // __free_pages(mp->rx_ring,2);
248 printk("\nNo memory for ring buffers.\n");
249 return -ENOMEM;
250 }
251
252 /* We want the receive data to be uncached. We dont care about the
253 byte reading order */
254
255 printk(".");
256 kernel_set_cachemode((void *)mp->rx_ring, 16384, IOMAP_NOCACHE_NONSER);
257
258 printk(".");
259 /* The transmit buffer needs to be write through */
260 kernel_set_cachemode((void *)mp->tx_ring, 4096, IOMAP_WRITETHROUGH);
261
262 printk(" Ok\n");
263 dev->irq = IRQ_MAC_MACE;
264 printk(KERN_INFO "%s: MACE at", dev->name);
265
266 /*
267 * The PROM contains 8 bytes which total 0xFF when XOR'd
268 * together. Due to the usual peculiar apple brain damage
269 * the bytes are spaced out in a strange boundary and the
270 * bits are reversed.
271 */
272
273 addr = (void *)MACE_PROM;
274
275 for (j = 0; j < 6; ++j)
276 {
277 u8 v=bitrev(addr[j<<4]);
278 checksum^=v;
279 dev->dev_addr[j] = v;
280 printk("%c%.2x", (j ? ':' : ' '), dev->dev_addr[j]);
281 }
282 for (; j < 8; ++j)
283 {
284 checksum^=bitrev(addr[j<<4]);
285 }
286
287 if(checksum!=0xFF)
288 {
289 printk(" (invalid checksum)\n");
290 return -ENODEV;
291 }
292 printk("\n");
293
294 memset(&mp->stats, 0, sizeof(mp->stats));
295 init_timer(&mp->tx_timeout);
296 mp->timeout_active = 0;
297
298 dev->open = mace68k_open;
299 dev->stop = mace68k_close;
300 dev->hard_start_xmit = mace68k_xmit_start;
301 dev->get_stats = mace68k_stats;
302 dev->set_multicast_list = mace68k_set_multicast;
303 dev->set_mac_address = mace68k_set_address;
304
305 ether_setup(dev);
306
307 mp = (struct mace68k_data *) dev->priv;
308 mp->maccc = ENXMT | ENRCV;
309 mp->dma_intr = IRQ_MAC_MACE_DMA;
310
311 psc_write_word(PSC_ENETWR_CTL, 0x9000);
312 psc_write_word(PSC_ENETRD_CTL, 0x9000);
313 psc_write_word(PSC_ENETWR_CTL, 0x0400);
314 psc_write_word(PSC_ENETRD_CTL, 0x0400);
315
316 /* apple's driver doesn't seem to do this */
317 /* except at driver shutdown time... */
318 #if 0
319 mace68k_dma_off(dev);
320 #endif
321
322 return 0;
323 }
324
325 /*
326 * Reset a MACE controller
327 */
328
329 static void mace68k_reset(struct net_device *dev)
330 {
331 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
332 volatile struct mace *mb = mp->mace;
333 int i;
334
335 /* soft-reset the chip */
336 i = 200;
337 while (--i) {
338 mb->biucc = SWRST;
339 if (mb->biucc & SWRST) {
340 udelay(10);
341 continue;
342 }
343 break;
344 }
345 if (!i) {
346 printk(KERN_ERR "mace: cannot reset chip!\n");
347 return;
348 }
349
350 mb->biucc = XMTSP_64;
351 mb->imr = 0xff; /* disable all intrs for now */
352 i = mb->ir;
353 mb->maccc = 0; /* turn off tx, rx */
354 mb->utr = RTRD;
355 mb->fifocc = RCVFW_64;
356 mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */
357
358 /* load up the hardware address */
359
360 mb->iac = ADDRCHG | PHYADDR;
361
362 while ((mb->iac & ADDRCHG) != 0);
363
364 for (i = 0; i < 6; ++i)
365 mb->padr = dev->dev_addr[i];
366
367 /* clear the multicast filter */
368 mb->iac = ADDRCHG | LOGADDR;
369
370 while ((mb->iac & ADDRCHG) != 0);
371
372 for (i = 0; i < 8; ++i)
373 mb->ladrf = 0;
374
375 mb->plscc = PORTSEL_GPSI + ENPLSIO;
376 }
377
378 /*
379 * Load the address on a mace controller.
380 */
381
382 static int mace68k_set_address(struct net_device *dev, void *addr)
383 {
384 unsigned char *p = addr;
385 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
386 volatile struct mace *mb = mp->mace;
387 int i;
388 unsigned long flags;
389
390 save_flags(flags);
391 cli();
392
393 /* load up the hardware address */
394 mb->iac = ADDRCHG | PHYADDR;
395 while ((mb->iac & ADDRCHG) != 0);
396
397 for (i = 0; i < 6; ++i)
398 mb->padr = dev->dev_addr[i] = p[i];
399 /* note: setting ADDRCHG clears ENRCV */
400 mb->maccc = mp->maccc;
401 restore_flags(flags);
402 return 0;
403 }
404
405 /*
406 * Open the Macintosh MACE. Most of this is playing with the DMA
407 * engine. The ethernet chip is quite friendly.
408 */
409
410 static int mace68k_open(struct net_device *dev)
411 {
412 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
413 volatile struct mace *mb = mp->mace;
414
415 /* reset the chip */
416 mace68k_reset(dev);
417
418 mp->rx_done = 0;
419 mace68k_rxdma_reset(dev);
420
421 /*
422 * The interrupt is fixed and comes off the PSC.
423 */
424
425 if (request_irq(dev->irq, mace68k_interrupt, 0, "68K MACE", dev))
426 {
427 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
428 return -EAGAIN;
429 }
430
431 /*
432 * Ditto the DMA interrupt.
433 */
434
435 if (request_irq(IRQ_MAC_MACE_DMA, mace68k_dma_intr, 0, "68K MACE DMA",
436 dev))
437 {
438 printk(KERN_ERR "MACE: can't get irq %d\n", IRQ_MAC_MACE_DMA);
439 return -EAGAIN;
440 }
441
442 /* Activate the Mac DMA engine */
443
444 mp->tx_slot = 0; /* Using register set 0 */
445 mp->tx_count = 1; /* 1 Buffer ready for use */
446 mace68k_txdma_reset(dev);
447
448 /* turn it on! */
449 mb->maccc = mp->maccc;
450 /* enable all interrupts except receive interrupts */
451 mb->imr = RCVINT;
452 return 0;
453 }
454
455 /*
456 * Shut down the mace and its interrupt channel
457 */
458
459 static int mace68k_close(struct net_device *dev)
460 {
461 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
462 volatile struct mace *mb = mp->mace;
463
464 /* disable rx and tx */
465 mb->maccc = 0;
466 mb->imr = 0xff; /* disable all intrs */
467
468 /* disable rx and tx dma */
469
470 mace68k_dma_off(dev);
471
472 free_irq(dev->irq, dev);
473 free_irq(IRQ_MAC_MACE_DMA, dev);
474 return 0;
475 }
476
477 static inline void mace68k_set_timeout(struct net_device *dev)
478 {
479 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
480 unsigned long flags;
481
482 save_flags(flags);
483 cli();
484 if (mp->timeout_active)
485 del_timer(&mp->tx_timeout);
486 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
487 mp->tx_timeout.function = mace68k_tx_timeout;
488 mp->tx_timeout.data = (unsigned long) dev;
489 add_timer(&mp->tx_timeout);
490 mp->timeout_active = 1;
491 restore_flags(flags);
492 }
493
494 /*
495 * Transmit a frame
496 */
497
498 static int mace68k_xmit_start(struct sk_buff *skb, struct net_device *dev)
499 {
500 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
501 /*
502 * This may need atomic types ???
503 */
504
505 printk("mace68k_xmit_start: mp->tx_count = %d, dev->tbusy = %d, mp->tx_ring = %p (%p)\n",
506 mp->tx_count, dev->tbusy,
507 mp->tx_ring, virt_to_bus(mp->tx_ring));
508 psc_debug_dump();
509
510 if(mp->tx_count == 0)
511 {
512 dev->tbusy=1;
513 mace68k_dma_intr(IRQ_MAC_MACE_DMA, dev, NULL);
514 return 1;
515 }
516 mp->tx_count--;
517
518 /*
519 * FIXME:
520 * This is hackish. The memcpy probably isnt needed but
521 * the rules for alignment are not known. Ideally we'd like
522 * to just blast the skb directly to ethernet. We also don't
523 * use the ring properly - just a one frame buffer. That
524 * also requires cache pushes ;).
525 */
526 memcpy((void *)mp->tx_ring, skb, skb->len);
527 psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, virt_to_bus(mp->tx_ring));
528 psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
529 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
530 mp->stats.tx_packets++;
531 mp->stats.tx_bytes+=skb->len;
532 dev_kfree_skb(skb);
533 return 0;
534 }
535
536 static struct net_device_stats *mace68k_stats(struct net_device *dev)
537 {
538 struct mace68k_data *p = (struct mace68k_data *) dev->priv;
539 return &p->stats;
540 }
541
542 /*
543 * CRC polynomial - used in working out multicast filter bits.
544 */
545 #define CRC_POLY 0xedb88320
546
547 static void mace68k_set_multicast(struct net_device *dev)
548 {
549 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
550 volatile struct mace *mb = mp->mace;
551 int i, j, k, b;
552 unsigned long crc;
553
554 mp->maccc &= ~PROM;
555 if (dev->flags & IFF_PROMISC)
556 {
557 mp->maccc |= PROM;
558 } else
559 {
560 unsigned char multicast_filter[8];
561 struct dev_mc_list *dmi = dev->mc_list;
562
563 if (dev->flags & IFF_ALLMULTI)
564 {
565 for (i = 0; i < 8; i++)
566 multicast_filter[i] = 0xff;
567 } else
568 {
569 for (i = 0; i < 8; i++)
570 multicast_filter[i] = 0;
571 for (i = 0; i < dev->mc_count; i++)
572 {
573 crc = ~0;
574 for (j = 0; j < 6; ++j)
575 {
576 b = dmi->dmi_addr[j];
577 for (k = 0; k < 8; ++k)
578 {
579 if ((crc ^ b) & 1)
580 crc = (crc >> 1) ^ CRC_POLY;
581 else
582 crc >>= 1;
583 b >>= 1;
584 }
585 }
586 j = crc >> 26; /* bit number in multicast_filter */
587 multicast_filter[j >> 3] |= 1 << (j & 7);
588 dmi = dmi->next;
589 }
590 }
591 #if 0
592 printk("Multicast filter :");
593 for (i = 0; i < 8; i++)
594 printk("%02x ", multicast_filter[i]);
595 printk("\n");
596 #endif
597
598 mb->iac = ADDRCHG | LOGADDR;
599 while ((mb->iac & ADDRCHG) != 0);
600
601 for (i = 0; i < 8; ++i)
602 mb->ladrf = multicast_filter[i];
603 }
604 /* reset maccc */
605 mb->maccc = mp->maccc;
606 }
607
608 /*
609 * Miscellaneous interrupts are handled here. We may end up
610 * having to bash the chip on the head for bad errors
611 */
612
613 static void mace68k_handle_misc_intrs(struct mace68k_data *mp, int intr)
614 {
615 volatile struct mace *mb = mp->mace;
616 static int mace68k_babbles, mace68k_jabbers;
617
618 if (intr & MPCO)
619 mp->stats.rx_missed_errors += 256;
620 mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */
621 if (intr & RNTPCO)
622 mp->stats.rx_length_errors += 256;
623 mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */
624 if (intr & CERR)
625 ++mp->stats.tx_heartbeat_errors;
626 if (intr & BABBLE)
627 if (mace68k_babbles++ < 4)
628 printk(KERN_DEBUG "mace: babbling transmitter\n");
629 if (intr & JABBER)
630 if (mace68k_jabbers++ < 4)
631 printk(KERN_DEBUG "mace: jabbering transceiver\n");
632 }
633
634 /*
635 * A transmit error has occured. (We kick the transmit side from
636 * the DMA completion)
637 */
638
639 static void mace68k_xmit_error(struct net_device *dev)
640 {
641 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
642 volatile struct mace *mb = mp->mace;
643 u8 xmtfs, xmtrc;
644
645 xmtfs = mb->xmtfs;
646 xmtrc = mb->xmtrc;
647
648 if(xmtfs & XMTSV)
649 {
650 if(xmtfs & UFLO)
651 {
652 printk("%s: DMA underrun.\n", dev->name);
653 mp->stats.tx_errors++;
654 mp->stats.tx_fifo_errors++;
655 mace68k_reset(dev);
656 }
657 if(xmtfs & RTRY)
658 mp->stats.collisions++;
659 }
660 mark_bh(NET_BH);
661 }
662
663 /*
664 * A receive interrupt occured.
665 */
666
667 static void mace68k_recv_interrupt(struct net_device *dev)
668 {
669 // struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
670 // volatile struct mace *mb = mp->mace;
671 }
672
673 /*
674 * Process the chip interrupt
675 */
676
677 static void mace68k_interrupt(int irq, void *dev_id, struct pt_regs *regs)
678 {
679 struct net_device *dev = (struct net_device *) dev_id;
680 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
681 volatile struct mace *mb = mp->mace;
682 u8 ir;
683
684 ir = mb->ir;
685 mace68k_handle_misc_intrs(mp, ir);
686
687 if(ir&XMTINT)
688 mace68k_xmit_error(dev);
689 if(ir&RCVINT)
690 mace68k_recv_interrupt(dev);
691 }
692
693 static void mace68k_tx_timeout(unsigned long data)
694 {
695 // struct net_device *dev = (struct net_device *) data;
696 // struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
697 // volatile struct mace *mb = mp->mace;
698 }
699
700 /*
701 * Handle a newly arrived frame
702 */
703
704 static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
705 {
706 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
707 struct sk_buff *skb;
708
709 if(mf->status&RS_OFLO)
710 {
711 printk("%s: fifo overflow.\n", dev->name);
712 mp->stats.rx_errors++;
713 mp->stats.rx_fifo_errors++;
714 }
715 if(mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR))
716 mp->stats.rx_errors++;
717
718 if(mf->status&RS_CLSN)
719 mp->stats.collisions++;
720 if(mf->status&RS_FRAMERR)
721 mp->stats.rx_frame_errors++;
722 if(mf->status&RS_FCSERR)
723 mp->stats.rx_crc_errors++;
724
725 skb = dev_alloc_skb(mf->len+2);
726 if(skb==NULL)
727 {
728 mp->stats.rx_dropped++;
729 return;
730 }
731 skb_reserve(skb,2);
732 memcpy(skb_put(skb, mf->len), mf->data, mf->len);
733
734 skb->protocol = eth_type_trans(skb, dev);
735 netif_rx(skb);
736 mp->stats.rx_packets++;
737 mp->stats.rx_bytes+=mf->len;
738 }
739
740 /*
741 * The PSC has passed us a DMA interrupt event.
742 */
743
744 static void mace68k_dma_intr(int irq, void *dev_id, struct pt_regs *regs)
745 {
746 struct net_device *dev = (struct net_device *) dev_id;
747 struct mace68k_data *mp = (struct mace68k_data *) dev->priv;
748
749 #if 0
750 u32 psc_status;
751
752 /* It seems this must be allowed to stabilise ?? */
753
754 while((psc_status=psc_read_long(0x0804))!=psc_read_long(0x0804));
755
756 /*
757 * Was this an ethernet event ?
758 */
759
760 if(psc_status&0x60000000)
761 {
762 #endif
763 /*
764 * Process the read queue
765 */
766
767 u16 psc_status = psc_read_word(PSC_ENETRD_CTL);
768
769 printk("mace68k_dma_intr: PSC_ENETRD_CTL = %04X\n", (uint) psc_status);
770
771 if (psc_status & 0x2000) {
772 mace68k_rxdma_reset(dev);
773 mp->rx_done = 0;
774 } else if (psc_status & 0x100) {
775 int left;
776
777 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
778 left=psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
779 /* read packets */
780
781 while(mp->rx_done < left)
782 {
783 struct mace_frame *mf=((struct mace_frame *)
784 mp->rx_ring)+mp->rx_done++;
785 mace_dma_rx_frame(dev, mf);
786 }
787
788 if(left == 0) /* Out of DMA room */
789 {
790 psc_load_rxdma_base(mp->rx_slot,
791 (void *)virt_to_phys(mp->rx_ring));
792 mp->rx_slot^=16;
793 mp->rx_done = 0;
794 }
795 else
796 {
797 psc_write_word(PSC_ENETRD_CMD+mp->rx_slot,
798 0x9800);
799 }
800
801 }
802
803 /*
804 * Process the write queue
805 */
806
807 psc_status = psc_read_word(PSC_ENETWR_CTL);
808 printk("mace68k_dma_intr: PSC_ENETWR_CTL = %04X\n", (uint) psc_status);
809
810 /* apple's driver seems to loop over this until neither */
811 /* condition is true. - jmt */
812
813 if (psc_status & 0x2000) {
814 mace68k_txdma_reset(dev);
815 } else if (psc_status & 0x0100) {
816 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x0100);
817 mp->tx_slot ^=16;
818 mp->tx_count++;
819 dev->tbusy = 0;
820 mark_bh(NET_BH);
821 }
822 #if 0
823 }
824 #endif
825 }
826
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