1 #ifndef _NET_H_SYMBA
2 #define _NET_H_SYMBA
3
4 /* transmit status bit definitions */
5 #define TX_STATUS_TXOK (1<<13) /* success */
6 #define TX_STATUS_TDLC (1<<12) /* dropped for late colls */
7 #define TX_STATUS_TCXSDFR (1<<11) /* excessive deferral */
8 #define TX_STATUS_TDEC (1<<10) /* excessive collisions */
9 #define TX_STATUS_TAUR (1<<9) /* abort on underrun/"jumbo" */
10 #define TX_STATUS_PDFRD (1<<8) /* packet deferred */
11 #define TX_STATUS_BCAST (1<<7) /* broadcast ok */
12 #define TX_STATUS_MCAST (1<<6) /* multicast ok */
13 #define TX_STATUS_CRCERR (1<<5) /* CRC error */
14 #define TX_STATUS_LC (1<<4) /* late collision */
15 #define TX_STATUS_CCNT_MASK 0xf /* collision count */
16
17 #define T_TXOK (1<<13)
18 #define T_TDLC (1<<12)
19 #define T_TCXSDFR (1<<11)
20 #define T_TDEC (1<<10)
21 #define T_TAUR (1<<9)
22 #define T_PDFRD (1<<8)
23 #define T_BCAST (1<<7)
24 #define T_MCAST (1<<6)
25 #define T_LC (1<<4)
26 #define T_CCNT_MASK 0xf
27
28 /* receive status bit definitions */
29 #define RX_STATUS_RXOVRN (1<<23) /* overrun */
30 #define RX_STATUS_CEPS (1<<22) /* carrier event already seen */
31 #define RX_STATUS_RXOK (1<<21) /* success */
32 #define RX_STATUS_BCAST (1<<20) /* broadcast ok */
33 #define RX_STATUS_MCAST (1<<19) /* multicast ok */
34 #define RX_STATUS_CRCERR (1<<18) /* CRC error */
35 #define RX_STATUS_DR (1<<17) /* dribble nibble */
36 #define RX_STATUS_RCV (1<<16) /* rx code violation */
37 #define RX_STATUS_PTL (1<<15) /* pkt > 1518 bytes */
38 #define RX_STATUS_PTS (1<<14) /* pkt < 64 bytes */
39 #define RX_STATUS_LEN_MASK 0x1fff /* length mask */
40
41 #define EEPROM_LENGTH 100
42
43
44 /* Serial EEPROM interface */
45 #define EE_STATUS 0xf0
46 #define EE_CONTROL 0xf1
47 #define EE_WORD_ADDR 0xf2
48 #define EE_READ_DATA 0xf3
49 #define EE_WRITE_DATA 0xf4
50 #define EE_FEATURE_ENB 0xf5
51
52 /* Use on EE_STATUS */
53 #define EE_SEB (1<<8)
54 #define EE_SEE 1
55
56 /* Serial EEPROM commands */
57 #define EE_CONTROL_SEQ_READB (1<<4)
58 #define EE_CONTROL_RND_WRITEB (1<<5)
59 #define EE_CONTROL_RND_READB ((1<<4)|(1<<5))
60
61 /* Enable writing to serial EEPROM */
62 #define EE_WRITE_ENB 1
63
64 /* The 885 configuration register */
65 #define MAC_CONFIG 0xa0
66 #define MAC_CONFIG_SRST 1<<15
67 #define MAC_CONFIG_ITXA 1<<13
68 #define MAC_CONFIG_RXEN 1<<12
69 #define MAC_CONFIG_INTLB 1<<10
70 #define MAC_CONFIG_MODE_MASK (1<<8|1<<9)
71 #define MAC_CONFIG_MODE_TP 1<<8
72 #define MAC_CONFIG_HUGEN 1<<5
73 #define MAC_CONFIG_RETRYL 1<<4
74 #define MAC_CONFIG_CRCEN 1<<3
75 #define MAC_CONFIG_PADEN 1<<2
76 #define MAC_CONFIG_FULLD 1<<1
77 #define MAC_CONFIG_NOCFR 1<<0
78
79
80
81
82
83 #define TX_WAIT_SELECT 0x18
84 #define RX_CHANNEL_CONTROL 0x40
85
86 /* Tx channel status */
87 #define TX_DBDMA_REG 0x00
88 #define TX_CHANNEL_CONTROL 0x00
89 #define TX_CHANNEL_STATUS 0x04
90 #define TX_STATUS_RUN 1<<15
91 #define TX_STATUS_PAUSE 1<<14
92 #define TX_STATUS_WAKE 1<<12
93 #define TX_STATUS_DEAD 1<<11
94 #define TX_STATUS_ACTIVE 1<<10
95 #define TX_STATUS_BT 1<<8
96 #define TX_STATUS_TXABORT 1<<7
97 #define TX_STATUS_TXSR 1<<6
98
99 #define TX_CHANNEL_RUN TX_STATUS_RUN
100 #define TX_CHANNEL_PAUSE TX_STATUS_PAUSE
101 #define TX_CHANNEL_WAKE TX_STATUS_WAKE
102 #define TX_CHANNEL_DEAD TX_STATUS_DEAD
103 #define TX_CHANNEL_ACTIVE TX_STATUS_ACTIVE
104 #define TX_CHANNEL_BT TX_STATUS_BT
105 #define TX_CHANNEL_TXABORT TX_STATUS_TXABORT
106 #define TX_CHANNEL_TXSR TX_STATUS_TXSR
107
108 #define TX_DBDMA_ENABLE (TX_CHANNEL_WAKE | TX_CHANNEL_PAUSE | \
109 TX_CHANNEL_RUN )
110
111 /* Transmit command ptr lo register */
112 #define TX_CMD_PTR_LO 0x0c
113
114 /* Transmit interrupt select register */
115 #define TX_INT_SELECT 0x10
116
117 /* Transmit branch select register */
118 #define TX_BRANCH_SELECT 0x14
119
120 /* Transmit wait select register */
121 #define TX_WAIT_SELECT 0x18
122 #define TX_WAIT_STAT_RECV 0x40
123
124 /* Rx channel status */
125 #define RX_DBDMA_REG 0x40
126 #define RX_CHANNEL_CONTROL 0x40
127 #define RX_CHANNEL_STATUS 0x44
128 #define RX_STATUS_RUN 1<<15
129 #define RX_STATUS_PAUSE 1<<14
130 #define RX_STATUS_WAKE 1<<12
131 #define RX_STATUS_DEAD 1<<11
132 #define RX_STATUS_ACTIVE 1<<10
133 #define RX_STATUS_BT 1<<8
134 #define RX_STATUS_EOP 1<<6
135
136 #define RX_CHANNEL_RUN RX_STATUS_RUN
137 #define RX_CHANNEL_PAUSE RX_STATUS_PAUSE
138 #define RX_CHANNEL_WAKE RX_STATUS_WAKE
139 #define RX_CHANNEL_DEAD RX_STATUS_DEAD
140 #define RX_CHANNEL_ACTIVE RX_STATUS_ACTIVE
141 #define RX_CHANNEL_BT RX_STATUS_BT
142 #define RX_CHANNEL_EOP RX_STATUS_EOP
143
144 #define RX_DBDMA_ENABLE (RX_CHANNEL_WAKE | RX_CHANNEL_PAUSE | \
145 RX_CHANNEL_RUN)
146
147 /* Receive command ptr lo */
148 #define RX_CMD_PTR_LO 0x4c
149
150 /* Receive interrupt select register */
151 #define RX_INT_SELECT 0x50
152 #define RX_INT_SELECT_EOP 0x40
153
154 /* Receive branch select */
155 #define RX_BRANCH_SELECT 0x54
156 #define RX_BRANCH_SELECT_EOP 0x40
157
158 /* Receive wait select */
159 #define RX_WAIT_SELECT 0x58
160 #define RX_WAIT_SELECT_EOP 0x40
161
162 /* Event status register */
163 #define EVENT_STATUS 0x80
164 #define EVENT_TXSR 1<<2
165 #define EVENT_EOP 1<<1
166 #define EVENT_TXABORT 1<<0
167
168 /* Interrupt enable register */
169 #define INTERRUPT_ENABLE 0x82
170
171 /* Interrupt clear register */
172 #define INTERRUPT_CLEAR 0x84
173
174 /* Interrupt status register */
175 #define INTERRUPT_STATUS_REG 0x86
176
177 /* bits for the above three interrupt registers */
178 #define INTERRUPT_INTE 1<<15 /* interrupt enable */
179 #define INTERRUPT_WI 1<<9 /* wakeup interrupt */
180 #define INTERRUPT_ERI 1<<8 /* early receive interrupt */
181 #define INTERRUPT_PPET 1<<7 /* PCI Tx parity error */
182 #define INTERRUPT_PBFT 1<<6 /* PCI Tx bus fault */
183 #define INTERRUPT_IIDT 1<<5 /* illegal instruction Tx */
184 #define INTERRUPT_DIT 1<<4 /* DBDMA Tx interrupt */
185 #define INTERRUPT_PPER 1<<3 /* PCI Rx parity error */
186 #define INTERRUPT_PBFR 1<<2 /* PCI Rx bus fault */
187 #define INTERRUPT_IIDR 1<<1 /* illegal instruction Rx */
188 #define INTERRUPT_DIR 1<<0 /* DBDMA Rx interrupt */
189
190 #define INTERRUPT_TX_MASK (INTERRUPT_PBFT|INTERRUPT_IIDT| \
191 INTERRUPT_PPET|INTERRUPT_DIT)
192 #define INTERRUPT_RX_MASK (INTERRUPT_PBFR|INTERRUPT_IIDR| \
193 INTERRUPT_PPER|INTERRUPT_DIR)
194
195 /* chip revision register */
196 #define CHIP_REVISION_REG 0x8c
197 #define CHIP_PCIREV_MASK (0xf<<16)
198 #define CHIP_PCIDEV_MASK 0xff
199
200 /* Tx threshold register */
201 #define TX_THRESHOLD 0x94
202
203 /* General purpose register */
204 #define GEN_PURPOSE_REG 0x9e
205
206 /* General purpose pin control reg */
207 #define GEN_PIN_CONTROL_REG 0x9f
208
209 /* DBDMA control register */
210 #define DBDMA_CONTROL 0x90
211 #define DBDMA_SRST 1<<31
212 #define DBDMA_TDPCE 1<<23
213 #define DBDMA_BE 1<<22
214 #define DBDMA_TAP_MASK (1<<19|1<<20|1<<21)
215 #define DBDMA_RAP_MASK (1<<16|1<<17|1<<18)
216 #define DBDMA_DPMRLE 1<<15
217 #define DBDMA_WIE 1<<14
218 #define DBDMA_MP 1<<13
219 #define DBDMA_SME 1<<12
220 #define DBDMA_CME 1<<11
221 #define DBDMA_DDPE 1<<10
222 #define DBDMA_TDPE 1<<9
223 #define DBDMA_EXTE 1<<8
224 #define DBDMA_BST_MASK (1<<4|1<<5|1<<6)
225 #define DBDMA_BSR_MASK (1<<0|1<<1|1<<2)
226
227 #define DBDMA_BURST_1 (0x00)
228 #define DBDMA_BURST_2 (0x01)
229 #define DBDMA_BURST_4 (0x02)
230 #define DBDMA_BURST_8 (0x03)
231 #define DBDMA_BURST_16 (0x04)
232 #define DBDMA_BURST_32 (0x05)
233 #define DBDMA_BURST_64 (0x06)
234 #define DBDMA_BURST_128 (0x07)
235
236 #define DBDMA_TX_BST_SHIFT (4)
237 #define DBDMA_RX_BST_SHIFT (0)
238
239 #define DBDMA_TX_ARBITRATION_DEFAULT ( 1 << 19 )
240 #define DBDMA_RX_ARBITRATION_DEFAULT ( 2 << 16 )
241
242
243 /* Back-to-back interpacket gap register */
244 #define BTOB_INTP_GAP 0xa2
245 #define BTOB_INTP_DEFAULT 0x18
246
247 /* Non-back-to-back interpacket gap register */
248 #define NBTOB_INTP_GAP 0xa4
249
250 /* MIIM command register */
251 #define MIIM_COMMAND 0xa6
252 #define MIIM_SCAN 1<<1
253 #define MIIM_RSTAT 1<<0
254
255 /* MII address register */
256 #define MII_ADDRESS 0xa8
257 #define MII_FIAD_MASK (1<<8|1<<9|1<<10|1<<11|1<<12)
258 #define MII_RGAD_MASK (1<<0|1<<1|1<<2|1<<3|1<<4)
259
260 #define TPPMD_CONTROL_REG 0xa8
261 #define TPPMD_FO 1<<1
262 #define TPPMD_LB 1<<0
263
264 /* MII read and write registers */
265 #define MII_WRITE_DATA 0xaa
266 #define MII_READ_DATA 0xac
267
268 /* MII indicators */
269 #define MII_INDICATOR 0xae
270 #define MII_NVALID 1<<2
271 #define MII_SCAN 1<<1
272 #define MII_BUSY 1<<0
273
274 /* Address filter */
275 #define ADDRESS_FILTER 0xd0
276 #define ADDRESS_RPPRM 1<<3 /* multicast promis. mode */
277 #define ADDRESS_RPPRO 1<<2 /* promiscuous mode */
278 #define ADDRESS_RPAMC 1<<1 /* accept multicasts */
279 #define ADDRESS_RPABC 1<<0 /* accept broadcasts */
280
281 /* Station addresses
282
283 Note that if the serial EEPROM is disabled, these values are all
284 zero. If, like us, you get the chips when they're fresh, they're
285 also zero and you have to initialize the address */
286 #define STATION_ADDRESS_0 0xd2
287 #define STATION_ADDRESS_1 0xd4
288 #define STATION_ADDRESS_2 0xd6
289
290 /* Hash tables */
291 #define HASH_TABLE_0 0xd8
292 #define HASH_TABLE_1 0xda
293 #define HASH_TABLE_2 0xdc
294 #define HASH_TABLE_3 0xde
295
296 /* PHY indentifiers */
297 #define PHY_IDENTIFIER_0 0xe4
298 #define PHY_IDENTIFIER_1 0xe6
299
300 /* MII Auto-negotiation register definitions */
301
302 #define MII_AUTO_NEGOTIATION_CONTROL (0x0000)
303 #define MANC_PHY_RESET (0x8000)
304 #define MANC_PHY_LOOPBACK_ENABLE (0x4000)
305 #define MANC_PHY_LOOPBACK_DISABLE (0x0000)
306 #define MANC_PHY_SPEED_100 (0x2000)
307 #define MANC_PHY_SPEED_10 (0x0000)
308 #define MANC_AUTO_NEGOTIATION_ENABLE (0x1000)
309 #define MANC_AUTO_NEGOTIATION_DISABLE (0x0000)
310 #define MANC_PHY_POWER_DOWN (0x0800)
311 #define MANC_PHY_POWER_UP (0x0000)
312 #define MANC_ISOLATE_ENABLE (0x0400)
313 #define MANC_ISOLATE_DISABLE (0x0000)
314 #define MANC_RESTART_AUTO_NEGOTIATION (0x0200)
315 #define MANC_FULL_DUPLEX (0x0100)
316 #define MANC_HALF_DUPLEX (0x0000)
317
318 #define MII_AUTO_NEGOTIATION_STATUS (0x0001)
319 #define MANS_100BASE_T4_HALF_DUPLEX (0x8000)
320 #define MANS_100BASE_X_FULL_DUPLEX (0x4000)
321 #define MANS_100BASE_X_HALF_DUPLEX (0x2000)
322 #define MANS_10MBS_FULL_DUPLEX (0x1000)
323 #define MANS_10MBS_HALF_DUPLEX (0x0800)
324 #define MANS_AUTO_NEGOTIATION_COMPLETE (0x0020)
325 #define MANS_REMOTE_FAULT (0x0010)
326 #define MANS_AUTO_NEGOTIATION_ABILITY (0x0008)
327 #define MANS_LINK_STATUS (0x0004)
328 #define MANS_JABBER_DETECT (0x0002)
329 #define MANS_EXTENDED_CAPABILITY (0x0001)
330
331 #define MII_PHY_IDENTIFIER_1 (0x0002)
332 #define MII_PHY_IDENTIFIER_2 (0x0003)
333
334 #define MII_AUTO_NEGOTIATION_ADVERTISEMENT (0x0004)
335 #define MANA_NEXT_PAGE (0x8000)
336 #define MANA_REMOTE_FAULT (0x2000)
337 #define MANA_TECHNOLOGY_ABILITY_MASK (0x1FE0)
338 #define MANATECH_10BASET_HALF_DUPLEX (0x0020)
339 #define MANATECH_10BASET_FULL_DUPLEX (0x0040)
340 #define MANATECH_100BASETX_HALF_DUPLEX (0x0080)
341 #define MANATECH_100BASETX_FULL_DUPLEX (0x0100)
342 #define MANATECH_100BASET4 (0x0200)
343 #define MANA_SELECTOR_MASK (0x001F)
344 #define MANASELECTOR_802_3 (0x0001)
345
346 #define MII_AUTO_NEGOTIATION_LINK_PARTNER (0x0005)
347 #define MANLP_NEXT_PAGE (0x8000)
348 #define MANLP_ACKNOWLEDGE (0x4000)
349 #define MANLP_REMOTE_FAULT (0x2000)
350 #define MANLP_TECHNOLOGY_ABILITY_MASK (0x1FE0)
351 #define MANLP_SELECTOR_MASK (0x001F)
352
353 #define MII_AUTO_NEGOTIATION_EXPANSION (0x0006)
354 #define MANE_PARALLEL_DETECTION_FAULT (0x0010)
355 #define MANE_LINK_PARTNER_NEXT_PAGE_ABLE (0x0008)
356 #define MANE_NEXT_PAGE_ABLE (0x0004)
357 #define MANE_PAGE_RECEIVED (0x0002)
358 #define MANE_LINK_PARTNER_AUTO_ABLE (0x0001)
359
360 #define MII_AUTO_NEGOTIATION_NEXT_PAGE_TRANSMIT (0x0007)
361 #define MANNPT_NEXT_PAGE (0x8000)
362 #define MANNPT_MESSAGE_PAGE (0x2000)
363 #define MANNPT_ACKNOWLEDGE_2 (0x1000)
364 #define MANNPT_TOGGLE (0x0800)
365 #define MANNPT_MESSAGE_FIELD_MASK (0x07FF)
366
367 #endif
368
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