1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15
16 static const char *version = "pcnet32.c:v1.25kf 26.9.1999 tsbogend@alpha.franken.de\n";
17
18 #include <linux/module.h>
19
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/malloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <asm/bitops.h>
32 #include <asm/io.h>
33 #include <asm/dma.h>
34
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39
40 static unsigned int pcnet32_portlist[] __initdata = {0x300, 0x320, 0x340, 0x360, 0};
41
42 static int pcnet32_debug = 1;
43 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
44
45 static struct net_device *pcnet32_dev;
46
47 static const int max_interrupt_work = 80;
48 static const int rx_copybreak = 200;
49
50 #define PORT_AUI 0x00
51 #define PORT_10BT 0x01
52 #define PORT_GPSI 0x02
53 #define PORT_MII 0x03
54
55 #define PORT_PORTSEL 0x03
56 #define PORT_ASEL 0x04
57 #define PORT_100 0x40
58 #define PORT_FD 0x80
59
60 #define PCNET32_DMA_MASK 0xffffffff
61
62 /*
63 * table to translate option values from tulip
64 * to internal options
65 */
66 static unsigned char options_mapping[] = {
67 PORT_ASEL, /* 0 Auto-select */
68 PORT_AUI, /* 1 BNC/AUI */
69 PORT_AUI, /* 2 AUI/BNC */
70 PORT_ASEL, /* 3 not supported */
71 PORT_10BT | PORT_FD, /* 4 10baseT-FD */
72 PORT_ASEL, /* 5 not supported */
73 PORT_ASEL, /* 6 not supported */
74 PORT_ASEL, /* 7 not supported */
75 PORT_ASEL, /* 8 not supported */
76 PORT_MII, /* 9 MII 10baseT */
77 PORT_MII | PORT_FD, /* 10 MII 10baseT-FD */
78 PORT_MII, /* 11 MII (autosel) */
79 PORT_10BT, /* 12 10BaseT */
80 PORT_MII | PORT_100, /* 13 MII 100BaseTx */
81 PORT_MII | PORT_100 | PORT_FD, /* 14 MII 100BaseTx-FD */
82 PORT_ASEL /* 15 not supported */
83 };
84
85 #define MAX_UNITS 8
86 static int options[MAX_UNITS];
87 static int full_duplex[MAX_UNITS];
88
89 /*
90 * Theory of Operation
91 *
92 * This driver uses the same software structure as the normal lance
93 * driver. So look for a verbose description in lance.c. The differences
94 * to the normal lance driver is the use of the 32bit mode of PCnet32
95 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
96 * 16MB limitation and we don't need bounce buffers.
97 */
98
99 /*
100 * History:
101 * v0.01: Initial version
102 * only tested on Alpha Noname Board
103 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
104 * tested on a ASUS SP3G
105 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
106 * looks like the 974 doesn't like stopping and restarting in a
107 * short period of time; now we do a reinit of the lance; the
108 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
109 * and hangs the machine (thanks to Klaus Liedl for debugging)
110 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
111 * made it standalone (no need for lance.c)
112 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
113 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
114 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
115 * v0.15: added 79C965 (VLB) probe
116 * added interrupt sharing for PCI chips
117 * v0.16: fixed set_multicast_list on Alpha machines
118 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
119 * v0.19: changed setting of autoselect bit
120 * v0.20: removed additional Compaq PCI probe; there is now a working one
121 * in arch/i386/bios32.c
122 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
123 * v0.22: added printing of status to ring dump
124 * v0.23: changed enet_statistics to net_devive_stats
125 * v0.90: added multicast filter
126 * added module support
127 * changed irq probe to new style
128 * added PCnetFast chip id
129 * added fix for receive stalls with Intel saturn chipsets
130 * added in-place rx skbs like in the tulip driver
131 * minor cleanups
132 * v0.91: added PCnetFast+ chip id
133 * back port to 2.0.x
134 * v1.00: added some stuff from Donald Becker's 2.0.34 version
135 * added support for byte counters in net_dev_stats
136 * v1.01: do ring dumps, only when debugging the driver
137 * increased the transmit timeout
138 * v1.02: fixed memory leak in pcnet32_init_ring()
139 * v1.10: workaround for stopped transmitter
140 * added port selection for modules
141 * detect special T1/E1 WAN card and setup port selection
142 * v1.11: fixed wrong checking of Tx errors
143 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
144 * added save original kmalloc addr for freeing (mcr@solidum.com)
145 * added support for PCnetHome chip (joe@MIT.EDU)
146 * rewritten PCI card detection
147 * added dwio mode to get driver working on some PPC machines
148 * v1.21: added mii selection and mii ioctl
149 * v1.22: changed pci scanning code to make PPC people happy
150 * fixed switching to 32bit mode in pcnet32_open() (thanks
151 * to Michael Richard <mcr@solidum.com> for noticing this one)
152 * added sub vendor/device id matching (thanks again to
153 * Michael Richard <mcr@solidum.com>)
154 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
155 * v1.23 fixed small bug, when manual selecting MII speed/duplex
156 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
157 * underflows. Added tx_start_pt module parameter. Increased
158 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
159 * for FAST[+] chipsets. <kaf@fc.hp.com>
160 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
161 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
162 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
163 * <jamey@crl.dec.com>
164 */
165
166
167 /*
168 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
169 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
170 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
171 */
172 #ifndef PCNET32_LOG_TX_BUFFERS
173 #define PCNET32_LOG_TX_BUFFERS 4
174 #define PCNET32_LOG_RX_BUFFERS 5
175 #endif
176
177 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
178 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
179 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
180
181 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
182 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
183 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
184
185 #define PKT_BUF_SZ 1544
186
187 /* Offsets from base I/O address. */
188 #define PCNET32_WIO_RDP 0x10
189 #define PCNET32_WIO_RAP 0x12
190 #define PCNET32_WIO_RESET 0x14
191 #define PCNET32_WIO_BDP 0x16
192
193 #define PCNET32_DWIO_RDP 0x10
194 #define PCNET32_DWIO_RAP 0x14
195 #define PCNET32_DWIO_RESET 0x18
196 #define PCNET32_DWIO_BDP 0x1C
197
198 #define PCNET32_TOTAL_SIZE 0x20
199
200 /* some PCI ids */
201 #ifndef PCI_DEVICE_ID_AMD_LANCE
202 #define PCI_VENDOR_ID_AMD 0x1022
203 #define PCI_DEVICE_ID_AMD_LANCE 0x2000
204 #endif
205 #ifndef PCI_DEVICE_ID_AMD_PCNETHOME
206 #define PCI_DEVICE_ID_AMD_PCNETHOME 0x2001
207 #endif
208
209
210 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
211
212 /* The PCNET32 Rx and Tx ring descriptors. */
213 struct pcnet32_rx_head {
214 u32 base;
215 s16 buf_length;
216 s16 status;
217 u32 msg_length;
218 u32 reserved;
219 };
220
221 struct pcnet32_tx_head {
222 u32 base;
223 s16 length;
224 s16 status;
225 u32 misc;
226 u32 reserved;
227 };
228
229 /* The PCNET32 32-Bit initialization block, described in databook. */
230 struct pcnet32_init_block {
231 u16 mode;
232 u16 tlen_rlen;
233 u8 phys_addr[6];
234 u16 reserved;
235 u32 filter[2];
236 /* Receive and transmit ring base, along with extra bits. */
237 u32 rx_ring;
238 u32 tx_ring;
239 };
240
241 /* PCnet32 access functions */
242 struct pcnet32_access {
243 u16 (*read_csr)(unsigned long, int);
244 void (*write_csr)(unsigned long, int, u16);
245 u16 (*read_bcr)(unsigned long, int);
246 void (*write_bcr)(unsigned long, int, u16);
247 u16 (*read_rap)(unsigned long);
248 void (*write_rap)(unsigned long, u16);
249 void (*reset)(unsigned long);
250 };
251
252 /*
253 * The first three fields of pcnet32_private are read by the ethernet device
254 * so we allocate the structure should be allocated by pci_alloc_consistent().
255 */
256 struct pcnet32_private {
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
259 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
260 struct pcnet32_init_block init_block;
261 dma_addr_t dma_addr; /* DMA address of beginning of this object, returned by pci_alloc_consistent */
262 struct pci_dev *pci_dev; /* Pointer to the associated pci device structure */
263 const char *name;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff *tx_skbuff[TX_RING_SIZE];
266 struct sk_buff *rx_skbuff[RX_RING_SIZE];
267 dma_addr_t tx_dma_addr[TX_RING_SIZE];
268 dma_addr_t rx_dma_addr[RX_RING_SIZE];
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
273 struct net_device_stats stats;
274 char tx_full;
275 int options;
276 int shared_irq:1, /* shared irq possible */
277 ltint:1,
278 #ifdef DO_DXSUFLO
279 dxsuflo:1, /* disable transmit stop on uflo */
280 #endif
281 full_duplex:1, /* full duplex possible */
282 mii:1; /* mii port available */
283 struct net_device *next;
284 };
285
286 static int pcnet32_probe_vlbus(int cards_found);
287 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
288 static int pcnet32_probe1(unsigned long, unsigned char, int, int, struct pci_dev *);
289 static int pcnet32_open(struct net_device *);
290 static int pcnet32_init_ring(struct net_device *);
291 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
292 static int pcnet32_rx(struct net_device *);
293 static void pcnet32_tx_timeout (struct net_device *dev);
294 static void pcnet32_interrupt(int, void *, struct pt_regs *);
295 static int pcnet32_close(struct net_device *);
296 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
297 static void pcnet32_set_multicast_list(struct net_device *);
298 #ifdef HAVE_PRIVATE_IOCTL
299 static int pcnet32_mii_ioctl(struct net_device *, struct ifreq *, int);
300 #endif
301
302 enum pci_flags_bit {
303 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
304 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
305 };
306
307 struct pcnet32_pci_id_info {
308 const char *name;
309 u16 vendor_id, device_id, svid, sdid, flags;
310 int io_size;
311 int (*probe1) (unsigned long, unsigned char, int, int, struct pci_dev *);
312 };
313
314
315 /*
316 * PCI device identifiers for "new style" Linux PCI Device Drivers
317 */
318 static struct pci_device_id pcnet32_pci_tbl[] __devinitdata = {
319 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PCNETHOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
320 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
321 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, 0x1014, 0x2000, 0, 0, 0 },
322 { 0, }
323 };
324
325 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
326
327 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
328 {
329 outw (index, addr+PCNET32_WIO_RAP);
330 return inw (addr+PCNET32_WIO_RDP);
331 }
332
333 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
334 {
335 outw (index, addr+PCNET32_WIO_RAP);
336 outw (val, addr+PCNET32_WIO_RDP);
337 }
338
339 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
340 {
341 outw (index, addr+PCNET32_WIO_RAP);
342 return inw (addr+PCNET32_WIO_BDP);
343 }
344
345 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
346 {
347 outw (index, addr+PCNET32_WIO_RAP);
348 outw (val, addr+PCNET32_WIO_BDP);
349 }
350
351 static u16 pcnet32_wio_read_rap (unsigned long addr)
352 {
353 return inw (addr+PCNET32_WIO_RAP);
354 }
355
356 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
357 {
358 outw (val, addr+PCNET32_WIO_RAP);
359 }
360
361 static void pcnet32_wio_reset (unsigned long addr)
362 {
363 inw (addr+PCNET32_WIO_RESET);
364 }
365
366 static int pcnet32_wio_check (unsigned long addr)
367 {
368 outw (88, addr+PCNET32_WIO_RAP);
369 return (inw (addr+PCNET32_WIO_RAP) == 88);
370 }
371
372 static struct pcnet32_access pcnet32_wio = {
373 pcnet32_wio_read_csr,
374 pcnet32_wio_write_csr,
375 pcnet32_wio_read_bcr,
376 pcnet32_wio_write_bcr,
377 pcnet32_wio_read_rap,
378 pcnet32_wio_write_rap,
379 pcnet32_wio_reset
380 };
381
382 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
383 {
384 outl (index, addr+PCNET32_DWIO_RAP);
385 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
386 }
387
388 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
389 {
390 outl (index, addr+PCNET32_DWIO_RAP);
391 outl (val, addr+PCNET32_DWIO_RDP);
392 }
393
394 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
395 {
396 outl (index, addr+PCNET32_DWIO_RAP);
397 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
398 }
399
400 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
401 {
402 outl (index, addr+PCNET32_DWIO_RAP);
403 outl (val, addr+PCNET32_DWIO_BDP);
404 }
405
406 static u16 pcnet32_dwio_read_rap (unsigned long addr)
407 {
408 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
409 }
410
411 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
412 {
413 outl (val, addr+PCNET32_DWIO_RAP);
414 }
415
416 static void pcnet32_dwio_reset (unsigned long addr)
417 {
418 inl (addr+PCNET32_DWIO_RESET);
419 }
420
421 static int pcnet32_dwio_check (unsigned long addr)
422 {
423 outl (88, addr+PCNET32_DWIO_RAP);
424 return (inl (addr+PCNET32_DWIO_RAP) == 88);
425 }
426
427 static struct pcnet32_access pcnet32_dwio = {
428 pcnet32_dwio_read_csr,
429 pcnet32_dwio_write_csr,
430 pcnet32_dwio_read_bcr,
431 pcnet32_dwio_write_bcr,
432 pcnet32_dwio_read_rap,
433 pcnet32_dwio_write_rap,
434 pcnet32_dwio_reset
435
436 };
437
438
439
440 /* only probes for non-PCI devices, the rest are handled by pci_register_driver via pcnet32_probe_pci*/
441 static int __init pcnet32_probe_vlbus(int cards_found)
442 {
443 unsigned long ioaddr = 0; // FIXME dev ? dev->base_addr: 0;
444 unsigned int irq_line = 0; // FIXME dev ? dev->irq : 0;
445 int *port;
446
447 printk(KERN_INFO "pcnet32_probe_vlbus: cards_found=%d\n", cards_found);
448 #ifndef __powerpc__
449 if (ioaddr > 0x1ff) {
450 if (check_region(ioaddr, PCNET32_TOTAL_SIZE) == 0)
451 return pcnet32_probe1(ioaddr, irq_line, 0, 0, NULL);
452 else
453 return -ENODEV;
454 } else
455 #endif
456 if (ioaddr != 0)
457 return -ENXIO;
458
459 /* now look for PCnet32 VLB cards */
460 for (port = pcnet32_portlist; *port; port++) {
461 unsigned long ioaddr = *port;
462
463 if ( check_region(ioaddr, PCNET32_TOTAL_SIZE) == 0) {
464 /* check if there is really a pcnet chip on that ioaddr */
465 if ((inb(ioaddr + 14) == 0x57) &&
466 (inb(ioaddr + 15) == 0x57) &&
467 (pcnet32_probe1(ioaddr, 0, 0, 0, NULL) == 0))
468 cards_found++;
469 }
470 }
471 return cards_found ? 0: -ENODEV;
472 }
473
474
475
476 static int __init
477 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
478 {
479 static int card_idx;
480 long ioaddr;
481 int err = 0;
482
483 printk(KERN_INFO "pcnet32_probe_pci: found device %#08x.%#08x\n", ent->vendor, ent->device);
484
485 ioaddr = pci_resource_start (pdev, 0);
486 printk(KERN_INFO " ioaddr=%#08lx resource_flags=%#08lx\n", ioaddr, pci_resource_flags (pdev, 0));
487 if (!ioaddr) {
488 printk (KERN_ERR "no PCI IO resources, aborting\n");
489 return -ENODEV;
490 }
491
492 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
493 printk(KERN_ERR "pcnet32.c: architecture does not support 32bit PCI busmaster DMA\n");
494 return -ENODEV;
495 }
496
497 if ((err = pci_enable_device(pdev)) < 0) {
498 printk(KERN_ERR "pcnet32.c: failed to enable device -- err=%d\n", err);
499 return err;
500 }
501
502 pci_set_master(pdev);
503
504 return pcnet32_probe1(ioaddr, pdev->irq, 1, card_idx, pdev);
505 }
506
507
508 /* pcnet32_probe1
509 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
510 * pdev will be NULL when called from pcnet32_probe_vlbus.
511 */
512 static int __init
513 pcnet32_probe1(unsigned long ioaddr, unsigned char irq_line, int shared, int card_idx, struct pci_dev *pdev)
514 {
515 struct pcnet32_private *lp;
516 dma_addr_t lp_dma_addr;
517 int i,media,fdx = 0, mii = 0, fset = 0;
518 #ifdef DO_DXSUFLO
519 int dxsuflo = 0;
520 #endif
521 int ltint = 0;
522 int chip_version;
523 char *chipname;
524 struct net_device *dev;
525 struct pcnet32_access *a = NULL;
526
527 /* reset the chip */
528 pcnet32_dwio_reset(ioaddr);
529 pcnet32_wio_reset(ioaddr);
530
531 if (pcnet32_wio_read_csr (ioaddr, 0) == 4 && pcnet32_wio_check (ioaddr)) {
532 a = &pcnet32_wio;
533 } else {
534 if (pcnet32_dwio_read_csr (ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
535 a = &pcnet32_dwio;
536 } else
537 return -ENODEV;
538 }
539
540 chip_version = a->read_csr (ioaddr, 88) | (a->read_csr (ioaddr,89) << 16);
541 if (pcnet32_debug > 2)
542 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
543 if ((chip_version & 0xfff) != 0x003)
544 return -ENODEV;
545 chip_version = (chip_version >> 12) & 0xffff;
546 switch (chip_version) {
547 case 0x2420:
548 chipname = "PCnet/PCI 79C970"; /* PCI */
549 break;
550 case 0x2430:
551 if (shared)
552 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
553 else
554 chipname = "PCnet/32 79C965"; /* 486/VL bus */
555 break;
556 case 0x2621:
557 chipname = "PCnet/PCI II 79C970A"; /* PCI */
558 fdx = 1;
559 break;
560 case 0x2623:
561 chipname = "PCnet/FAST 79C971"; /* PCI */
562 fdx = 1; mii = 1; fset = 1;
563 ltint = 1;
564 break;
565 case 0x2624:
566 chipname = "PCnet/FAST+ 79C972"; /* PCI */
567 fdx = 1; mii = 1; fset = 1;
568 break;
569 case 0x2625:
570 chipname = "PCnet/FAST III 79C973"; /* PCI */
571 fdx = 1; mii = 1;
572 break;
573 case 0x2626:
574 chipname = "PCnet/Home 79C978"; /* PCI */
575 fdx = 1;
576 /*
577 * This is based on specs published at www.amd.com. This section
578 * assumes that a card with a 79C978 wants to go into 1Mb HomePNA
579 * mode. The 79C978 can also go into standard ethernet, and there
580 * probably should be some sort of module option to select the
581 * mode by which the card should operate
582 */
583 /* switch to home wiring mode */
584 media = a->read_bcr (ioaddr, 49);
585 #if 0
586 if (pcnet32_debug > 2)
587 printk(KERN_DEBUG "pcnet32: pcnet32 media value %#x.\n", media);
588 media &= ~3;
589 media |= 1;
590 #endif
591 if (pcnet32_debug > 2)
592 printk(KERN_DEBUG "pcnet32: pcnet32 media reset to %#x.\n", media);
593 a->write_bcr (ioaddr, 49, media);
594 break;
595 case 0x2627:
596 chipname = "PCnet/FAST III 79C975"; /* PCI */
597 fdx = 1; mii = 1;
598 break;
599 default:
600 printk(KERN_INFO "pcnet32: PCnet version %#x, no PCnet32 chip.\n",chip_version);
601 return -ENODEV;
602 }
603
604 /*
605 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
606 * starting until the packet is loaded. Strike one for reliability, lose
607 * one for latency - although on PCI this isnt a big loss. Older chips
608 * have FIFO's smaller than a packet, so you can't do this.
609 */
610
611 if(fset)
612 {
613 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0800));
614 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
615 #ifdef DO_DXSUFLO
616 dxsuflo = 1;
617 #endif
618 ltint = 1;
619 }
620
621 dev = init_etherdev(NULL, 0);
622 if(dev==NULL)
623 return -ENOMEM;
624
625 printk(KERN_INFO "%s: %s at %#3lx,", dev->name, chipname, ioaddr);
626
627 /* There is a 16 byte station address PROM at the base address.
628 The first six bytes are the station address. */
629 for (i = 0; i < 6; i++)
630 printk(" %2.2x", dev->dev_addr[i] = inb(ioaddr + i));
631
632 if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
633 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
634 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
635 switch(i>>10) {
636 case 0: printk(" 20 bytes,"); break;
637 case 1: printk(" 64 bytes,"); break;
638 case 2: printk(" 128 bytes,"); break;
639 case 3: printk("~220 bytes,"); break;
640 }
641 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
642 printk(" BCR18(%x):",i&0xffff);
643 if (i & (1<<5)) printk("BurstWrEn ");
644 if (i & (1<<6)) printk("BurstRdEn ");
645 if (i & (1<<7)) printk("DWordIO ");
646 if (i & (1<<11)) printk("NoUFlow ");
647 i = a->read_bcr(ioaddr, 25);
648 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
649 i = a->read_bcr(ioaddr, 26);
650 printk(" SRAM_BND=0x%04x,",i<<8);
651 i = a->read_bcr(ioaddr, 27);
652 if (i & (1<<14)) printk("LowLatRx");
653 }
654
655 dev->base_addr = ioaddr;
656 request_region(ioaddr, PCNET32_TOTAL_SIZE, chipname);
657
658 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
659 if ((lp = (struct pcnet32_private *)pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL)
660 return -ENOMEM;
661
662 memset(lp, 0, sizeof(*lp));
663 lp->dma_addr = lp_dma_addr;
664 lp->pci_dev = pdev;
665 printk("\n" KERN_INFO "pcnet32: pcnet32_private lp=%p lp_dma_addr=%#08x", lp, lp_dma_addr);
666
667 spin_lock_init(&lp->lock);
668
669 dev->priv = lp;
670 lp->name = chipname;
671 lp->shared_irq = shared;
672 lp->full_duplex = fdx;
673 #ifdef DO_DXSUFLO
674 lp->dxsuflo = dxsuflo;
675 #endif
676 lp->ltint = ltint;
677 lp->mii = mii;
678 if (options[card_idx] > sizeof (options_mapping))
679 lp->options = PORT_ASEL;
680 else
681 lp->options = options_mapping[options[card_idx]];
682
683 if (fdx && !(lp->options & PORT_ASEL) && full_duplex[card_idx])
684 lp->options |= PORT_FD;
685
686 if (a == NULL) {
687 printk(KERN_ERR "pcnet32: No access methods\n");
688 return -ENODEV;
689 }
690 lp->a = *a;
691
692 /* detect special T1/E1 WAN card by checking for MAC address */
693 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && dev->dev_addr[2] == 0x75)
694 lp->options = PORT_FD | PORT_GPSI;
695
696 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
697 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
698 for (i = 0; i < 6; i++)
699 lp->init_block.phys_addr[i] = dev->dev_addr[i];
700 lp->init_block.filter[0] = 0x00000000;
701 lp->init_block.filter[1] = 0x00000000;
702 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
703 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
704
705 /* switch pcnet32 to 32bit mode */
706 a->write_bcr (ioaddr, 20, 2);
707
708 a->write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) & 0xffff);
709 a->write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
710
711 if (irq_line) {
712 dev->irq = irq_line;
713 }
714
715 if (dev->irq >= 2)
716 printk(" assigned IRQ %d.\n", dev->irq);
717 else {
718 unsigned long irq_mask = probe_irq_on();
719
720 /*
721 * To auto-IRQ we enable the initialization-done and DMA error
722 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
723 * boards will work.
724 */
725 /* Trigger an initialization just for the interrupt. */
726 a->write_csr (ioaddr, 0, 0x41);
727 mdelay (1);
728
729 dev->irq = probe_irq_off (irq_mask);
730 if (dev->irq)
731 printk(", probed IRQ %d.\n", dev->irq);
732 else {
733 printk(", failed to detect IRQ line.\n");
734 return -ENODEV;
735 }
736 }
737
738 if (pcnet32_debug > 0)
739 printk(KERN_INFO "%s", version);
740
741 /* The PCNET32-specific entries in the device structure. */
742 dev->open = &pcnet32_open;
743 dev->hard_start_xmit = &pcnet32_start_xmit;
744 dev->stop = &pcnet32_close;
745 dev->get_stats = &pcnet32_get_stats;
746 dev->set_multicast_list = &pcnet32_set_multicast_list;
747 #ifdef HAVE_PRIVATE_IOCTL
748 dev->do_ioctl = &pcnet32_mii_ioctl;
749 #endif
750 dev->tx_timeout = pcnet32_tx_timeout;
751 dev->watchdog_timeo = (HZ >> 1);
752
753 lp->next = pcnet32_dev;
754 pcnet32_dev = dev;
755
756 /* Fill in the generic fields of the device structure. */
757 ether_setup(dev);
758 return 0;
759 }
760
761
762 static int
763 pcnet32_open(struct net_device *dev)
764 {
765 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
766 unsigned long ioaddr = dev->base_addr;
767 u16 val;
768 int i;
769
770 if (dev->irq == 0 ||
771 request_irq(dev->irq, &pcnet32_interrupt,
772 lp->shared_irq ? SA_SHIRQ : 0, lp->name, (void *)dev)) {
773 return -EAGAIN;
774 }
775
776 /* Reset the PCNET32 */
777 lp->a.reset (ioaddr);
778
779 /* switch pcnet32 to 32bit mode */
780 lp->a.write_bcr (ioaddr, 20, 2);
781
782 if (pcnet32_debug > 1)
783 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
784 dev->name, dev->irq,
785 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
786 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
787 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
788
789 /* set/reset autoselect bit */
790 val = lp->a.read_bcr (ioaddr, 2) & ~2;
791 if (lp->options & PORT_ASEL)
792 val |= 2;
793 lp->a.write_bcr (ioaddr, 2, val);
794
795 /* handle full duplex setting */
796 if (lp->full_duplex) {
797 val = lp->a.read_bcr (ioaddr, 9) & ~3;
798 if (lp->options & PORT_FD) {
799 val |= 1;
800 if (lp->options == (PORT_FD | PORT_AUI))
801 val |= 2;
802 }
803 lp->a.write_bcr (ioaddr, 9, val);
804 }
805
806 /* set/reset GPSI bit in test register */
807 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
808 if ((lp->options & PORT_PORTSEL) == PORT_GPSI)
809 val |= 0x10;
810 lp->a.write_csr (ioaddr, 124, val);
811
812 if (lp->mii & !(lp->options & PORT_ASEL)) {
813 val = lp->a.read_bcr (ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
814 if (lp->options & PORT_FD)
815 val |= 0x10;
816 if (lp->options & PORT_100)
817 val |= 0x08;
818 lp->a.write_bcr (ioaddr, 32, val);
819 }
820
821 #ifdef DO_DXSUFLO
822 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
823 val = lp->a.read_csr (ioaddr, 3);
824 val |= 0x40;
825 lp->a.write_csr (ioaddr, 3, val);
826 }
827 #endif
828 if (lp->ltint) { /* Enable TxDone-intr inhibitor */
829 val = lp->a.read_csr (ioaddr, 5);
830 val |= (1<<14);
831 lp->a.write_csr (ioaddr, 5, val);
832 }
833
834 lp->init_block.mode = le16_to_cpu((lp->options & PORT_PORTSEL) << 7);
835 lp->init_block.filter[0] = 0x00000000;
836 lp->init_block.filter[1] = 0x00000000;
837 if (pcnet32_init_ring(dev))
838 return -ENOMEM;
839
840 /* Re-initialize the PCNET32, and start it when done. */
841 lp->a.write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) &0xffff);
842 lp->a.write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
843
844 lp->a.write_csr (ioaddr, 4, 0x0915);
845 lp->a.write_csr (ioaddr, 0, 0x0001);
846
847 netif_start_queue(dev);
848
849 i = 0;
850 while (i++ < 100)
851 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
852 break;
853 /*
854 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
855 * reports that doing so triggers a bug in the '974.
856 */
857 lp->a.write_csr (ioaddr, 0, 0x0042);
858
859 if (pcnet32_debug > 2)
860 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
861 dev->name, i, (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)),
862 lp->a.read_csr (ioaddr, 0));
863
864
865 MOD_INC_USE_COUNT;
866
867 return 0; /* Always succeed */
868 }
869
870 /*
871 * The LANCE has been halted for one reason or another (busmaster memory
872 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
873 * etc.). Modern LANCE variants always reload their ring-buffer
874 * configuration when restarted, so we must reinitialize our ring
875 * context before restarting. As part of this reinitialization,
876 * find all packets still on the Tx ring and pretend that they had been
877 * sent (in effect, drop the packets on the floor) - the higher-level
878 * protocols will time out and retransmit. It'd be better to shuffle
879 * these skbs to a temp list and then actually re-Tx them after
880 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
881 */
882
883 static void
884 pcnet32_purge_tx_ring(struct net_device *dev)
885 {
886 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
887 int i;
888
889 for (i = 0; i < TX_RING_SIZE; i++) {
890 if (lp->tx_skbuff[i]) {
891 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
892 dev_kfree_skb(lp->tx_skbuff[i]);
893 lp->tx_skbuff[i] = NULL;
894 lp->tx_dma_addr[i] = 0;
895 }
896 }
897 }
898
899
900 /* Initialize the PCNET32 Rx and Tx rings. */
901 static int
902 pcnet32_init_ring(struct net_device *dev)
903 {
904 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
905 int i;
906
907 lp->tx_full = 0;
908 lp->cur_rx = lp->cur_tx = 0;
909 lp->dirty_rx = lp->dirty_tx = 0;
910
911 for (i = 0; i < RX_RING_SIZE; i++) {
912 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
913 if (rx_skbuff == NULL) {
914 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
915 /* there is not much, we can do at this point */
916 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",dev->name);
917 return -1;
918 }
919 skb_reserve (rx_skbuff, 2);
920 }
921 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail, rx_skbuff->len, PCI_DMA_FROMDEVICE);
922 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
923 lp->rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
924 lp->rx_ring[i].status = le16_to_cpu(0x8000);
925 }
926 /* The Tx buffer address is filled in as needed, but we do need to clear
927 the upper ownership bit. */
928 for (i = 0; i < TX_RING_SIZE; i++) {
929 lp->tx_ring[i].base = 0;
930 lp->tx_ring[i].status = 0;
931 lp->tx_dma_addr[i] = 0;
932 }
933
934 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
935 for (i = 0; i < 6; i++)
936 lp->init_block.phys_addr[i] = dev->dev_addr[i];
937 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
938 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
939 return 0;
940 }
941
942 static void
943 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
944 {
945 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
946 unsigned long ioaddr = dev->base_addr;
947 int i;
948
949 pcnet32_purge_tx_ring(dev);
950 if (pcnet32_init_ring(dev))
951 return;
952
953 /* ReInit Ring */
954 lp->a.write_csr (ioaddr, 0, 1);
955 i = 0;
956 while (i++ < 100)
957 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
958 break;
959
960 lp->a.write_csr (ioaddr, 0, csr0_bits);
961 }
962
963
964 static void
965 pcnet32_tx_timeout (struct net_device *dev)
966 {
967 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
968 unsigned int ioaddr = dev->base_addr;
969
970 /* Transmitter timeout, serious problems. */
971 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
972 dev->name, lp->a.read_csr (ioaddr, 0));
973 lp->a.write_csr (ioaddr, 0, 0x0004);
974 lp->stats.tx_errors++;
975 if (pcnet32_debug > 2) {
976 int i;
977 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
978 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
979 lp->cur_rx);
980 for (i = 0 ; i < RX_RING_SIZE; i++)
981 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
982 lp->rx_ring[i].base, -lp->rx_ring[i].buf_length,
983 lp->rx_ring[i].msg_length, (unsigned)lp->rx_ring[i].status);
984 for (i = 0 ; i < TX_RING_SIZE; i++)
985 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
986 lp->tx_ring[i].base, -lp->tx_ring[i].length,
987 lp->tx_ring[i].misc, (unsigned)lp->tx_ring[i].status);
988 printk("\n");
989 }
990 pcnet32_restart(dev, 0x0042);
991
992 dev->trans_start = jiffies;
993 netif_start_queue(dev);
994 }
995
996
997 static int
998 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
999 {
1000 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
1001 unsigned int ioaddr = dev->base_addr;
1002 u16 status;
1003 int entry;
1004 unsigned long flags;
1005
1006 if (pcnet32_debug > 3) {
1007 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1008 dev->name, lp->a.read_csr (ioaddr, 0));
1009 }
1010
1011 spin_lock_irqsave(&lp->lock, flags);
1012
1013 /* Default status -- will not enable Successful-TxDone
1014 * interrupt when that option is available to us.
1015 */
1016 status = 0x8300;
1017 if ((lp->ltint) &&
1018 ((lp->cur_tx - lp->dirty_tx == TX_RING_SIZE/2) ||
1019 (lp->cur_tx - lp->dirty_tx >= TX_RING_SIZE-2)))
1020 {
1021 /* Enable Successful-TxDone interrupt if we have
1022 * 1/2 of, or nearly all of, our ring buffer Tx'd
1023 * but not yet cleaned up. Thus, most of the time,
1024 * we will not enable Successful-TxDone interrupts.
1025 */
1026 status = 0x9300;
1027 }
1028
1029 /* Fill in a Tx ring entry */
1030
1031 /* Mask to ring buffer boundary. */
1032 entry = lp->cur_tx & TX_RING_MOD_MASK;
1033
1034 /* Caution: the write order is important here, set the base address
1035 with the "ownership" bits last. */
1036
1037 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1038
1039 lp->tx_ring[entry].misc = 0x00000000;
1040
1041 lp->tx_skbuff[entry] = skb;
1042 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1043 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1044 lp->tx_ring[entry].status = le16_to_cpu(status);
1045
1046 lp->cur_tx++;
1047 lp->stats.tx_bytes += skb->len;
1048
1049 /* Trigger an immediate send poll. */
1050 lp->a.write_csr (ioaddr, 0, 0x0048);
1051
1052 dev->trans_start = jiffies;
1053
1054 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base == 0)
1055 netif_start_queue(dev);
1056 else {
1057 lp->tx_full = 1;
1058 netif_stop_queue(dev);
1059 }
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061 return 0;
1062 }
1063
1064 /* The PCNET32 interrupt handler. */
1065 static void
1066 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1067 {
1068 struct net_device *dev = (struct net_device *)dev_id;
1069 struct pcnet32_private *lp;
1070 unsigned long ioaddr;
1071 u16 csr0,rap;
1072 int boguscnt = max_interrupt_work;
1073 int must_restart;
1074
1075 if (dev == NULL) {
1076 printk (KERN_DEBUG "pcnet32_interrupt(): irq %d for unknown device.\n", irq);
1077 return;
1078 }
1079
1080 ioaddr = dev->base_addr;
1081 lp = (struct pcnet32_private *)dev->priv;
1082
1083 spin_lock(&lp->lock);
1084
1085 rap = lp->a.read_rap(ioaddr);
1086 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8600 && --boguscnt >= 0) {
1087 /* Acknowledge all of the current interrupt sources ASAP. */
1088 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1089
1090 must_restart = 0;
1091
1092 if (pcnet32_debug > 5)
1093 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1094 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1095
1096 if (csr0 & 0x0400) /* Rx interrupt */
1097 pcnet32_rx(dev);
1098
1099 if (csr0 & 0x0200) { /* Tx-done interrupt */
1100 unsigned int dirty_tx = lp->dirty_tx;
1101
1102 while (dirty_tx < lp->cur_tx) {
1103 int entry = dirty_tx & TX_RING_MOD_MASK;
1104 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1105
1106 if (status < 0)
1107 break; /* It still hasn't been Txed */
1108
1109 lp->tx_ring[entry].base = 0;
1110
1111 if (status & 0x4000) {
1112 /* There was an major error, log it. */
1113 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1114 lp->stats.tx_errors++;
1115 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1116 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1117 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1118 #ifndef DO_DXSUFLO
1119 if (err_status & 0x40000000) {
1120 lp->stats.tx_fifo_errors++;
1121 /* Ackk! On FIFO errors the Tx unit is turned off! */
1122 /* Remove this verbosity later! */
1123 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1124 dev->name, csr0);
1125 must_restart = 1;
1126 }
1127 #else
1128 if (err_status & 0x40000000) {
1129 lp->stats.tx_fifo_errors++;
1130 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1131 /* Ackk! On FIFO errors the Tx unit is turned off! */
1132 /* Remove this verbosity later! */
1133 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1134 dev->name, csr0);
1135 must_restart = 1;
1136 }
1137 }
1138 #endif
1139 } else {
1140 if (status & 0x1800)
1141 lp->stats.collisions++;
1142 lp->stats.tx_packets++;
1143 }
1144
1145 /* We must free the original skb */
1146 if (lp->tx_skbuff[entry]) {
1147 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry], lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1148 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1149 lp->tx_skbuff[entry] = 0;
1150 lp->tx_dma_addr[entry] = 0;
1151 }
1152 dirty_tx++;
1153 }
1154
1155 #ifndef final_version
1156 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1157 printk(KERN_ERR "out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1158 dirty_tx, lp->cur_tx, lp->tx_full);
1159 dirty_tx += TX_RING_SIZE;
1160 }
1161 #endif
1162 if (lp->tx_full &&
1163 netif_queue_stopped(dev) &&
1164 dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1165 /* The ring is no longer full, clear tbusy. */
1166 lp->tx_full = 0;
1167 netif_wake_queue (dev);
1168 }
1169 lp->dirty_tx = dirty_tx;
1170 }
1171
1172 /* Log misc errors. */
1173 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1174 if (csr0 & 0x1000) {
1175 /*
1176 * this happens when our receive ring is full. This shouldn't
1177 * be a problem as we will see normal rx interrupts for the frames
1178 * in the receive ring. But there are some PCI chipsets (I can reproduce
1179 * this on SP3G with Intel saturn chipset) which have sometimes problems
1180 * and will fill up the receive ring with error descriptors. In this
1181 * situation we don't get a rx interrupt, but a missed frame interrupt sooner
1182 * or later. So we try to clean up our receive ring here.
1183 */
1184 pcnet32_rx(dev);
1185 lp->stats.rx_errors++; /* Missed a Rx frame. */
1186 }
1187 if (csr0 & 0x0800) {
1188 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1189 dev->name, csr0);
1190 /* unlike for the lance, there is no restart needed */
1191 }
1192
1193 if (must_restart) {
1194 /* stop the chip to clear the error condition, then restart */
1195 lp->a.write_csr (ioaddr, 0, 0x0004);
1196 pcnet32_restart(dev, 0x0002);
1197 }
1198 }
1199
1200 /* Clear any other interrupt, and set interrupt enable. */
1201 lp->a.write_csr (ioaddr, 0, 0x7940);
1202 lp->a.write_rap(ioaddr,rap);
1203
1204 if (pcnet32_debug > 4)
1205 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1206 dev->name, lp->a.read_csr (ioaddr, 0));
1207
1208 spin_unlock(&lp->lock);
1209 }
1210
1211 static int
1212 pcnet32_rx(struct net_device *dev)
1213 {
1214 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
1215 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1216
1217 /* If we own the next entry, it's a new packet. Send it up. */
1218 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1219 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1220
1221 if (status != 0x03) { /* There was an error. */
1222 /*
1223 * There is a tricky error noted by John Murphy,
1224 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1225 * buffers it's possible for a jabber packet to use two
1226 * buffers, with only the last correctly noting the error.
1227 */
1228 if (status & 0x01) /* Only count a general error at the */
1229 lp->stats.rx_errors++; /* end of a packet.*/
1230 if (status & 0x20) lp->stats.rx_frame_errors++;
1231 if (status & 0x10) lp->stats.rx_over_errors++;
1232 if (status & 0x08) lp->stats.rx_crc_errors++;
1233 if (status & 0x04) lp->stats.rx_fifo_errors++;
1234 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1235 } else {
1236 /* Malloc up new buffer, compatible with net-2e. */
1237 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1238 struct sk_buff *skb;
1239
1240 if(pkt_len < 60) {
1241 printk(KERN_ERR "%s: Runt packet!\n",dev->name);
1242 lp->stats.rx_errors++;
1243 } else {
1244 int rx_in_place = 0;
1245
1246 if (pkt_len > rx_copybreak) {
1247 struct sk_buff *newskb;
1248
1249 if ((newskb = dev_alloc_skb (PKT_BUF_SZ))) {
1250 skb_reserve (newskb, 2);
1251 skb = lp->rx_skbuff[entry];
1252 skb_put (skb, pkt_len);
1253 lp->rx_skbuff[entry] = newskb;
1254 newskb->dev = dev;
1255 lp->rx_dma_addr[entry] = pci_map_single(lp->pci_dev, newskb->tail, newskb->len, PCI_DMA_FROMDEVICE);
1256 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1257 rx_in_place = 1;
1258 } else
1259 skb = NULL;
1260 } else {
1261 skb = dev_alloc_skb(pkt_len+2);
1262 }
1263
1264 if (skb == NULL) {
1265 int i;
1266 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n", dev->name);
1267 for (i = 0; i < RX_RING_SIZE; i++)
1268 if ((short)le16_to_cpu(lp->rx_ring[(entry+i) & RX_RING_MOD_MASK].status) < 0)
1269 break;
1270
1271 if (i > RX_RING_SIZE -2) {
1272 lp->stats.rx_dropped++;
1273 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1274 lp->cur_rx++;
1275 }
1276 break;
1277 }
1278 skb->dev = dev;
1279 if (!rx_in_place) {
1280 skb_reserve(skb,2); /* 16 byte align */
1281 skb_put(skb,pkt_len); /* Make room */
1282 eth_copy_and_sum(skb,
1283 (unsigned char *)(lp->rx_skbuff[entry]->tail),
1284 pkt_len,0);
1285 }
1286 lp->stats.rx_bytes += skb->len;
1287 skb->protocol=eth_type_trans(skb,dev);
1288 netif_rx(skb);
1289 lp->stats.rx_packets++;
1290 }
1291 }
1292 /*
1293 * The docs say that the buffer length isn't touched, but Andrew Boyd
1294 * of QNX reports that some revs of the 79C965 clear it.
1295 */
1296 lp->rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
1297 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1298 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1299 }
1300
1301 return 0;
1302 }
1303
1304 static int
1305 pcnet32_close(struct net_device *dev)
1306 {
1307 unsigned long ioaddr = dev->base_addr;
1308 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
1309 int i;
1310
1311 netif_stop_queue(dev);
1312
1313 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1314
1315 if (pcnet32_debug > 1)
1316 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1317 dev->name, lp->a.read_csr (ioaddr, 0));
1318
1319 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
1320 lp->a.write_csr (ioaddr, 0, 0x0004);
1321
1322 /*
1323 * Switch back to 16bit mode to avoid problems with dumb
1324 * DOS packet driver after a warm reboot
1325 */
1326 lp->a.write_bcr (ioaddr, 20, 4);
1327
1328 free_irq(dev->irq, dev);
1329
1330 /* free all allocated skbuffs */
1331 for (i = 0; i < RX_RING_SIZE; i++) {
1332 lp->rx_ring[i].status = 0;
1333 if (lp->rx_skbuff[i]) {
1334 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], lp->rx_skbuff[i]->len, PCI_DMA_FROMDEVICE);
1335 dev_kfree_skb(lp->rx_skbuff[i]);
1336 }
1337 lp->rx_skbuff[i] = NULL;
1338 lp->rx_dma_addr[i] = 0;
1339 }
1340
1341 for (i = 0; i < TX_RING_SIZE; i++) {
1342 if (lp->tx_skbuff[i]) {
1343 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1344 dev_kfree_skb(lp->tx_skbuff[i]);
1345 }
1346 lp->tx_skbuff[i] = NULL;
1347 lp->tx_dma_addr[i] = 0;
1348 }
1349
1350 MOD_DEC_USE_COUNT;
1351
1352 return 0;
1353 }
1354
1355 static struct net_device_stats *
1356 pcnet32_get_stats(struct net_device *dev)
1357 {
1358 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
1359 unsigned long ioaddr = dev->base_addr;
1360 u16 saved_addr;
1361 unsigned long flags;
1362
1363 spin_lock_irqsave(&lp->lock, flags);
1364 saved_addr = lp->a.read_rap(ioaddr);
1365 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1366 lp->a.write_rap(ioaddr, saved_addr);
1367 spin_unlock_irqrestore(&lp->lock, flags);
1368
1369 return &lp->stats;
1370 }
1371
1372 /* taken from the sunlance driver, which it took from the depca driver */
1373 static void pcnet32_load_multicast (struct net_device *dev)
1374 {
1375 struct pcnet32_private *lp = (struct pcnet32_private *) dev->priv;
1376 volatile struct pcnet32_init_block *ib = &lp->init_block;
1377 volatile u16 *mcast_table = (u16 *)&ib->filter;
1378 struct dev_mc_list *dmi=dev->mc_list;
1379 char *addrs;
1380 int i, j, bit, byte;
1381 u32 crc, poly = CRC_POLYNOMIAL_LE;
1382
1383 /* set all multicast bits */
1384 if (dev->flags & IFF_ALLMULTI){
1385 ib->filter [0] = 0xffffffff;
1386 ib->filter [1] = 0xffffffff;
1387 return;
1388 }
1389 /* clear the multicast filter */
1390 ib->filter [0] = 0;
1391 ib->filter [1] = 0;
1392
1393 /* Add addresses */
1394 for (i = 0; i < dev->mc_count; i++){
1395 addrs = dmi->dmi_addr;
1396 dmi = dmi->next;
1397
1398 /* multicast address? */
1399 if (!(*addrs & 1))
1400 continue;
1401
1402 crc = 0xffffffff;
1403 for (byte = 0; byte < 6; byte++)
1404 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1405 int test;
1406
1407 test = ((bit ^ crc) & 0x01);
1408 crc >>= 1;
1409
1410 if (test) {
1411 crc = crc ^ poly;
1412 }
1413 }
1414
1415 crc = crc >> 26;
1416 mcast_table [crc >> 4] |= 1 << (crc & 0xf);
1417 }
1418 return;
1419 }
1420
1421
1422 /*
1423 * Set or clear the multicast filter for this adaptor.
1424 */
1425 static void pcnet32_set_multicast_list(struct net_device *dev)
1426 {
1427 unsigned long ioaddr = dev->base_addr;
1428 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
1429
1430 if (dev->flags&IFF_PROMISC) {
1431 /* Log any net taps. */
1432 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1433 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PORT_PORTSEL) << 7);
1434 } else {
1435 lp->init_block.mode = le16_to_cpu((lp->options & PORT_PORTSEL) << 7);
1436 pcnet32_load_multicast (dev);
1437 }
1438
1439 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
1440
1441 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
1442 }
1443
1444 #ifdef HAVE_PRIVATE_IOCTL
1445 static int pcnet32_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1446 {
1447 unsigned long ioaddr = dev->base_addr;
1448 struct pcnet32_private *lp = (struct pcnet32_private *)dev->priv;
1449 u16 *data = (u16 *)&rq->ifr_data;
1450 int phyaddr = lp->a.read_bcr (ioaddr, 33);
1451
1452 if (lp->mii) {
1453 switch(cmd) {
1454 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1455 data[0] = (phyaddr >> 5) & 0x1f;
1456 /* Fall Through */
1457 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1458 lp->a.write_bcr (ioaddr, 33, ((data[0] & 0x1f) << 5) | (data[1] & 0x1f));
1459 data[3] = lp->a.read_bcr (ioaddr, 34);
1460 lp->a.write_bcr (ioaddr, 33, phyaddr);
1461 return 0;
1462 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1463 if (!capable(CAP_NET_ADMIN))
1464 return -EPERM;
1465 lp->a.write_bcr (ioaddr, 33, ((data[0] & 0x1f) << 5) | (data[1] & 0x1f));
1466 lp->a.write_bcr (ioaddr, 34, data[2]);
1467 lp->a.write_bcr (ioaddr, 33, phyaddr);
1468 return 0;
1469 default:
1470 return -EOPNOTSUPP;
1471 }
1472 }
1473 return -EOPNOTSUPP;
1474 }
1475 #endif /* HAVE_PRIVATE_IOCTL */
1476
1477 static struct pci_driver pcnet32_driver = {
1478 name: "pcnet32",
1479 probe: pcnet32_probe_pci,
1480 remove: NULL,
1481 id_table: pcnet32_pci_tbl,
1482 };
1483
1484 MODULE_PARM(debug, "i");
1485 MODULE_PARM(max_interrupt_work, "i");
1486 MODULE_PARM(rx_copybreak, "i");
1487 MODULE_PARM(tx_start_pt, "i");
1488 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
1489 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
1490 MODULE_AUTHOR("Thomas Bogendoerfer");
1491 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
1492
1493 /* An additional parameter that may be passed in... */
1494 static int debug = -1;
1495 static int tx_start_pt = -1;
1496
1497 static int __init pcnet32_init_module(void)
1498 {
1499 int cards_found = 0;
1500 int err;
1501
1502 if (debug > 0)
1503 pcnet32_debug = debug;
1504 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
1505 tx_start = tx_start_pt;
1506
1507 pcnet32_dev = NULL;
1508 /* find the PCI devices */
1509 #define USE_PCI_REGISTER_DRIVER
1510 #ifdef USE_PCI_REGISTER_DRIVER
1511 if ((err = pci_module_init(&pcnet32_driver)) < 0 )
1512 return err;
1513 #else
1514 {
1515 struct pci_device_id *devid = pcnet32_pci_tbl;
1516 for (devid = pcnet32_pci_tbl; devid != NULL && devid->vendor != 0; devid++) {
1517 struct pci_dev *pdev = pci_find_subsys(devid->vendor, devid->device, devid->subvendor, devid->subdevice, NULL);
1518 if (pdev != NULL) {
1519 if (pcnet32_probe_pci(pdev, devid) >= 0) {
1520 cards_found++;
1521 }
1522 }
1523 }
1524 }
1525 #endif
1526 return 0;
1527 /* find any remaining VLbus devices */
1528 return pcnet32_probe_vlbus(cards_found);
1529 }
1530
1531 static void __exit pcnet32_cleanup_module(void)
1532 {
1533 struct net_device *next_dev;
1534
1535 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1536 while (pcnet32_dev) {
1537 struct pcnet32_private *lp = (struct pcnet32_private *) pcnet32_dev->priv;
1538 next_dev = lp->next;
1539 unregister_netdev(pcnet32_dev);
1540 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
1541 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1542 kfree(pcnet32_dev);
1543 pcnet32_dev = next_dev;
1544 }
1545 }
1546
1547 module_init(pcnet32_init_module);
1548 module_exit(pcnet32_cleanup_module);
1549
1550 /*
1551 * Local variables:
1552 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c pcnet32.c"
1553 * c-indent-level: 4
1554 * tab-width: 8
1555 * End:
1556 */
1557
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