1 /* rtl8129.c: A RealTek RTL8129 Fast Ethernet driver for Linux. */
2 /*
3 Written 1997-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU Public License, incorporated herein by reference.
7 All other rights reserved.
8
9 This driver is for boards based on the RTL8129 PCI ethernet chip.
10
11 The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O
12 Center of Excellence in Space Data and Information Sciences
13 Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771
14
15 Support and updates available at
16 http://cesdis.gsfc.nasa.gov/linux/drivers/rtl8139.html
17
18 Twister-tuning table provided by Kinston <shangh@realtek.com.tw>.
19 */
20
21 static const char *version =
22 "rtl8129.c:v1.07 5/6/99 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/rtl8139.html\n";
23
24 /* A few user-configurable values. */
25 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
26 static int max_interrupt_work = 20;
27 #define rtl8129_debug debug
28 static int rtl8129_debug = 1;
29
30 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
31 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
32 static int multicast_filter_limit = 32;
33
34 /* Used to pass the full-duplex flag, etc. */
35 #define MAX_UNITS 8 /* More are supported, limit only on options */
36 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
37 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
38
39 /* Size of the in-memory receive ring. */
40 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K */
41 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
42 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
43 #define TX_BUF_SIZE 1536
44
45 /* PCI Tuning Parameters
46 Threshold is bytes transferred to chip before transmission starts. */
47 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
48
49 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024. */
50 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
51 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
52 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
53
54 /* Operational parameters that usually are not changed. */
55 /* Time in jiffies before concluding the transmitter is hung. */
56 #define TX_TIMEOUT (4*HZ)
57
58 #include <linux/module.h>
59 #include <linux/version.h>
60 #include <linux/kernel.h>
61 #include <linux/sched.h>
62 #include <linux/string.h>
63 #include <linux/timer.h>
64 #include <linux/errno.h>
65 #include <linux/ioport.h>
66 #include <linux/malloc.h>
67 #include <linux/interrupt.h>
68 #include <linux/init.h>
69 #include <linux/pci.h>
70 #include <linux/netdevice.h>
71 #include <linux/etherdevice.h>
72 #include <linux/skbuff.h>
73 #include <asm/processor.h> /* Processor type for cache alignment. */
74 #include <asm/bitops.h>
75 #include <asm/io.h>
76
77 /* Kernel compatibility defines, some common to David Hind's PCMCIA package.
78 This is only in the support-all-kernels source code. */
79
80 #define RUN_AT(x) (jiffies + (x))
81
82 #include <linux/delay.h>
83
84 #if LINUX_VERSION_CODE < 0x20123
85 #define test_and_set_bit(val, addr) set_bit(val, addr)
86 #endif
87 #if LINUX_VERSION_CODE <= 0x20139
88 #define net_device_stats enet_statistics
89 #else
90 #define NETSTATS_VER2
91 #endif
92 #if LINUX_VERSION_CODE < 0x20155 || defined(CARDBUS)
93 /* Grrrr, the PCI code changed, but did not consider CardBus... */
94 #include <linux/bios32.h>
95 #define PCI_SUPPORT_VER1
96 #else
97 #define PCI_SUPPORT_VER2
98 #endif
99
100 /* The I/O extent. */
101 #define RTL8129_TOTAL_SIZE 0x80
102
103 /*
104 Theory of Operation
105
106 I. Board Compatibility
107
108 This device driver is designed for the RealTek RTL8129, the RealTek Fast
109 Ethernet controllers for PCI. This chip is used on a few clone boards.
110
111
112 II. Board-specific settings
113
114 PCI bus devices are configured by the system at boot time, so no jumpers
115 need to be set on the board. The system BIOS will assign the
116 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
117 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
118 interrupt lines.
119
120 III. Driver operation
121
122 IIIa. Rx Ring buffers
123
124 The receive unit uses a single linear ring buffer rather than the more
125 common (and more efficient) descriptor-based architecture. Incoming frames
126 are sequentially stored into the Rx region, and the host copies them into
127 skbuffs.
128
129 Comment: While it is theoretically possible to process many frames in place,
130 any delay in Rx processing would cause us to drop frames. More importantly,
131 the Linux protocol stack is not designed to operate in this manner.
132
133 IIIb. Tx operation
134
135 The RTL8129 uses a fixed set of four Tx descriptors in register space.
136 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
137 aligns the IP header on word boundaries, and 14 byte ethernet header means
138 that almost all frames will need to be copied to an alignment buffer.
139
140 IVb. References
141
142 http://www.realtek.com.tw/cn/cn.html
143 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
144
145 IVc. Errata
146
147 */
148
149
150 /* This table drives the PCI probe routines. It's mostly boilerplate in all
151 of the drivers, and will likely be provided by some future kernel.
152 Note the matching code -- the first table entry matchs all 56** cards but
153 second only the 1234 card.
154 */
155 enum pci_flags_bit {
156 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
157 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
158 };
159 struct pci_id_info {
160 const char *name;
161 u16 vendor_id, device_id, device_id_mask, flags;
162 int io_size;
163 struct net_device *(*probe1)(struct pci_dev *pdev, int pci_bus, int pci_devfn, long ioaddr, int irq, int chip_idx, int fnd_cnt);
164 };
165
166 static struct net_device * rtl8129_probe1(struct pci_dev *pdev, int pci_bus,
167 int pci_devfn, long ioaddr,
168 int irq, int chp_idx, int fnd_cnt);
169
170 static struct pci_id_info pci_tbl[] =
171 {{ "RealTek RTL8129 Fast Ethernet",
172 0x10ec, 0x8129, 0xffff, PCI_USES_IO|PCI_USES_MASTER, 0x80, rtl8129_probe1},
173 #ifdef USE_8139_SUPPORT_ALSO
174 { "RealTek RTL8139 Fast Ethernet",
175 0x10ec, 0x8139, 0xffff, PCI_USES_IO|PCI_USES_MASTER, 0x80, rtl8129_probe1},
176 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)",
177 0x1113, 0x1211, 0xffff, PCI_USES_IO|PCI_USES_MASTER, 0x80, rtl8129_probe1},
178 { "Accton MPX5030 (RealTek RTL8139)",
179 0x1113, 0x1211, 0xffff, PCI_USES_IO|PCI_USES_MASTER, 0x80, rtl8129_probe1},
180 #endif
181 {0,}, /* 0 terminated list. */
182 };
183
184 /* The capability table matches the chip table above. */
185 enum {HAS_MII_XCVR=0x01, HAS_CHIP_XCVR=0x02, HAS_LNK_CHNG=0x04};
186 static int rtl_cap_tbl[] = {
187 HAS_MII_XCVR, HAS_CHIP_XCVR|HAS_LNK_CHNG, HAS_CHIP_XCVR|HAS_LNK_CHNG,
188 };
189
190
191 /* The rest of these values should never change. */
192 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
193
194 /* Symbolic offsets to registers. */
195 enum RTL8129_registers {
196 MAC0=0, /* Ethernet hardware address. */
197 MAR0=8, /* Multicast filter. */
198 TxStatus0=0x10, /* Transmit status (Four 32bit registers). */
199 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
200 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
201 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
202 IntrMask=0x3C, IntrStatus=0x3E,
203 TxConfig=0x40, RxConfig=0x44,
204 Timer=0x48, /* A general-purpose counter. */
205 RxMissed=0x4C, /* 24 bits valid, write clears. */
206 Cfg9346=0x50, Config0=0x51, Config1=0x52,
207 FlashReg=0x54, GPPinData=0x58, GPPinDir=0x59, MII_SMI=0x5A, HltClk=0x5B,
208 MultiIntr=0x5C, TxSummary=0x60,
209 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
210 NWayExpansion=0x6A,
211 /* Undocumented registers, but required for proper operation. */
212 FIFOTMS=0x70, /* FIFO Test Mode Select */
213 CSCR=0x74, /* Chip Status and Configuration Register. */
214 PARA78=0x78, PARA7c=0x7c, /* Magic transceiver parameter register. */
215 };
216
217 enum ChipCmdBits {
218 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
219
220 /* Interrupt register bits, using my own meaningful names. */
221 enum IntrStatusBits {
222 PCIErr=0x8000, PCSTimeout=0x4000,
223 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
224 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
225 };
226 enum TxStatusBits {
227 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
228 TxOutOfWindow=0x20000000, TxAborted=0x40000000, TxCarrierLost=0x80000000,
229 };
230 enum RxStatusBits {
231 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
232 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
233 RxBadAlign=0x0002, RxStatusOK=0x0001,
234 };
235
236 /* Twister tuning parameters from RealTek.
237 Completely undocumented, but required to tune bad links. */
238 enum CSCRBits {
239 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
240 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
241 CSCR_LinkDownCmd=0x0f3c0,
242 };
243 static const unsigned long param[4][4]={
244 {0x0cb39de43,0x0cb39ce43,0x0fb38de03,0x0cb38de43},
245 {0x0cb39de43,0x0cb39ce43,0x0cb39ce83,0x0cb39ce83},
246 {0x0cb39de43,0x0cb39ce43,0x0cb39ce83,0x0cb39ce83},
247 {0x0bb39de43,0x0bb39ce43,0x0bb39ce83,0x0bb39ce83}
248 };
249
250 struct ring_info {
251 struct sk_buff *skb;
252 dma_addr_t mapping;
253 };
254
255 struct rtl8129_private {
256 char devname[8]; /* Used only for kernel debugging. */
257 const char *product_name;
258 struct net_device *next_module;
259 struct pci_dev *pdev;
260 int chip_id;
261 int chip_revision;
262 unsigned char pci_bus, pci_devfn;
263 struct net_device_stats stats;
264 struct timer_list timer; /* Media selection timer. */
265 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
266 unsigned int cur_tx, dirty_tx, tx_flag;
267 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
268 struct ring_info tx_info[NUM_TX_DESC];
269 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
270 unsigned char *rx_ring;
271 unsigned char *tx_bufs; /* Tx bounce buffer region. */
272 dma_addr_t rx_ring_dma;
273 dma_addr_t tx_bufs_dma;
274 char phys[4]; /* MII device addresses. */
275 char twistie, twist_cnt; /* Twister tune state. */
276 unsigned int tx_full:1; /* The Tx queue is full. */
277 unsigned int full_duplex:1; /* Full-duplex operation requested. */
278 unsigned int duplex_lock:1;
279 unsigned int default_port:4; /* Last dev->if_port value. */
280 unsigned int media2:4; /* Secondary monitored media port. */
281 unsigned int medialock:1; /* Don't sense media type. */
282 unsigned int mediasense:1; /* Media sensing in progress. */
283 };
284
285 MODULE_AUTHOR("Donald Becker <becker@cesdis.gsfc.nasa.gov>");
286 MODULE_DESCRIPTION("RealTek RTL8129 Fast Ethernet driver");
287 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
288 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
289 MODULE_PARM(multicast_filter_limit, "i");
290 MODULE_PARM(max_interrupt_work, "i");
291 MODULE_PARM(debug, "i");
292
293 static int rtl8129_open(struct net_device *dev);
294 static int read_eeprom(long ioaddr, int location);
295 static int mdio_read(struct net_device *dev, int phy_id, int location);
296 static void mdio_write(struct net_device *dev, int phy_id, int location, int val);
297 static void rtl8129_timer(unsigned long data);
298 static void rtl8129_tx_timeout(struct net_device *dev);
299 static void rtl8129_init_ring(struct net_device *dev);
300 static int rtl8129_start_xmit(struct sk_buff *skb, struct net_device *dev);
301 static int rtl8129_rx(struct net_device *dev);
302 static void rtl8129_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
303 static int rtl8129_close(struct net_device *dev);
304 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
305 static struct net_device_stats *rtl8129_get_stats(struct net_device *dev);
306 static inline u32 ether_crc(int length, unsigned char *data);
307 static void set_rx_mode(struct net_device *dev);
308
309
310 /* A list of all installed RTL8129 devices, for removing the driver module. */
311 static struct net_device *root_rtl8129_dev = NULL;
312
313 /* Ideally we would detect all network cards in slot order. That would
314 be best done a central PCI probe dispatch, which wouldn't work
315 well when dynamically adding drivers. So instead we detect just the
316 Rtl81*9 cards in slot order. */
317
318 static int __init rtl8129_probe(void)
319 {
320 int cards_found = 0;
321 int pci_index = 0;
322 unsigned char pci_bus, pci_device_fn;
323 struct net_device *dev;
324
325 if ( ! pcibios_present())
326 return -ENODEV;
327
328 for (; pci_index < 0xff; pci_index++) {
329 struct pci_dev *pdev;
330 u16 vendor, device, pci_command, new_command;
331 int chip_idx, irq;
332 long ioaddr;
333
334 if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index,
335 &pci_bus, &pci_device_fn)
336 != PCIBIOS_SUCCESSFUL)
337 break;
338 pcibios_read_config_word(pci_bus, pci_device_fn,
339 PCI_VENDOR_ID, &vendor);
340 pcibios_read_config_word(pci_bus, pci_device_fn,
341 PCI_DEVICE_ID, &device);
342
343 for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++)
344 if (vendor == pci_tbl[chip_idx].vendor_id
345 && (device & pci_tbl[chip_idx].device_id_mask) ==
346 pci_tbl[chip_idx].device_id)
347 break;
348 if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */
349 continue;
350
351 pdev = pci_find_slot(pci_bus, pci_device_fn);
352
353 ioaddr = pci_resource_start(pdev, 0);
354 irq = pdev->irq;
355
356 if (pci_enable_device(pdev))
357 continue;
358
359 if ((pci_tbl[chip_idx].flags & PCI_USES_IO) &&
360 check_region(ioaddr, pci_tbl[chip_idx].io_size))
361 continue;
362
363 /* Activate the card: fix for brain-damaged Win98 BIOSes. */
364 pcibios_read_config_word(pci_bus, pci_device_fn,
365 PCI_COMMAND, &pci_command);
366 new_command = pci_command | (pci_tbl[chip_idx].flags & 7);
367 if (pci_command != new_command) {
368 printk(KERN_INFO " The PCI BIOS has not enabled the"
369 " device at %d/%d! Updating PCI command %4.4x->%4.4x.\n",
370 pci_bus, pci_device_fn, pci_command, new_command);
371 pcibios_write_config_word(pci_bus, pci_device_fn,
372 PCI_COMMAND, new_command);
373 }
374
375 dev = pci_tbl[chip_idx].probe1(pdev, pci_bus, pci_device_fn, ioaddr, irq, chip_idx, cards_found);
376
377 if (dev && (pci_tbl[chip_idx].flags & PCI_COMMAND_MASTER)) {
378 u8 pci_latency;
379 pcibios_read_config_byte(pci_bus, pci_device_fn,
380 PCI_LATENCY_TIMER, &pci_latency);
381 if (pci_latency < 32) {
382 printk(KERN_NOTICE " PCI latency timer (CFLT) is "
383 "unreasonably low at %d. Setting to 64 clocks.\n",
384 pci_latency);
385 pcibios_write_config_byte(pci_bus, pci_device_fn,
386 PCI_LATENCY_TIMER, 64);
387 }
388 }
389 dev = 0;
390 cards_found++;
391 }
392
393 return cards_found ? 0 : -ENODEV;
394 }
395
396 static struct net_device *rtl8129_probe1(struct pci_dev *pdev, int pci_bus,
397 int pci_devfn, long ioaddr,
398 int irq, int chip_idx, int found_cnt)
399 {
400 static int did_version = 0; /* Already printed version info. */
401 struct rtl8129_private *tp;
402 int i, option = found_cnt < MAX_UNITS ? options[found_cnt] : 0;
403 struct net_device *dev;
404
405 if (rtl8129_debug > 0 && did_version++ == 0)
406 printk(KERN_INFO "%s", version);
407
408 dev = init_etherdev(NULL, 0);
409 if (dev == NULL)
410 goto out;
411
412 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
413 dev->name, pci_tbl[chip_idx].name, ioaddr, irq);
414
415 /* Bring the chip out of low-power mode. */
416 outb(0x00, ioaddr + Config1);
417
418 if (read_eeprom(ioaddr, 0) != 0xffff) {
419 for (i = 0; i < 3; i++) {
420 ((u16 *)(dev->dev_addr))[i] =
421 le16_to_cpu(read_eeprom(ioaddr, i + 7));
422 }
423 } else {
424 for (i = 0; i < 6; i++)
425 dev->dev_addr[i] = inb(ioaddr + MAC0 + i);
426 }
427 for (i = 0; i < 5; i++)
428 printk("%2.2x:", dev->dev_addr[i]);
429 printk("%2.2x.\n", dev->dev_addr[i]);
430
431 /* We do a request_region() to register /proc/ioports info. */
432 if (!request_region(ioaddr, pci_tbl[chip_idx].io_size, dev->name))
433 goto out_free_dev;
434
435 dev->base_addr = ioaddr;
436 dev->irq = irq;
437
438 /* Some data structures must be quadword aligned. */
439 tp = kmalloc(sizeof(*tp), GFP_KERNEL | GFP_DMA);
440 if (tp == NULL)
441 goto out_release_region;
442
443 memset(tp, 0, sizeof(*tp));
444 dev->priv = tp;
445
446 tp->next_module = root_rtl8129_dev;
447 root_rtl8129_dev = dev;
448
449 tp->pdev = pdev;
450 tp->chip_id = chip_idx;
451 tp->pci_bus = pci_bus;
452 tp->pci_devfn = pci_devfn;
453
454 /* Find the connected MII xcvrs.
455 Doing this in open() would allow detecting external xcvrs later, but
456 takes too much time. */
457 if (rtl_cap_tbl[chip_idx] & HAS_MII_XCVR) {
458 int phy, phy_idx;
459 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys);
460 phy++) {
461 int mii_status = mdio_read(dev, phy, 1);
462 if (mii_status != 0xffff && mii_status != 0x0000) {
463 tp->phys[phy_idx++] = phy;
464 printk(KERN_INFO "%s: MII transceiver found at address %d.\n",
465 dev->name, phy);
466 }
467 }
468 if (phy_idx == 0) {
469 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
470 "transceiver.\n",
471 dev->name);
472 tp->phys[0] = -1;
473 }
474 } else
475 tp->phys[0] = 32;
476
477 /* Put the chip into low-power mode. */
478 outb(0xC0, ioaddr + Cfg9346);
479 outb(0x03, ioaddr + Config1);
480 outb('H', ioaddr + HltClk); /* 'R' would leave the clock running. */
481
482 /* The lower four bits are the media type. */
483 if (option > 0) {
484 tp->full_duplex = (option & 0x200) ? 1 : 0;
485 tp->default_port = option & 15;
486 if (tp->default_port)
487 tp->medialock = 1;
488 }
489
490 if (found_cnt < MAX_UNITS && full_duplex[found_cnt] > 0)
491 tp->full_duplex = full_duplex[found_cnt];
492
493 if (tp->full_duplex) {
494 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
495 mdio_write(dev, tp->phys[0], 4, 0x141);
496 tp->duplex_lock = 1;
497 }
498
499 /* The Rtl8129-specific entries in the device structure. */
500 dev->open = &rtl8129_open;
501 dev->hard_start_xmit = &rtl8129_start_xmit;
502 dev->tx_timeout = &rtl8129_tx_timeout;
503 dev->watchdog_timeo = TX_TIMEOUT;
504 dev->stop = &rtl8129_close;
505 dev->get_stats = &rtl8129_get_stats;
506 dev->set_multicast_list = &set_rx_mode;
507 dev->do_ioctl = &mii_ioctl;
508 return dev;
509
510 out_release_region:
511 release_region(ioaddr, pci_tbl[chip_idx].io_size);
512 out_free_dev:
513 unregister_netdev(dev);
514 kfree(dev);
515 out:
516 return NULL;
517 }
518
519 /* Serial EEPROM section. */
520
521 /* EEPROM_Ctrl bits. */
522 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
523 #define EE_CS 0x08 /* EEPROM chip select. */
524 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
525 #define EE_WRITE_0 0x00
526 #define EE_WRITE_1 0x02
527 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
528 #define EE_ENB (0x80 | EE_CS)
529
530 /* Delay between EEPROM clock transitions.
531 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
532 */
533
534 #define eeprom_delay() inl(ee_addr)
535
536 /* The EEPROM commands include the alway-set leading bit. */
537 #define EE_WRITE_CMD (5 << 6)
538 #define EE_READ_CMD (6 << 6)
539 #define EE_ERASE_CMD (7 << 6)
540
541 static int read_eeprom(long ioaddr, int location)
542 {
543 int i;
544 unsigned retval = 0;
545 long ee_addr = ioaddr + Cfg9346;
546 int read_cmd = location | EE_READ_CMD;
547
548 outb(EE_ENB & ~EE_CS, ee_addr);
549 outb(EE_ENB, ee_addr);
550
551 /* Shift the read command bits out. */
552 for (i = 10; i >= 0; i--) {
553 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
554 outb(EE_ENB | dataval, ee_addr);
555 eeprom_delay();
556 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
557 eeprom_delay();
558 }
559 outb(EE_ENB, ee_addr);
560 eeprom_delay();
561
562 for (i = 16; i > 0; i--) {
563 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
564 eeprom_delay();
565 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
566 outb(EE_ENB, ee_addr);
567 eeprom_delay();
568 }
569
570 /* Terminate the EEPROM access. */
571 outb(~EE_CS, ee_addr);
572 return retval;
573 }
574
575 /* MII serial management: mostly bogus for now. */
576 /* Read and write the MII management registers using software-generated
577 serial MDIO protocol.
578 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
579 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
580 "overclocking" issues. */
581 #define MDIO_DIR 0x80
582 #define MDIO_DATA_OUT 0x04
583 #define MDIO_DATA_IN 0x02
584 #define MDIO_CLK 0x01
585 #define MDIO_WRITE0 (MDIO_DIR)
586 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
587
588 #define mdio_delay() inb(mdio_addr)
589
590 static char mii_2_8139_map[8] = {MII_BMCR, MII_BMSR, 0, 0, NWayAdvert,
591 NWayLPAR, NWayExpansion, 0 };
592
593 /* Syncronize the MII management interface by shifting 32 one bits out. */
594 static void mdio_sync(long mdio_addr)
595 {
596 int i;
597
598 for (i = 32; i >= 0; i--) {
599 outb(MDIO_WRITE1, mdio_addr);
600 mdio_delay();
601 outb(MDIO_WRITE1 | MDIO_CLK, mdio_addr);
602 mdio_delay();
603 }
604 return;
605 }
606 static int mdio_read(struct net_device *dev, int phy_id, int location)
607 {
608 long mdio_addr = dev->base_addr + MII_SMI;
609 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
610 int retval = 0;
611 int i;
612
613 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
614 return location < 8 && mii_2_8139_map[location] ?
615 inw(dev->base_addr + mii_2_8139_map[location]) : 0;
616 }
617 mdio_sync(mdio_addr);
618 /* Shift the read command bits out. */
619 for (i = 15; i >= 0; i--) {
620 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
621
622 outb(MDIO_DIR | dataval, mdio_addr);
623 mdio_delay();
624 outb(MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
625 mdio_delay();
626 }
627
628 /* Read the two transition, 16 data, and wire-idle bits. */
629 for (i = 19; i > 0; i--) {
630 outb(0, mdio_addr);
631 mdio_delay();
632 retval = (retval << 1) | ((inb(mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
633 outb(MDIO_CLK, mdio_addr);
634 mdio_delay();
635 }
636 return (retval>>1) & 0xffff;
637 }
638
639 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
640 {
641 long mdio_addr = dev->base_addr + MII_SMI;
642 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
643 int i;
644
645 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
646 if (location < 8 && mii_2_8139_map[location])
647 outw(value, dev->base_addr + mii_2_8139_map[location]);
648 return;
649 }
650 mdio_sync(mdio_addr);
651
652 /* Shift the command bits out. */
653 for (i = 31; i >= 0; i--) {
654 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
655 outb(dataval, mdio_addr);
656 mdio_delay();
657 outb(dataval | MDIO_CLK, mdio_addr);
658 mdio_delay();
659 }
660 /* Clear out extra bits. */
661 for (i = 2; i > 0; i--) {
662 outb(0, mdio_addr);
663 mdio_delay();
664 outb(MDIO_CLK, mdio_addr);
665 mdio_delay();
666 }
667 return;
668 }
669
670
671 static int
672 rtl8129_open(struct net_device *dev)
673 {
674 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
675 long ioaddr = dev->base_addr;
676 int i, retval;
677
678 MOD_INC_USE_COUNT;
679
680 /* Soft reset the chip. */
681 outb(CmdReset, ioaddr + ChipCmd);
682
683 if ((retval = request_irq(dev->irq, &rtl8129_interrupt, SA_SHIRQ, dev->name, dev))) {
684 MOD_DEC_USE_COUNT;
685 return retval;
686 }
687
688 tp->tx_bufs = pci_alloc_consistent(tp->pdev,
689 TX_BUF_SIZE * NUM_TX_DESC,
690 &tp->tx_bufs_dma);
691 tp->rx_ring = pci_alloc_consistent(tp->pdev,
692 RX_BUF_LEN + 16,
693 &tp->rx_ring_dma);
694 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
695 free_irq(dev->irq, dev);
696 if (tp->tx_bufs)
697 pci_free_consistent(tp->pdev,
698 TX_BUF_SIZE * NUM_TX_DESC,
699 tp->tx_bufs, tp->tx_bufs_dma);
700 if (tp->rx_ring)
701 pci_free_consistent(tp->pdev,
702 RX_BUF_LEN + 16,
703 tp->rx_ring, tp->rx_ring_dma);
704 if (rtl8129_debug > 0)
705 printk(KERN_ERR "%s: Couldn't allocate a %d byte receive ring.\n",
706 dev->name, RX_BUF_LEN);
707 MOD_DEC_USE_COUNT;
708 return -ENOMEM;
709 }
710 rtl8129_init_ring(dev);
711
712 /* Check that the chip has finished the reset. */
713 for (i = 1000; i > 0; i--)
714 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0)
715 break;
716
717 for (i = 0; i < 6; i++)
718 outb(dev->dev_addr[i], ioaddr + MAC0 + i);
719
720 /* Must enable Tx/Rx before setting transfer thresholds! */
721 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
722 outl((RX_FIFO_THRESH << 13) | (RX_BUF_LEN_IDX << 11) | (RX_DMA_BURST<<8),
723 ioaddr + RxConfig);
724 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
725 tp->tx_flag = (TX_FIFO_THRESH<<11) & 0x003f0000;
726
727 tp->full_duplex = tp->duplex_lock;
728 if (tp->phys[0] >= 0 || (rtl_cap_tbl[tp->chip_id] & HAS_MII_XCVR)) {
729 u16 mii_reg5 = mdio_read(dev, tp->phys[0], 5);
730 if (mii_reg5 == 0xffff)
731 ; /* Not there */
732 else if ((mii_reg5 & 0x0100) == 0x0100
733 || (mii_reg5 & 0x00C0) == 0x0040)
734 tp->full_duplex = 1;
735 if (rtl8129_debug > 1)
736 printk(KERN_INFO"%s: Setting %s%s-duplex based on"
737 " auto-negotiated partner ability %4.4x.\n", dev->name,
738 mii_reg5 == 0 ? "" :
739 (mii_reg5 & 0x0180) ? "100mbps " : "10mbps ",
740 tp->full_duplex ? "full" : "half", mii_reg5);
741 }
742
743 outb(0xC0, ioaddr + Cfg9346);
744 outb(tp->full_duplex ? 0x60 : 0x20, ioaddr + Config1);
745 outb(0x00, ioaddr + Cfg9346);
746
747 outl(tp->rx_ring_dma, ioaddr + RxBuf);
748
749 /* Start the chip's Tx and Rx process. */
750 outl(0, ioaddr + RxMissed);
751 set_rx_mode(dev);
752
753 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
754
755 /* Enable all known interrupts by setting the interrupt mask. */
756 outw(PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver
757 | TxErr | TxOK | RxErr | RxOK, ioaddr + IntrMask);
758
759 if (rtl8129_debug > 1)
760 printk(KERN_DEBUG"%s: rtl8129_open() ioaddr %#lx IRQ %d"
761 " GP Pins %2.2x %s-duplex.\n",
762 dev->name, ioaddr, dev->irq, inb(ioaddr + GPPinData),
763 tp->full_duplex ? "full" : "half");
764
765 /* Set the timer to switch to check for link beat and perhaps switch
766 to an alternate media type. */
767 init_timer(&tp->timer);
768 tp->timer.expires = RUN_AT((24*HZ)/10); /* 2.4 sec. */
769 tp->timer.data = (unsigned long)dev;
770 tp->timer.function = &rtl8129_timer;
771 add_timer(&tp->timer);
772
773 return 0;
774 }
775
776 static void rtl8129_timer(unsigned long data)
777 {
778 struct net_device *dev = (struct net_device *)data;
779 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
780 long ioaddr = dev->base_addr;
781 int next_tick = 60*HZ;
782 int mii_reg5 = mdio_read(dev, tp->phys[0], 5);
783
784 if (! tp->duplex_lock && mii_reg5 != 0xffff) {
785 int duplex = (mii_reg5&0x0100) || (mii_reg5 & 0x01C0) == 0x0040;
786 if (tp->full_duplex != duplex) {
787 tp->full_duplex = duplex;
788 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
789 " partner ability of %4.4x.\n", dev->name,
790 tp->full_duplex ? "full" : "half", tp->phys[0], mii_reg5);
791 outb(0xC0, ioaddr + Cfg9346);
792 outb(tp->full_duplex ? 0x60 : 0x20, ioaddr + Config1);
793 outb(0x00, ioaddr + Cfg9346);
794 }
795 }
796 /* Check for bogusness. */
797 if (inw(ioaddr + IntrStatus) & (TxOK | RxOK)) {
798 int status = inw(ioaddr + IntrStatus);
799 if (status & (TxOK | RxOK)) { /* Double check */
800 printk(KERN_ERR "%s: RTL8129 Interrupt line blocked, status %x.\n",
801 dev->name, status);
802 rtl8129_interrupt(dev->irq, dev, 0);
803 }
804 }
805 if (netif_queue_stopped(dev) &&
806 (jiffies - dev->trans_start) >= 2*TX_TIMEOUT)
807 rtl8129_tx_timeout(dev);
808
809 #if 0
810 if (tp->twistie) {
811 unsigned int CSCRval = inw(ioaddr + CSCR); /* Read link status. */
812 if (tp->twistie == 1) {
813 if (CSCRval & CSCR_LinkOKBit) {
814 outw(CSCR_LinkDownOffCmd, ioaddr + CSCR);
815 tp->twistie = 2;
816 next_tick = HZ/10;
817 } else {
818 outw(CSCR_LinkDownCmd, ioaddr + CSCR);
819 outl(FIFOTMS_default,ioaddr + FIFOTMS);
820 outl(PARA78_default ,ioaddr + PARA78);
821 outl(PARA7c_default ,ioaddr + PARA7c);
822 tp->twistie = 0;
823 }
824 } else if (tp->twistie == 2) {
825 int linkcase = (CSCRval & CSCR_LinkStatusBits) >> 12;
826 int row;
827 if (linkcase >= 0x7000) row = 3;
828 else if (linkcase >= 0x3000) row = 2;
829 else if (linkcase >= 0x1000) row = 1;
830 else row = 0;
831 tp->twistie == row + 3;
832 outw(0,ioaddr+FIFOTMS);
833 outl(param[row][0], ioaddr+PARA7c);
834 tp->twist_cnt = 1;
835 } else {
836 outl(param[tp->twistie-3][tp->twist_cnt], ioaddr+PARA7c);
837 if (++tp->twist_cnt < 4) {
838 next_tick = HZ/10;
839 } else if (tp->twistie-3 == 3) {
840 if ((CSCRval & CSCR_LinkStatusBits) != 0x7000) {
841 outl(PARA7c_xxx, ioaddr+PARA7c);
842 next_tick = HZ/10; /* 100ms. */
843 outl(FIFOTMS_default, ioaddr+FIFOTMS);
844 outl(PARA78_default, ioaddr+PARA78);
845 outl(PARA7c_default, ioaddr+PARA7c);
846 tp->twistie == 3 + 3;
847 outw(0,ioaddr+FIFOTMS);
848 outl(param[3][0], ioaddr+PARA7c);
849 tp->twist_cnt = 1;
850 }
851 }
852 }
853 }
854 #endif
855
856 if (rtl8129_debug > 2) {
857 if (rtl_cap_tbl[tp->chip_id] & HAS_MII_XCVR)
858 printk(KERN_DEBUG"%s: Media selection tick, GP pins %2.2x.\n",
859 dev->name, inb(ioaddr + GPPinData));
860 else
861 printk(KERN_DEBUG"%s: Media selection tick, Link partner %4.4x.\n",
862 dev->name, inw(ioaddr + NWayLPAR));
863 printk(KERN_DEBUG"%s: Other registers are IntMask %4.4x IntStatus %4.4x"
864 " RxStatus %4.4x.\n",
865 dev->name, inw(ioaddr + IntrMask), inw(ioaddr + IntrStatus),
866 inl(ioaddr + RxEarlyStatus));
867 printk(KERN_DEBUG"%s: Chip config %2.2x %2.2x.\n",
868 dev->name, inb(ioaddr + Config0), inb(ioaddr + Config1));
869 }
870
871 tp->timer.expires = RUN_AT(next_tick);
872 add_timer(&tp->timer);
873 }
874
875 static void rtl8129_tx_timeout(struct net_device *dev)
876 {
877 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
878 long ioaddr = dev->base_addr;
879 int mii_reg, i;
880
881 if (rtl8129_debug > 0)
882 printk(KERN_WARNING "%s: Transmit timeout, status %2.2x %4.4x "
883 "media %2.2x.\n",
884 dev->name, inb(ioaddr + ChipCmd), inw(ioaddr + IntrStatus),
885 inb(ioaddr + GPPinData));
886
887 /* Disable interrupts by clearing the interrupt mask. */
888 outw(0x0000, ioaddr + IntrMask);
889 /* Emit info to figure out what went wrong. */
890 printk("%s: Tx queue start entry %d dirty entry %d.\n",
891 dev->name, tp->cur_tx, tp->dirty_tx);
892 for (i = 0; i < NUM_TX_DESC; i++)
893 printk(KERN_DEBUG"%s: Tx descriptor %d is %8.8x.%s\n",
894 dev->name, i, inl(ioaddr + TxStatus0 + i*4),
895 i == tp->dirty_tx % NUM_TX_DESC ? " (queue head)" : "");
896 printk(KERN_DEBUG"%s: MII #%d registers are:", dev->name, tp->phys[0]);
897 for (mii_reg = 0; mii_reg < 8; mii_reg++)
898 printk(" %4.4x", mdio_read(dev, tp->phys[0], mii_reg));
899 printk(".\n");
900
901 /* Soft reset the chip. */
902 outb(CmdReset, ioaddr + ChipCmd);
903 /* Check that the chip has finished the reset. */
904 for (i = 1000; i > 0; i--)
905 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0)
906 break;
907 for (i = 0; i < 6; i++)
908 outb(dev->dev_addr[i], ioaddr + MAC0 + i);
909
910 outb(0x00, ioaddr + Cfg9346);
911 tp->cur_rx = 0;
912 /* Must enable Tx/Rx before setting transfer thresholds! */
913 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
914 outl((RX_FIFO_THRESH << 13) | (RX_BUF_LEN_IDX << 11) | (RX_DMA_BURST<<8),
915 ioaddr + RxConfig);
916 outl((TX_DMA_BURST<<8), ioaddr + TxConfig);
917 set_rx_mode(dev);
918 { /* Save the unsent Tx packets. */
919 struct sk_buff *saved_skb[NUM_TX_DESC], *skb;
920 int j;
921 for (j = 0; tp->cur_tx - tp->dirty_tx > 0 ; j++, tp->dirty_tx++) {
922 struct ring_info *rp = &tp->tx_info[tp->dirty_tx % NUM_TX_DESC];
923
924 saved_skb[j] = rp->skb;
925 if (rp->mapping != 0) {
926 pci_unmap_single(tp->pdev, rp->mapping, rp->skb->len, PCI_DMA_TODEVICE);
927 rp->mapping = 0;
928 }
929 }
930 tp->dirty_tx = tp->cur_tx = 0;
931
932 for (i = 0; i < j; i++) {
933 skb = tp->tx_info[i].skb = saved_skb[i];
934 if ((long)skb->data & 3) { /* Must use alignment buffer. */
935 memcpy(tp->tx_buf[i], skb->data, skb->len);
936 outl(tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs),
937 ioaddr + TxAddr0 + i*4);
938 } else {
939 tp->tx_info[i].mapping =
940 pci_map_single(tp->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
941 outl(tp->tx_info[i].mapping, ioaddr + TxAddr0 + i*4);
942 }
943 /* Note: the chip doesn't have auto-pad! */
944 outl(tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN),
945 ioaddr + TxStatus0 + i*4);
946 }
947 tp->cur_tx = i;
948 while (i < NUM_TX_DESC) {
949 tp->tx_info[i].skb = NULL;
950 tp->tx_info[i].mapping = 0;
951 i++;
952 }
953 if (tp->cur_tx - tp->dirty_tx < NUM_TX_DESC) {/* Typical path */
954 netif_wake_queue(dev);
955 tp->tx_full = 0;
956 } else {
957 tp->tx_full = 1;
958 netif_stop_queue(dev);
959 }
960 }
961
962 dev->trans_start = jiffies;
963 tp->stats.tx_errors++;
964 /* Enable all known interrupts by setting the interrupt mask. */
965 outw(PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver
966 | TxErr | TxOK | RxErr | RxOK, ioaddr + IntrMask);
967 return;
968 }
969
970
971 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
972 static void
973 rtl8129_init_ring(struct net_device *dev)
974 {
975 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
976 int i;
977
978 tp->tx_full = 0;
979 tp->cur_rx = 0;
980 tp->dirty_tx = tp->cur_tx = 0;
981
982 for (i = 0; i < NUM_TX_DESC; i++) {
983 tp->tx_buf[i] = &tp->tx_bufs[i*TX_BUF_SIZE];
984 tp->tx_info[i].skb = NULL;
985 tp->tx_info[i].mapping = 0;
986 }
987 }
988
989 static int
990 rtl8129_start_xmit(struct sk_buff *skb, struct net_device *dev)
991 {
992 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
993 long ioaddr = dev->base_addr;
994 int entry;
995
996 netif_stop_queue(dev);
997
998 /* Calculate the next Tx descriptor entry. */
999 entry = tp->cur_tx % NUM_TX_DESC;
1000
1001 tp->tx_info[entry].skb = skb;
1002 if ((long)skb->data & 3) { /* Must use alignment buffer. */
1003 tp->tx_info[entry].mapping = 0;
1004 memcpy(tp->tx_buf[entry], skb->data, skb->len);
1005 outl(tp->tx_bufs_dma + (tp->tx_buf[entry] - tp->tx_bufs),
1006 ioaddr + TxAddr0 + entry*4);
1007 } else {
1008 tp->tx_info[entry].mapping =
1009 pci_map_single(tp->pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
1010 outl(tp->tx_info[entry].mapping, ioaddr + TxAddr0 + entry*4);
1011 }
1012 /* Note: the chip doesn't have auto-pad! */
1013 outl(tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN),
1014 ioaddr + TxStatus0 + entry*4);
1015
1016 if (++tp->cur_tx - tp->dirty_tx < NUM_TX_DESC) { /* Typical path */
1017 netif_start_queue(dev);
1018 } else {
1019 tp->tx_full = 1;
1020 }
1021
1022 dev->trans_start = jiffies;
1023 if (rtl8129_debug > 4)
1024 printk(KERN_DEBUG"%s: Queued Tx packet at %p size %d to slot %d.\n",
1025 dev->name, skb->data, (int)skb->len, entry);
1026
1027 return 0;
1028 }
1029
1030 /* The interrupt handler does all of the Rx thread work and cleans up
1031 after the Tx thread. */
1032 static void rtl8129_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1033 {
1034 struct net_device *dev = (struct net_device *)dev_instance;
1035 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
1036 int boguscnt = max_interrupt_work;
1037 int status, link_changed = 0;
1038 long ioaddr = dev->base_addr;
1039
1040 do {
1041 status = inw(ioaddr + IntrStatus);
1042 /* Acknowledge all of the current interrupt sources ASAP, but
1043 an first get an additional status bit from CSCR. */
1044 if ((status & RxUnderrun) && inw(ioaddr+CSCR) & CSCR_LinkChangeBit)
1045 link_changed = 1;
1046 outw(status, ioaddr + IntrStatus);
1047
1048 if (rtl8129_debug > 4)
1049 printk(KERN_DEBUG"%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1050 dev->name, status, inw(ioaddr + IntrStatus));
1051
1052 if ((status & (PCIErr|PCSTimeout|RxUnderrun|RxOverflow|RxFIFOOver
1053 |TxErr|TxOK|RxErr|RxOK)) == 0)
1054 break;
1055
1056 if (status & (RxOK|RxUnderrun|RxOverflow|RxFIFOOver))/* Rx interrupt */
1057 rtl8129_rx(dev);
1058
1059 if (status & (TxOK | TxErr)) {
1060 unsigned int dirty_tx = tp->dirty_tx;
1061
1062 while (tp->cur_tx - dirty_tx > 0) {
1063 int entry = dirty_tx % NUM_TX_DESC;
1064 int txstatus = inl(ioaddr + TxStatus0 + entry*4);
1065
1066 if ( ! (txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1067 break; /* It still hasn't been Txed */
1068
1069 /* Note: TxCarrierLost is always asserted at 100mbps. */
1070 if (txstatus & (TxOutOfWindow | TxAborted)) {
1071 /* There was an major error, log it. */
1072 if (rtl8129_debug > 1)
1073 printk(KERN_NOTICE"%s: Transmit error, Tx status %8.8x.\n",
1074 dev->name, txstatus);
1075 tp->stats.tx_errors++;
1076 if (txstatus&TxAborted) {
1077 tp->stats.tx_aborted_errors++;
1078 outl((TX_DMA_BURST<<8)|0x03000001, ioaddr + TxConfig);
1079 }
1080 if (txstatus&TxCarrierLost) tp->stats.tx_carrier_errors++;
1081 if (txstatus&TxOutOfWindow) tp->stats.tx_window_errors++;
1082 #ifdef ETHER_STATS
1083 if ((txstatus & 0x0f000000) == 0x0f000000)
1084 tp->stats.collisions16++;
1085 #endif
1086 } else {
1087 if (txstatus & TxUnderrun) {
1088 /* Add 64 to the Tx FIFO threshold. */
1089 if (tp->tx_flag < 0x00300000)
1090 tp->tx_flag += 0x00020000;
1091 tp->stats.tx_fifo_errors++;
1092 }
1093 tp->stats.collisions += (txstatus >> 24) & 15;
1094 #if LINUX_VERSION_CODE > 0x20119
1095 tp->stats.tx_bytes += txstatus & 0x7ff;
1096 #endif
1097 tp->stats.tx_packets++;
1098 }
1099
1100 if (tp->tx_info[entry].mapping != 0) {
1101 pci_unmap_single(tp->pdev,
1102 tp->tx_info[entry].mapping,
1103 tp->tx_info[entry].skb->len,
1104 PCI_DMA_TODEVICE);
1105 tp->tx_info[entry].mapping = 0;
1106 }
1107
1108 /* Free the original skb. */
1109 dev_kfree_skb_irq(tp->tx_info[entry].skb);
1110 tp->tx_info[entry].skb = NULL;
1111 if (tp->tx_full) {
1112 /* The ring is no longer full, wake the queue. */
1113 tp->tx_full = 0;
1114 netif_wake_queue(dev);
1115 }
1116 dirty_tx++;
1117 }
1118
1119 #ifndef final_version
1120 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1121 printk(KERN_ERR"%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1122 dev->name, dirty_tx, tp->cur_tx, tp->tx_full);
1123 dirty_tx += NUM_TX_DESC;
1124 }
1125 #endif
1126 tp->dirty_tx = dirty_tx;
1127 }
1128
1129 /* Check uncommon events with one test. */
1130 if (status & (PCIErr|PCSTimeout |RxUnderrun|RxOverflow|RxFIFOOver
1131 |TxErr|RxErr)) {
1132 if (rtl8129_debug > 2)
1133 printk(KERN_NOTICE"%s: Abnormal interrupt, status %8.8x.\n",
1134 dev->name, status);
1135
1136 if (status == 0xffffffff)
1137 break;
1138 /* Update the error count. */
1139 tp->stats.rx_missed_errors += inl(ioaddr + RxMissed);
1140 outl(0, ioaddr + RxMissed);
1141
1142 if ((status & RxUnderrun) && link_changed &&
1143 (rtl_cap_tbl[tp->chip_id] & HAS_LNK_CHNG)) {
1144 /* Really link-change on new chips. */
1145 int lpar = inw(ioaddr + NWayLPAR);
1146 int duplex = (lpar&0x0100)||(lpar & 0x01C0) == 0x0040;
1147 if (tp->full_duplex != duplex) {
1148 tp->full_duplex = duplex;
1149 outb(0xC0, ioaddr + Cfg9346);
1150 outb(tp->full_duplex ? 0x60 : 0x20, ioaddr + Config1);
1151 outb(0x00, ioaddr + Cfg9346);
1152 }
1153 status &= ~RxUnderrun;
1154 }
1155 if (status & (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1156 tp->stats.rx_errors++;
1157
1158 if (status & (PCSTimeout)) tp->stats.rx_length_errors++;
1159 if (status & (RxUnderrun|RxFIFOOver)) tp->stats.rx_fifo_errors++;
1160 if (status & RxOverflow) {
1161 tp->stats.rx_over_errors++;
1162 tp->cur_rx = inw(ioaddr + RxBufAddr) % RX_BUF_LEN;
1163 outw(tp->cur_rx - 16, ioaddr + RxBufPtr);
1164 }
1165 if (status & PCIErr) {
1166 u32 pci_cmd_status;
1167 pcibios_read_config_dword(tp->pci_bus, tp->pci_devfn,
1168 PCI_COMMAND, &pci_cmd_status);
1169
1170 printk(KERN_ERR "%s: PCI Bus error %4.4x.\n",
1171 dev->name, pci_cmd_status);
1172 }
1173 }
1174 if (--boguscnt < 0) {
1175 printk(KERN_WARNING"%s: Too much work at interrupt, "
1176 "IntrStatus=0x%4.4x.\n",
1177 dev->name, status);
1178 /* Clear all interrupt sources. */
1179 outw(0xffff, ioaddr + IntrStatus);
1180 break;
1181 }
1182 } while (1);
1183
1184 if (rtl8129_debug > 3)
1185 printk(KERN_DEBUG"%s: exiting interrupt, intr_status=%#4.4x.\n",
1186 dev->name, inl(ioaddr + IntrStatus));
1187 return;
1188 }
1189
1190 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1191 field alignments and semantics. */
1192 static int rtl8129_rx(struct net_device *dev)
1193 {
1194 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
1195 long ioaddr = dev->base_addr;
1196 unsigned char *rx_ring = tp->rx_ring;
1197 u16 cur_rx = tp->cur_rx;
1198
1199 if (rtl8129_debug > 4)
1200 printk(KERN_DEBUG"%s: In rtl8129_rx(), current %4.4x BufAddr %4.4x,"
1201 " free to %4.4x, Cmd %2.2x.\n",
1202 dev->name, cur_rx, inw(ioaddr + RxBufAddr),
1203 inw(ioaddr + RxBufPtr), inb(ioaddr + ChipCmd));
1204
1205 while ((inb(ioaddr + ChipCmd) & 1) == 0) {
1206 int ring_offset = cur_rx % RX_BUF_LEN;
1207 u32 rx_status = le32_to_cpu(*(u32*)(rx_ring + ring_offset));
1208 int rx_size = rx_status >> 16;
1209
1210 if (rtl8129_debug > 4) {
1211 int i;
1212 printk(KERN_DEBUG"%s: rtl8129_rx() status %4.4x, size %4.4x, cur %4.4x.\n",
1213 dev->name, rx_status, rx_size, cur_rx);
1214 printk(KERN_DEBUG"%s: Frame contents ", dev->name);
1215 for (i = 0; i < 70; i++)
1216 printk(" %2.2x", le32_to_cpu(rx_ring[ring_offset + i]));
1217 printk(".\n");
1218 }
1219 if (rx_status & RxTooLong) {
1220 if (rtl8129_debug > 0)
1221 printk(KERN_NOTICE"%s: Oversized Ethernet frame, status %4.4x!\n",
1222 dev->name, rx_status);
1223 tp->stats.rx_length_errors++;
1224 } else if (rx_status &
1225 (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) {
1226 if (rtl8129_debug > 1)
1227 printk(KERN_DEBUG"%s: Ethernet frame had errors,"
1228 " status %4.4x.\n", dev->name, rx_status);
1229 tp->stats.rx_errors++;
1230 if (rx_status & (RxBadSymbol|RxBadAlign))
1231 tp->stats.rx_frame_errors++;
1232 if (rx_status & (RxRunt|RxTooLong)) tp->stats.rx_length_errors++;
1233 if (rx_status & RxCRCErr) tp->stats.rx_crc_errors++;
1234 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1235 tp->cur_rx = 0;
1236 outb(CmdTxEnb, ioaddr + ChipCmd);
1237 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
1238 outl((RX_FIFO_THRESH << 13) | (RX_BUF_LEN_IDX << 11) |
1239 (RX_DMA_BURST<<8), ioaddr + RxConfig);
1240 } else {
1241 /* Malloc up new buffer, compatible with net-2e. */
1242 /* Omit the four octet CRC from the length. */
1243 struct sk_buff *skb;
1244 int pkt_size = rx_size - 4;
1245
1246 skb = dev_alloc_skb(pkt_size + 2);
1247 if (skb == NULL) {
1248 printk(KERN_WARNING"%s: Memory squeeze, deferring packet.\n",
1249 dev->name);
1250 /* We should check that some rx space is free.
1251 If not, free one and mark stats->rx_dropped++. */
1252 tp->stats.rx_dropped++;
1253 break;
1254 }
1255 skb->dev = dev;
1256 skb_reserve(skb, 2); /* 16 byte align the IP fields. */
1257 if (ring_offset+rx_size > RX_BUF_LEN) {
1258 int semi_count = RX_BUF_LEN - ring_offset - 4;
1259 memcpy(skb_put(skb, semi_count), &rx_ring[ring_offset + 4],
1260 semi_count);
1261 memcpy(skb_put(skb, pkt_size-semi_count), rx_ring,
1262 pkt_size-semi_count);
1263 if (rtl8129_debug > 4) {
1264 int i;
1265 printk(KERN_DEBUG"%s: Frame wrap @%d",
1266 dev->name, semi_count);
1267 for (i = 0; i < 16; i++)
1268 printk(" %2.2x", le32_to_cpu(rx_ring[i]));
1269 printk(".\n");
1270 memset(rx_ring, 0xcc, 16);
1271 }
1272 } else {
1273 #if 1 /* USE_IP_COPYSUM */
1274 eth_copy_and_sum(skb, &rx_ring[ring_offset + 4],
1275 pkt_size, 0);
1276 skb_put(skb, pkt_size);
1277 #else
1278 memcpy(skb_put(skb, pkt_size), &rx_ring[ring_offset + 4],
1279 pkt_size);
1280 #endif
1281 }
1282 skb->protocol = eth_type_trans(skb, dev);
1283 netif_rx(skb);
1284 #if LINUX_VERSION_CODE > 0x20119
1285 tp->stats.rx_bytes += pkt_size;
1286 #endif
1287 tp->stats.rx_packets++;
1288 }
1289
1290 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1291 outw(cur_rx - 16, ioaddr + RxBufPtr);
1292 }
1293 if (rtl8129_debug > 4)
1294 printk(KERN_DEBUG"%s: Done rtl8129_rx(), current %4.4x BufAddr %4.4x,"
1295 " free to %4.4x, Cmd %2.2x.\n",
1296 dev->name, cur_rx, inw(ioaddr + RxBufAddr),
1297 inw(ioaddr + RxBufPtr), inb(ioaddr + ChipCmd));
1298 tp->cur_rx = cur_rx;
1299 return 0;
1300 }
1301
1302 static int
1303 rtl8129_close(struct net_device *dev)
1304 {
1305 long ioaddr = dev->base_addr;
1306 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
1307 int i;
1308
1309 netif_stop_queue(dev);
1310
1311 del_timer_sync(&tp->timer);
1312
1313 if (rtl8129_debug > 1)
1314 printk(KERN_DEBUG"%s: Shutting down ethercard, status was 0x%4.4x.\n",
1315 dev->name, inw(ioaddr + IntrStatus));
1316
1317 /* Disable interrupts by clearing the interrupt mask. */
1318 outw(0x0000, ioaddr + IntrMask);
1319
1320 /* Stop the chip's Tx and Rx DMA processes. */
1321 outb(0x00, ioaddr + ChipCmd);
1322
1323 /* Update the error counts. */
1324 tp->stats.rx_missed_errors += inl(ioaddr + RxMissed);
1325 outl(0, ioaddr + RxMissed);
1326
1327 free_irq(dev->irq, dev);
1328
1329 for (i = 0; i < NUM_TX_DESC; i++) {
1330 struct sk_buff *skb = tp->tx_info[i].skb;
1331 dma_addr_t mapping = tp->tx_info[i].mapping;
1332
1333 if (skb) {
1334 if (mapping)
1335 pci_unmap_single(tp->pdev, mapping, skb->len, PCI_DMA_TODEVICE);
1336 dev_kfree_skb(skb);
1337 }
1338 tp->tx_info[i].skb = NULL;
1339 tp->tx_info[i].mapping = 0;
1340 }
1341 pci_free_consistent(tp->pdev, RX_BUF_LEN + 16,
1342 tp->rx_ring, tp->rx_ring_dma);
1343 pci_free_consistent(tp->pdev, TX_BUF_SIZE * NUM_TX_DESC,
1344 tp->tx_bufs, tp->tx_bufs_dma);
1345 tp->rx_ring = NULL;
1346 tp->tx_bufs = NULL;
1347
1348 /* Green! Put the chip in low-power mode. */
1349 outb(0xC0, ioaddr + Cfg9346);
1350 outb(0x03, ioaddr + Config1);
1351 outb('H', ioaddr + HltClk); /* 'R' would leave the clock running. */
1352
1353 MOD_DEC_USE_COUNT;
1354
1355 return 0;
1356 }
1357
1358 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1359 {
1360 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
1361 u16 *data = (u16 *)&rq->ifr_data;
1362
1363 switch(cmd) {
1364 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1365 data[0] = tp->phys[0] & 0x3f;
1366 /* Fall Through */
1367 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1368 data[3] = mdio_read(dev, data[0], data[1] & 0x1f);
1369 return 0;
1370 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1371 if (!capable(CAP_NET_ADMIN))
1372 return -EPERM;
1373 mdio_write(dev, data[0], data[1] & 0x1f, data[2]);
1374 return 0;
1375 default:
1376 return -EOPNOTSUPP;
1377 }
1378 }
1379
1380 static struct net_device_stats *
1381 rtl8129_get_stats(struct net_device *dev)
1382 {
1383 struct rtl8129_private *tp = (struct rtl8129_private *)dev->priv;
1384 long ioaddr = dev->base_addr;
1385
1386 if (netif_running(dev)) {
1387 tp->stats.rx_missed_errors += inl(ioaddr + RxMissed);
1388 outl(0, ioaddr + RxMissed);
1389 }
1390
1391 return &tp->stats;
1392 }
1393
1394 /* Set or clear the multicast filter for this adaptor.
1395 This routine is not state sensitive and need not be SMP locked. */
1396
1397 static unsigned const ethernet_polynomial = 0x04c11db7U;
1398 static inline u32 ether_crc(int length, unsigned char *data)
1399 {
1400 int crc = -1;
1401
1402 while (--length >= 0) {
1403 unsigned char current_octet = *data++;
1404 int bit;
1405 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
1406 crc = (crc << 1) ^
1407 ((crc < 0) ^ (current_octet & 1) ? ethernet_polynomial : 0);
1408 }
1409 return crc;
1410 }
1411
1412 /* Bits in RxConfig. */
1413 enum rx_mode_bits {
1414 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
1415 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
1416 };
1417
1418 static void set_rx_mode(struct net_device *dev)
1419 {
1420 long ioaddr = dev->base_addr;
1421 u32 mc_filter[2]; /* Multicast hash filter */
1422 int i, rx_mode;
1423
1424 if (rtl8129_debug > 3)
1425 printk(KERN_DEBUG"%s: set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1426 dev->name, dev->flags, inl(ioaddr + RxConfig));
1427
1428 /* Note: do not reorder, GCC is clever about common statements. */
1429 if (dev->flags & IFF_PROMISC) {
1430 /* Unconditionally log net taps. */
1431 printk(KERN_NOTICE"%s: Promiscuous mode enabled.\n", dev->name);
1432 rx_mode = AcceptBroadcast|AcceptMulticast|AcceptMyPhys|AcceptAllPhys;
1433 mc_filter[1] = mc_filter[0] = 0xffffffff;
1434 } else if ((dev->mc_count > multicast_filter_limit)
1435 || (dev->flags & IFF_ALLMULTI)) {
1436 /* Too many to filter perfectly -- accept all multicasts. */
1437 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1438 mc_filter[1] = mc_filter[0] = 0xffffffff;
1439 } else {
1440 struct dev_mc_list *mclist;
1441 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1442 mc_filter[1] = mc_filter[0] = 0;
1443 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1444 i++, mclist = mclist->next)
1445 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26, mc_filter);
1446 }
1447 /* We can safely update without stopping the chip. */
1448 outb(rx_mode, ioaddr + RxConfig);
1449 outl(mc_filter[0], ioaddr + MAR0 + 0);
1450 outl(mc_filter[1], ioaddr + MAR0 + 4);
1451 return;
1452 }
1453
1454
1455 static void __exit rtl8129_cleanup (void)
1456 {
1457 struct net_device *next_dev;
1458
1459 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1460 while (root_rtl8129_dev) {
1461 struct rtl8129_private *tp =
1462 (struct rtl8129_private *)root_rtl8129_dev->priv;
1463 next_dev = tp->next_module;
1464 unregister_netdev(root_rtl8129_dev);
1465 release_region(root_rtl8129_dev->base_addr,
1466 pci_tbl[tp->chip_id].io_size);
1467 kfree(tp);
1468 kfree(root_rtl8129_dev);
1469 root_rtl8129_dev = next_dev;
1470 }
1471 }
1472
1473 module_init(rtl8129_probe);
1474 module_exit(rtl8129_cleanup);
1475
1476 /*
1477 * Local variables:
1478 * compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c rtl8129.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`"
1479 * c-indent-level: 4
1480 * c-basic-offset: 4
1481 * tab-width: 4
1482 * End:
1483 */
1484
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.