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Linux Cross Reference
Linux/drivers/net/sonic.h

Version: ~ [ 2.4.0 ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * Helpfile for sonic.c
  3  *
  4  * (C) Waldorf Electronics, Germany
  5  * Written by Andreas Busse
  6  *
  7  * NOTE: most of the structure definitions here are endian dependent.
  8  * If you want to use this driver on big endian machines, the data
  9  * and pad structure members must be exchanged. Also, the structures
 10  * need to be changed accordingly to the bus size. 
 11  *
 12  * 981229 MSch: did just that for the 68k Mac port (32 bit, big endian),
 13  *              see CONFIG_MACSONIC branch below.
 14  *
 15  */
 16 
 17 #ifndef SONIC_H
 18 #define SONIC_H
 19 
 20 #include <linux/config.h>
 21 
 22 /*
 23  * SONIC register offsets
 24  */
 25  
 26 #define SONIC_CMD              0x00
 27 #define SONIC_DCR              0x01
 28 #define SONIC_RCR              0x02
 29 #define SONIC_TCR              0x03
 30 #define SONIC_IMR              0x04
 31 #define SONIC_ISR              0x05
 32 
 33 #define SONIC_UTDA             0x06
 34 #define SONIC_CTDA             0x07
 35 
 36 #define SONIC_URDA             0x0d
 37 #define SONIC_CRDA             0x0e
 38 #define SONIC_EOBC             0x13
 39 #define SONIC_URRA             0x14
 40 #define SONIC_RSA              0x15
 41 #define SONIC_REA              0x16
 42 #define SONIC_RRP              0x17
 43 #define SONIC_RWP              0x18
 44 #define SONIC_RSC              0x2b
 45 
 46 #define SONIC_CEP              0x21
 47 #define SONIC_CAP2             0x22
 48 #define SONIC_CAP1             0x23
 49 #define SONIC_CAP0             0x24
 50 #define SONIC_CE               0x25
 51 #define SONIC_CDP              0x26
 52 #define SONIC_CDC              0x27
 53 
 54 #define SONIC_WT0              0x29
 55 #define SONIC_WT1              0x2a
 56 
 57 #define SONIC_SR               0x28
 58 
 59 
 60 /* test-only registers */
 61 
 62 #define SONIC_TPS               0x08
 63 #define SONIC_TFC               0x09
 64 #define SONIC_TSA0              0x0a
 65 #define SONIC_TSA1              0x0b
 66 #define SONIC_TFS               0x0c
 67 
 68 #define SONIC_CRBA0             0x0f
 69 #define SONIC_CRBA1             0x10
 70 #define SONIC_RBWC0             0x11
 71 #define SONIC_RBWC1             0x12
 72 #define SONIC_TTDA              0x20
 73 #define SONIC_MDT               0x2f
 74 
 75 #define SONIC_TRBA0             0x19
 76 #define SONIC_TRBA1             0x1a
 77 #define SONIC_TBWC0             0x1b
 78 #define SONIC_TBWC1             0x1c
 79 #define SONIC_LLFA              0x1f
 80 
 81 #define SONIC_ADDR0             0x1d
 82 #define SONIC_ADDR1             0x1e
 83 
 84 /*
 85  * Error counters
 86  */
 87 #define SONIC_CRCT              0x2c
 88 #define SONIC_FAET              0x2d
 89 #define SONIC_MPT               0x2e
 90 
 91 
 92 /*
 93  * SONIC command bits
 94  */
 95 
 96 #define SONIC_CR_LCAM           0x0200
 97 #define SONIC_CR_RRRA           0x0100
 98 #define SONIC_CR_RST            0x0080
 99 #define SONIC_CR_ST             0x0020
100 #define SONIC_CR_STP            0x0010
101 #define SONIC_CR_RXEN           0x0008
102 #define SONIC_CR_RXDIS          0x0004
103 #define SONIC_CR_TXP            0x0002
104 #define SONIC_CR_HTX            0x0001
105 
106 /*
107  * SONIC data configuration bits
108  */
109 
110 #define SONIC_DCR_EXBUS         0x8000
111 #define SONIC_DCR_LBR           0x2000
112 #define SONIC_DCR_PO1           0x1000
113 #define SONIC_DCR_PO0           0x0800
114 #define SONIC_DCR_SBUS          0x0400
115 #define SONIC_DCR_USR1          0x0200
116 #define SONIC_DCR_USR0          0x0100
117 #define SONIC_DCR_WC1           0x0080
118 #define SONIC_DCR_WC0           0x0040
119 #define SONIC_DCR_DW            0x0020
120 #define SONIC_DCR_BMS           0x0010
121 #define SONIC_DCR_RFT1          0x0008
122 #define SONIC_DCR_RFT0          0x0004
123 #define SONIC_DCR_TFT1          0x0002
124 #define SONIC_DCR_TFT0          0x0001
125 
126 /*
127  * Constants for the SONIC receive control register.
128  */
129 
130 #define SONIC_RCR_ERR           0x8000
131 #define SONIC_RCR_RNT           0x4000
132 #define SONIC_RCR_BRD           0x2000
133 #define SONIC_RCR_PRO           0x1000
134 #define SONIC_RCR_AMC           0x0800
135 #define SONIC_RCR_LB1           0x0400
136 #define SONIC_RCR_LB0           0x0200
137 
138 #define SONIC_RCR_MC            0x0100
139 #define SONIC_RCR_BC            0x0080
140 #define SONIC_RCR_LPKT          0x0040
141 #define SONIC_RCR_CRS           0x0020
142 #define SONIC_RCR_COL           0x0010
143 #define SONIC_RCR_CRCR          0x0008
144 #define SONIC_RCR_FAER          0x0004
145 #define SONIC_RCR_LBK           0x0002
146 #define SONIC_RCR_PRX           0x0001
147 
148 #define SONIC_RCR_LB_OFF        0
149 #define SONIC_RCR_LB_MAC        SONIC_RCR_LB0
150 #define SONIC_RCR_LB_ENDEC      SONIC_RCR_LB1
151 #define SONIC_RCR_LB_TRANS      (SONIC_RCR_LB0 | SONIC_RCR_LB1)
152 
153 /* default RCR setup */
154 
155 #define SONIC_RCR_DEFAULT       (SONIC_RCR_BRD)
156 
157 
158 /*
159  * SONIC Transmit Control register bits
160  */
161 
162 #define SONIC_TCR_PINTR         0x8000
163 #define SONIC_TCR_POWC          0x4000
164 #define SONIC_TCR_CRCI          0x2000
165 #define SONIC_TCR_EXDIS         0x1000
166 #define SONIC_TCR_EXD           0x0400
167 #define SONIC_TCR_DEF           0x0200
168 #define SONIC_TCR_NCRS          0x0100
169 #define SONIC_TCR_CRLS          0x0080
170 #define SONIC_TCR_EXC           0x0040
171 #define SONIC_TCR_PMB           0x0008
172 #define SONIC_TCR_FU            0x0004
173 #define SONIC_TCR_BCM           0x0002
174 #define SONIC_TCR_PTX           0x0001
175 
176 #define SONIC_TCR_DEFAULT       0x0000
177 
178 /* 
179  * Constants for the SONIC_INTERRUPT_MASK and
180  * SONIC_INTERRUPT_STATUS registers.
181  */
182 
183 #define SONIC_INT_BR            0x4000
184 #define SONIC_INT_HBL           0x2000
185 #define SONIC_INT_LCD           0x1000
186 #define SONIC_INT_PINT          0x0800
187 #define SONIC_INT_PKTRX         0x0400
188 #define SONIC_INT_TXDN          0x0200
189 #define SONIC_INT_TXER          0x0100
190 #define SONIC_INT_TC            0x0080
191 #define SONIC_INT_RDE           0x0040
192 #define SONIC_INT_RBE           0x0020
193 #define SONIC_INT_RBAE          0x0010
194 #define SONIC_INT_CRC           0x0008
195 #define SONIC_INT_FAE           0x0004
196 #define SONIC_INT_MP            0x0002
197 #define SONIC_INT_RFO           0x0001
198 
199 
200 /*
201  * The interrupts we allow.
202  */
203 
204 #define SONIC_IMR_DEFAULT       (SONIC_INT_BR | \
205                                 SONIC_INT_LCD | \
206                                 SONIC_INT_PINT | \
207                                 SONIC_INT_PKTRX | \
208                                 SONIC_INT_TXDN | \
209                                 SONIC_INT_TXER | \
210                                 SONIC_INT_RDE | \
211                                 SONIC_INT_RBE | \
212                                 SONIC_INT_RBAE | \
213                                 SONIC_INT_CRC | \
214                                 SONIC_INT_FAE | \
215                                 SONIC_INT_MP)
216 
217 
218 #define SONIC_END_OF_LINKS      0x0001
219 
220 
221 #ifdef CONFIG_MACSONIC
222 /* Big endian like structures on Mac
223  * (680x0)
224  */
225 
226 typedef struct {
227   u32 rx_bufadr_l;      /* receive buffer ptr */
228   u32 rx_bufadr_h;
229 
230   u32 rx_bufsize_l;     /* no. of words in the receive buffer */
231   u32 rx_bufsize_h;
232 } sonic_rr_t;
233 
234 /*
235  * Sonic receive descriptor. Receive descriptors are
236  * kept in a linked list of these structures.
237  */
238 
239 typedef struct {
240   SREGS_PAD(pad0);
241   u16 rx_status;        /* status after reception of a packet */
242   SREGS_PAD(pad1);
243   u16 rx_pktlen;        /* length of the packet incl. CRC */
244   
245   /*
246    * Pointers to the location in the receive buffer area (RBA)
247    * where the packet resides. A packet is always received into
248    * a contiguous piece of memory.
249    */
250   SREGS_PAD(pad2);
251   u16 rx_pktptr_l;
252   SREGS_PAD(pad3);
253   u16 rx_pktptr_h;
254 
255   SREGS_PAD(pad4);
256   u16 rx_seqno; /* sequence no. */
257 
258   SREGS_PAD(pad5);
259   u16 link;             /* link to next RDD (end if EOL bit set) */
260 
261   /*
262    * Owner of this descriptor, 0= driver, 1=sonic
263    */
264   
265   SREGS_PAD(pad6);
266   u16 in_use;   
267 
268   caddr_t rda_next;             /* pointer to next RD */
269 } sonic_rd_t;
270 
271 
272 /*
273  * Describes a Transmit Descriptor
274  */
275 typedef struct {
276   SREGS_PAD(pad0);              
277   u16 tx_status;        /* status after transmission of a packet */
278   SREGS_PAD(pad1);              
279   u16 tx_config;        /* transmit configuration for this packet */
280   SREGS_PAD(pad2);              
281   u16 tx_pktsize;       /* size of the packet to be transmitted */
282   SREGS_PAD(pad3);              
283   u16 tx_frag_count;    /* no. of fragments */
284 
285   SREGS_PAD(pad4);              
286   u16 tx_frag_ptr_l;
287   SREGS_PAD(pad5);              
288   u16 tx_frag_ptr_h;
289   SREGS_PAD(pad6);              
290   u16 tx_frag_size;
291   
292   SREGS_PAD(pad7);              
293   u16 link;             /* ptr to next descriptor */
294 } sonic_td_t;
295 
296 
297 /*
298  * Describes an entry in the CAM Descriptor Area.
299  */
300 
301 typedef struct {
302   SREGS_PAD(pad0);
303   u16 cam_entry_pointer;
304   SREGS_PAD(pad1);
305   u16 cam_cap0;
306   SREGS_PAD(pad2);
307   u16 cam_cap1;
308   SREGS_PAD(pad3);
309   u16 cam_cap2;
310 } sonic_cd_t;
311 
312 #define CAM_DESCRIPTORS 16
313 
314 
315 typedef struct {
316   sonic_cd_t cam_desc[CAM_DESCRIPTORS];
317   SREGS_PAD(pad);
318   u16 cam_enable;
319 } sonic_cda_t;
320 
321 #else /* original declarations, little endian 32 bit */
322 
323 /*
324  * structure definitions
325  */
326 
327 typedef struct {
328   u32 rx_bufadr_l;      /* receive buffer ptr */
329   u32 rx_bufadr_h;
330 
331   u32 rx_bufsize_l;     /* no. of words in the receive buffer */
332   u32 rx_bufsize_h;
333 } sonic_rr_t;
334 
335 /*
336  * Sonic receive descriptor. Receive descriptors are
337  * kept in a linked list of these structures.
338  */
339 
340 typedef struct {
341   u16 rx_status;        /* status after reception of a packet */
342   SREGS_PAD(pad0);
343   u16 rx_pktlen;        /* length of the packet incl. CRC */
344   SREGS_PAD(pad1);
345   
346   /*
347    * Pointers to the location in the receive buffer area (RBA)
348    * where the packet resides. A packet is always received into
349    * a contiguous piece of memory.
350    */
351   u16 rx_pktptr_l;
352   SREGS_PAD(pad2);
353   u16 rx_pktptr_h;
354   SREGS_PAD(pad3);
355 
356   u16 rx_seqno; /* sequence no. */
357   SREGS_PAD(pad4);
358 
359   u16 link;             /* link to next RDD (end if EOL bit set) */
360   SREGS_PAD(pad5);
361 
362   /*
363    * Owner of this descriptor, 0= driver, 1=sonic
364    */
365   
366   u16 in_use;   
367   SREGS_PAD(pad6);
368 
369   caddr_t rda_next;             /* pointer to next RD */
370 } sonic_rd_t;
371 
372 
373 /*
374  * Describes a Transmit Descriptor
375  */
376 typedef struct {
377   u16 tx_status;        /* status after transmission of a packet */
378   SREGS_PAD(pad0);
379   u16 tx_config;        /* transmit configuration for this packet */
380   SREGS_PAD(pad1);
381   u16 tx_pktsize;       /* size of the packet to be transmitted */
382   SREGS_PAD(pad2);
383   u16 tx_frag_count;    /* no. of fragments */
384   SREGS_PAD(pad3);
385 
386   u16 tx_frag_ptr_l;
387   SREGS_PAD(pad4);
388   u16 tx_frag_ptr_h;
389   SREGS_PAD(pad5);
390   u16 tx_frag_size;
391   SREGS_PAD(pad6);
392   
393   u16 link;             /* ptr to next descriptor */
394   SREGS_PAD(pad7);
395 } sonic_td_t;
396 
397 
398 /*
399  * Describes an entry in the CAM Descriptor Area.
400  */
401 
402 typedef struct {
403   u16 cam_entry_pointer;
404   SREGS_PAD(pad0);
405   u16 cam_cap0;
406   SREGS_PAD(pad1);
407   u16 cam_cap1;
408   SREGS_PAD(pad2);
409   u16 cam_cap2;
410   SREGS_PAD(pad3);
411 } sonic_cd_t;
412 
413 #define CAM_DESCRIPTORS 16
414 
415 
416 typedef struct {
417   sonic_cd_t cam_desc[CAM_DESCRIPTORS];
418   u16 cam_enable;
419   SREGS_PAD(pad);
420 } sonic_cda_t;
421 #endif  /* endianness */ 
422 
423 /*
424  * Some tunables for the buffer areas. Power of 2 is required
425  * the current driver uses one receive buffer for each descriptor.
426  *
427  * MSch: use more buffer space for the slow m68k Macs!
428  */
429 #ifdef CONFIG_MACSONIC
430 #define SONIC_NUM_RRS    32             /* number of receive resources */
431 #define SONIC_NUM_RDS    SONIC_NUM_RRS  /* number of receive descriptors */
432 #define SONIC_NUM_TDS    32      /* number of transmit descriptors */
433 #else
434 #define SONIC_NUM_RRS    16             /* number of receive resources */
435 #define SONIC_NUM_RDS    SONIC_NUM_RRS  /* number of receive descriptors */
436 #define SONIC_NUM_TDS    16      /* number of transmit descriptors */
437 #endif
438 #define SONIC_RBSIZE   1520      /* size of one resource buffer */
439 
440 #define SONIC_RDS_MASK   (SONIC_NUM_RDS-1)
441 #define SONIC_TDS_MASK   (SONIC_NUM_TDS-1)
442 
443 
444 /* Information that need to be kept for each board. */
445 struct sonic_local {
446     sonic_cda_t   cda;                     /* virtual CPU address of CDA */
447     sonic_td_t    tda[SONIC_NUM_TDS];      /* transmit descriptor area */
448     sonic_rr_t    rra[SONIC_NUM_RRS];      /* receive resource arrea */
449     sonic_rd_t    rda[SONIC_NUM_RDS];      /* receive descriptor area */
450     struct sk_buff* tx_skb[SONIC_NUM_TDS]; /* skbuffs for packets to transmit */
451     unsigned int  tx_laddr[SONIC_NUM_TDS]; /* logical DMA address fro skbuffs */
452     unsigned char *rba;                    /* start of receive buffer areas */    
453     unsigned int  cda_laddr;               /* logical DMA address of CDA */    
454     unsigned int  tda_laddr;               /* logical DMA address of TDA */
455     unsigned int  rra_laddr;               /* logical DMA address of RRA */    
456     unsigned int  rda_laddr;               /* logical DMA address of RDA */
457     unsigned int  rba_laddr;               /* logical DMA address of RBA */
458     unsigned int  cur_rra;                 /* current indexes to resource areas */
459     unsigned int  cur_rx;
460     unsigned int  cur_tx;
461     unsigned int  dirty_tx;                /* last unacked transmit packet */
462     char tx_full;
463     struct net_device_stats stats;
464 };
465 
466 /* Index to functions, as function prototypes. */
467 
468 static int sonic_open(struct net_device *dev);
469 static int sonic_send_packet(struct sk_buff *skb, struct net_device *dev);
470 static void sonic_interrupt(int irq, void *dev_id, struct pt_regs *regs);
471 static void sonic_rx(struct net_device *dev);
472 static int sonic_close(struct net_device *dev);
473 static struct net_device_stats *sonic_get_stats(struct net_device *dev);
474 static void sonic_multicast_list(struct net_device *dev);
475 static int sonic_init(struct net_device *dev);
476 
477 static const char *version =
478         "sonic.c:v0.92 20.9.98 tsbogend@alpha.franken.de\n";
479 
480 #endif /* SONIC_H */
481 

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