1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
2 /*
3 Written 1999-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 */
20
21 /* These identify the driver base version and may not be removed. */
22 static const char version1[] =
23 "sundance.c:v1.01 4/09/00 Written by Donald Becker\n";
24 static const char version2[] =
25 " http://www.scyld.com/network/sundance.html\n";
26
27 /* The user-configurable values.
28 These may be modified when a driver module is loaded.*/
29
30 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
31 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
32 static int max_interrupt_work = 20;
33 static int mtu = 0;
34 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
35 Typical is a 64 element hash table based on the Ethernet CRC. */
36 static int multicast_filter_limit = 32;
37
38 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
39 Setting to > 1518 effectively disables this feature.
40 This chip can receive into offset buffers, so the Alpha does not
41 need a copy-align. */
42 static int rx_copybreak = 0;
43
44 /* Used to pass the media type, etc.
45 Both 'options[]' and 'full_duplex[]' should exist for driver
46 interoperability.
47 The media type is usually passed in 'options[]'.
48 */
49 #define MAX_UNITS 8 /* More are supported, limit only on options */
50 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
51 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
52
53 /* Operational parameters that are set at compile time. */
54
55 /* Keep the ring sizes a power of two for compile efficiency.
56 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
57 Making the Tx ring too large decreases the effectiveness of channel
58 bonding and packet priority, and more than 128 requires modifying the
59 Tx error recovery.
60 Large receive rings merely waste memory. */
61 #define TX_RING_SIZE 16
62 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
63 #define RX_RING_SIZE 32
64
65 /* Operational parameters that usually are not changed. */
66 /* Time in jiffies before concluding the transmitter is hung. */
67 #define TX_TIMEOUT (2*HZ)
68
69 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
70
71 #ifndef __KERNEL__
72 #define __KERNEL__
73 #endif
74 #if !defined(__OPTIMIZE__)
75 #warning You must compile this file with the correct options!
76 #warning See the last lines of the source file.
77 #error You must compile this driver with "-O".
78 #endif
79
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/malloc.h>
88 #include <linux/interrupt.h>
89 #include <linux/pci.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/skbuff.h>
93 #include <linux/init.h>
94 #include <asm/processor.h> /* Processor type for cache alignment. */
95 #include <asm/bitops.h>
96 #include <asm/io.h>
97
98 #include <linux/spinlock.h>
99
100
101 /* Condensed operations for readability. */
102 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
103 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
104
105
106 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
107 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
108 MODULE_PARM(max_interrupt_work, "i");
109 MODULE_PARM(mtu, "i");
110 MODULE_PARM(debug, "i");
111 MODULE_PARM(rx_copybreak, "i");
112 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
113 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
114
115 /*
116 Theory of Operation
117
118 I. Board Compatibility
119
120 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
121
122 II. Board-specific settings
123
124 III. Driver operation
125
126 IIIa. Ring buffers
127
128 This driver uses two statically allocated fixed-size descriptor lists
129 formed into rings by a branch from the final descriptor to the beginning of
130 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
131 Some chips explicitly use only 2^N sized rings, while others use a
132 'next descriptor' pointer that the driver forms into rings.
133
134 IIIb/c. Transmit/Receive Structure
135
136 This driver uses a zero-copy receive and transmit scheme.
137 The driver allocates full frame size skbuffs for the Rx ring buffers at
138 open() time and passes the skb->data field to the chip as receive data
139 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
140 a fresh skbuff is allocated and the frame is copied to the new skbuff.
141 When the incoming frame is larger, the skbuff is passed directly up the
142 protocol stack. Buffers consumed this way are replaced by newly allocated
143 skbuffs in a later phase of receives.
144
145 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
146 using a full-sized skbuff for small frames vs. the copying costs of larger
147 frames. New boards are typically used in generously configured machines
148 and the underfilled buffers have negligible impact compared to the benefit of
149 a single allocation size, so the default value of zero results in never
150 copying packets. When copying is done, the cost is usually mitigated by using
151 a combined copy/checksum routine. Copying also preloads the cache, which is
152 most useful with small frames.
153
154 A subtle aspect of the operation is that the IP header at offset 14 in an
155 ethernet frame isn't longword aligned for further processing.
156 Unaligned buffers are permitted by the Sundance hardware, so
157 frames are received into the skbuff at an offset of "+2", 16-byte aligning
158 the IP header.
159
160 IIId. Synchronization
161
162 The driver runs as two independent, single-threaded flows of control. One
163 is the send-packet routine, which enforces single-threaded use by the
164 dev->tbusy flag. The other thread is the interrupt handler, which is single
165 threaded by the hardware and interrupt handling software.
166
167 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
168 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
169 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
170 the 'lp->tx_full' flag.
171
172 The interrupt handler has exclusive control over the Rx ring and records stats
173 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
174 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
175 clears both the tx_full and tbusy flags.
176
177 IV. Notes
178
179 IVb. References
180
181 The Sundance ST201 datasheet, preliminary version.
182 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
183 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
184
185 IVc. Errata
186
187 */
188
189
190
191 enum pci_id_flags_bits {
192 /* Set PCI command register bits before calling probe1(). */
193 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
194 /* Read and map the single following PCI BAR. */
195 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
196 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
197 };
198 enum chip_capability_flags {CanHaveMII=1, };
199 #ifdef USE_IO_OPS
200 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
201 #else
202 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
203 #endif
204
205 static struct pci_device_id sundance_pci_tbl[] __devinitdata = {
206 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
207 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
208 { 0, }
209 };
210 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
211
212 struct pci_id_info {
213 const char *name;
214 struct match_info {
215 int pci, pci_mask, subsystem, subsystem_mask;
216 int revision, revision_mask; /* Only 8 bits. */
217 } id;
218 enum pci_id_flags_bits pci_flags;
219 int io_size; /* Needed for I/O region check or ioremap(). */
220 int drv_flags; /* Driver use, intended as capability flags. */
221 };
222 static struct pci_id_info pci_id_tbl[] = {
223 {"OEM Sundance Technology ST201", {0x10021186, 0xffffffff, },
224 PCI_IOTYPE, 128, CanHaveMII},
225 {"Sundance Technology Alta", {0x020113F0, 0xffffffff, },
226 PCI_IOTYPE, 128, CanHaveMII},
227 {0,}, /* 0 terminated list. */
228 };
229
230 /* This driver was written to use PCI memory space, however x86-oriented
231 hardware often uses I/O space accesses. */
232 #ifdef USE_IO_OPS
233 #undef readb
234 #undef readw
235 #undef readl
236 #undef writeb
237 #undef writew
238 #undef writel
239 #define readb inb
240 #define readw inw
241 #define readl inl
242 #define writeb outb
243 #define writew outw
244 #define writel outl
245 #endif
246
247 /* Offsets to the device registers.
248 Unlike software-only systems, device drivers interact with complex hardware.
249 It's not useful to define symbolic names for every register bit in the
250 device. The name can only partially document the semantics and make
251 the driver longer and more difficult to read.
252 In general, only the important configuration values or bits changed
253 multiple times should be defined symbolically.
254 */
255 enum alta_offsets {
256 DMACtrl=0x00, TxListPtr=0x04, TxDMACtrl=0x08, TxDescPoll=0x0a,
257 RxDMAStatus=0x0c, RxListPtr=0x10, RxDMACtrl=0x14, RxDescPoll=0x16,
258 LEDCtrl=0x1a, ASICCtrl=0x30,
259 EEData=0x34, EECtrl=0x36, TxThreshold=0x3c,
260 FlashAddr=0x40, FlashData=0x44, TxStatus=0x46, DownCounter=0x48,
261 IntrClear=0x4a, IntrEnable=0x4c, IntrStatus=0x4e,
262 MACCtrl0=0x50, MACCtrl1=0x52, StationAddr=0x54,
263 MaxTxSize=0x5A, RxMode=0x5c, MIICtrl=0x5e,
264 MulticastFilter0=0x60, MulticastFilter1=0x64,
265 RxOctetsLow=0x68, RxOctetsHigh=0x6a, TxOctetsLow=0x6c, TxOctetsHigh=0x6e,
266 TxFramesOK=0x70, RxFramesOK=0x72, StatsCarrierError=0x74,
267 StatsLateColl=0x75, StatsMultiColl=0x76, StatsOneColl=0x77,
268 StatsTxDefer=0x78, RxMissed=0x79, StatsTxXSDefer=0x7a, StatsTxAbort=0x7b,
269 StatsBcastTx=0x7c, StatsBcastRx=0x7d, StatsMcastTx=0x7e, StatsMcastRx=0x7f,
270 /* Aliased and bogus values! */
271 RxStatus=0x0c,
272 };
273
274 /* Bits in the interrupt status/mask registers. */
275 enum intr_status_bits {
276 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
277 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
278 IntrDrvRqst=0x0040,
279 StatsMax=0x0080, LinkChange=0x0100,
280 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
281 };
282
283 /* Bits in the RxMode register. */
284 enum rx_mode_bits {
285 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
286 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
287 };
288 /* Bits in MACCtrl. */
289 enum mac_ctrl0_bits {
290 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
291 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
292 };
293 enum mac_ctrl1_bits {
294 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
295 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
296 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
297 };
298
299 /* The Rx and Tx buffer descriptors. */
300 /* Note that using only 32 bit fields simplifies conversion to big-endian
301 architectures. */
302 struct netdev_desc {
303 u32 next_desc;
304 u32 status;
305 struct desc_frag { u32 addr, length; } frag[1];
306 };
307
308 /* Bits in netdev_desc.status */
309 enum desc_status_bits {
310 DescOwn=0x8000, DescEndPacket=0x4000, DescEndRing=0x2000,
311 LastFrag=0x80000000, DescIntrOnTx=0x8000, DescIntrOnDMADone=0x80000000,
312 };
313
314 #define PRIV_ALIGN 15 /* Required alignment mask */
315 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
316 within the structure. */
317 struct netdev_private {
318 /* Descriptor rings first for alignment. */
319 struct netdev_desc rx_ring[RX_RING_SIZE];
320 struct netdev_desc tx_ring[TX_RING_SIZE];
321 /* The addresses of receive-in-place skbuffs. */
322 struct sk_buff* rx_skbuff[RX_RING_SIZE];
323 /* The saved address of a sent-in-place packet/buffer, for later free(). */
324 struct sk_buff* tx_skbuff[TX_RING_SIZE];
325 struct net_device_stats stats;
326 struct timer_list timer; /* Media monitoring timer. */
327 /* Frequently used values: keep some adjacent for cache effect. */
328 spinlock_t lock;
329 int chip_id, drv_flags;
330 /* Note: Cache paragraph grouped variables. */
331 struct netdev_desc *rx_head_desc;
332 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
333 unsigned int rx_buf_sz; /* Based on MTU+slack. */
334 spinlock_t txlock; /* Group with Tx control cache line. */
335 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
336 unsigned int cur_tx, dirty_tx;
337 unsigned int tx_full:1; /* The Tx queue is full. */
338 /* These values are keep track of the transceiver/media in use. */
339 unsigned int full_duplex:1; /* Full-duplex operation requested. */
340 unsigned int duplex_lock:1;
341 unsigned int medialock:1; /* Do not sense media. */
342 unsigned int default_port:4; /* Last dev->if_port value. */
343 /* Multicast and receive mode. */
344 spinlock_t mcastlock; /* SMP lock multicast updates. */
345 u16 mcast_filter[4];
346 /* MII transceiver section. */
347 int mii_cnt; /* MII device addresses. */
348 u16 advertising; /* NWay media advertisement */
349 unsigned char phys[2]; /* MII device addresses. */
350 };
351
352 /* The station address location in the EEPROM. */
353 #define EEPROM_SA_OFFSET 0x10
354
355 static int eeprom_read(long ioaddr, int location);
356 static int mdio_read(struct net_device *dev, int phy_id, int location);
357 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
358 static int netdev_open(struct net_device *dev);
359 static void check_duplex(struct net_device *dev);
360 static void netdev_timer(unsigned long data);
361 static void tx_timeout(struct net_device *dev);
362 static void init_ring(struct net_device *dev);
363 static int start_tx(struct sk_buff *skb, struct net_device *dev);
364 static void intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
365 static void netdev_error(struct net_device *dev, int intr_status);
366 static int netdev_rx(struct net_device *dev);
367 static void netdev_error(struct net_device *dev, int intr_status);
368 static void set_rx_mode(struct net_device *dev);
369 static struct net_device_stats *get_stats(struct net_device *dev);
370 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
371 static int netdev_close(struct net_device *dev);
372
373
374
375 static int __devinit sundance_probe1 (struct pci_dev *pdev,
376 const struct pci_device_id *ent)
377 {
378 struct net_device *dev;
379 struct netdev_private *np;
380 static int card_idx;
381 int chip_idx = ent->driver_data;
382 int irq = pdev->irq;
383 int i, option = card_idx < MAX_UNITS ? options[card_idx] : 0;
384 long ioaddr;
385
386 if (pci_enable_device(pdev))
387 return -EIO;
388 pci_set_master(pdev);
389
390 dev = init_etherdev(NULL, sizeof(*np));
391 if (!dev)
392 return -ENOMEM;
393 SET_MODULE_OWNER(dev);
394
395 #ifdef USE_IO_OPS
396 ioaddr = pci_resource_start(pdev, 0);
397 if (!request_region(ioaddr, pci_id_tbl[chip_idx].io_size, dev->name))
398 goto err_out_netdev;
399 #else
400 ioaddr = pci_resource_start(pdev, 1);
401 if (!request_mem_region(ioaddr, pci_id_tbl[chip_idx].io_size, dev->name))
402 goto err_out_netdev;
403 ioaddr = (long) ioremap (ioaddr, pci_id_tbl[chip_idx].io_size);
404 if (!ioaddr)
405 goto err_out_iomem;
406 #endif
407
408 printk(KERN_INFO "%s: %s at 0x%lx, ",
409 dev->name, pci_id_tbl[chip_idx].name, ioaddr);
410
411 for (i = 0; i < 3; i++)
412 ((u16 *)dev->dev_addr)[i] =
413 le16_to_cpu(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
414 for (i = 0; i < 5; i++)
415 printk("%2.2x:", dev->dev_addr[i]);
416 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
417
418 dev->base_addr = ioaddr;
419 dev->irq = irq;
420
421 np = dev->priv;
422 np->chip_id = chip_idx;
423 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
424 spin_lock_init(&np->lock);
425
426 if (dev->mem_start)
427 option = dev->mem_start;
428
429 /* The lower four bits are the media type. */
430 if (option > 0) {
431 if (option & 0x200)
432 np->full_duplex = 1;
433 np->default_port = option & 15;
434 if (np->default_port)
435 np->medialock = 1;
436 }
437 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
438 np->full_duplex = 1;
439
440 if (np->full_duplex)
441 np->duplex_lock = 1;
442
443 /* The chip-specific entries in the device structure. */
444 dev->open = &netdev_open;
445 dev->hard_start_xmit = &start_tx;
446 dev->stop = &netdev_close;
447 dev->get_stats = &get_stats;
448 dev->set_multicast_list = &set_rx_mode;
449 dev->do_ioctl = &mii_ioctl;
450 dev->tx_timeout = &tx_timeout;
451 dev->watchdog_timeo = TX_TIMEOUT;
452
453 if (mtu)
454 dev->mtu = mtu;
455
456 if (1) {
457 int phy, phy_idx = 0;
458 np->phys[0] = 1; /* Default setting */
459 for (phy = 0; phy < 32 && phy_idx < 4; phy++) {
460 int mii_status = mdio_read(dev, phy, 1);
461 if (mii_status != 0xffff && mii_status != 0x0000) {
462 np->phys[phy_idx++] = phy;
463 np->advertising = mdio_read(dev, phy, 4);
464 printk(KERN_INFO "%s: MII PHY found at address %d, status "
465 "0x%4.4x advertising %4.4x.\n",
466 dev->name, phy, mii_status, np->advertising);
467 }
468 }
469 np->mii_cnt = phy_idx;
470 if (phy_idx == 0)
471 printk(KERN_INFO "%s: No MII transceiver found!, ASIC status %x\n",
472 dev->name, readl(ioaddr + ASICCtrl));
473 }
474
475 /* Perhaps move the reset here? */
476 /* Reset the chip to erase previous misconfiguration. */
477 if (debug > 1)
478 printk("ASIC Control is %x.\n", readl(ioaddr + ASICCtrl));
479 writew(0x007f, ioaddr + ASICCtrl + 2);
480 if (debug > 1)
481 printk("ASIC Control is now %x.\n", readl(ioaddr + ASICCtrl));
482
483 card_idx++;
484 return 0;
485
486 #ifndef USE_IO_OPS
487 err_out_iomem:
488 release_mem_region(pci_resource_start(pdev, 1),
489 pci_id_tbl[chip_idx].io_size);
490 #endif
491 err_out_netdev:
492 unregister_netdev (dev);
493 kfree (dev);
494 return -ENODEV;
495 }
496
497
498 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
499 static int eeprom_read(long ioaddr, int location)
500 {
501 int boguscnt = 1000; /* Typical 190 ticks. */
502 writew(0x0200 | (location & 0xff), ioaddr + EECtrl);
503 do {
504 if (! (readw(ioaddr + EECtrl) & 0x8000)) {
505 return readw(ioaddr + EEData);
506 }
507 } while (--boguscnt > 0);
508 return 0;
509 }
510
511 /* MII transceiver control section.
512 Read and write the MII registers using software-generated serial
513 MDIO protocol. See the MII specifications or DP83840A data sheet
514 for details.
515
516 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
517 met by back-to-back 33Mhz PCI cycles. */
518 #define mdio_delay() readb(mdio_addr)
519
520 /* Set iff a MII transceiver on any interface requires mdio preamble.
521 This only set with older tranceivers, so the extra
522 code size of a per-interface flag is not worthwhile. */
523 static char mii_preamble_required = 0;
524
525 enum mii_reg_bits {
526 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
527 };
528 #define MDIO_EnbIn (0)
529 #define MDIO_WRITE0 (MDIO_EnbOutput)
530 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
531
532 /* Generate the preamble required for initial synchronization and
533 a few older transceivers. */
534 static void mdio_sync(long mdio_addr)
535 {
536 int bits = 32;
537
538 /* Establish sync by sending at least 32 logic ones. */
539 while (--bits >= 0) {
540 writeb(MDIO_WRITE1, mdio_addr);
541 mdio_delay();
542 writeb(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
543 mdio_delay();
544 }
545 }
546
547 static int mdio_read(struct net_device *dev, int phy_id, int location)
548 {
549 long mdio_addr = dev->base_addr + MIICtrl;
550 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
551 int i, retval = 0;
552
553 if (mii_preamble_required)
554 mdio_sync(mdio_addr);
555
556 /* Shift the read command bits out. */
557 for (i = 15; i >= 0; i--) {
558 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
559
560 writeb(dataval, mdio_addr);
561 mdio_delay();
562 writeb(dataval | MDIO_ShiftClk, mdio_addr);
563 mdio_delay();
564 }
565 /* Read the two transition, 16 data, and wire-idle bits. */
566 for (i = 19; i > 0; i--) {
567 writeb(MDIO_EnbIn, mdio_addr);
568 mdio_delay();
569 retval = (retval << 1) | ((readb(mdio_addr) & MDIO_Data) ? 1 : 0);
570 writeb(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
571 mdio_delay();
572 }
573 return (retval>>1) & 0xffff;
574 }
575
576 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
577 {
578 long mdio_addr = dev->base_addr + MIICtrl;
579 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
580 int i;
581
582 if (mii_preamble_required)
583 mdio_sync(mdio_addr);
584
585 /* Shift the command bits out. */
586 for (i = 31; i >= 0; i--) {
587 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
588
589 writeb(dataval, mdio_addr);
590 mdio_delay();
591 writeb(dataval | MDIO_ShiftClk, mdio_addr);
592 mdio_delay();
593 }
594 /* Clear out extra bits. */
595 for (i = 2; i > 0; i--) {
596 writeb(MDIO_EnbIn, mdio_addr);
597 mdio_delay();
598 writeb(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
599 mdio_delay();
600 }
601 return;
602 }
603
604
605 static int netdev_open(struct net_device *dev)
606 {
607 struct netdev_private *np = (struct netdev_private *)dev->priv;
608 long ioaddr = dev->base_addr;
609 int i;
610
611 /* Do we need to reset the chip??? */
612
613 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
614 if (i)
615 return i;
616
617 if (debug > 1)
618 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
619 dev->name, dev->irq);
620
621 init_ring(dev);
622
623 writel(virt_to_bus(np->rx_ring), ioaddr + RxListPtr);
624 /* The Tx list pointer is written as packets are queued. */
625
626 for (i = 0; i < 6; i++)
627 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
628
629 /* Initialize other registers. */
630 /* Configure the PCI bus bursts and FIFO thresholds. */
631
632 if (dev->if_port == 0)
633 dev->if_port = np->default_port;
634
635 np->full_duplex = np->duplex_lock;
636 np->mcastlock = (spinlock_t) SPIN_LOCK_UNLOCKED;
637
638 set_rx_mode(dev);
639 writew(0, ioaddr + DownCounter);
640 /* Set the chip to poll every N*320nsec. */
641 writeb(100, ioaddr + RxDescPoll);
642 writeb(127, ioaddr + TxDescPoll);
643 netif_start_queue(dev);
644
645 /* Enable interrupts by setting the interrupt mask. */
646 writew(IntrRxDone | IntrRxDMADone | IntrPCIErr | IntrDrvRqst | IntrTxDone
647 | StatsMax | LinkChange, ioaddr + IntrEnable);
648
649 writew(StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
650
651 if (debug > 2)
652 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
653 "MAC Control %x, %4.4x %4.4x.\n",
654 dev->name, readl(ioaddr + RxStatus), readb(ioaddr + TxStatus),
655 readl(ioaddr + MACCtrl0),
656 readw(ioaddr + MACCtrl1), readw(ioaddr + MACCtrl0));
657
658 /* Set the timer to check for link beat. */
659 init_timer(&np->timer);
660 np->timer.expires = jiffies + 3*HZ;
661 np->timer.data = (unsigned long)dev;
662 np->timer.function = &netdev_timer; /* timer handler */
663 add_timer(&np->timer);
664
665 return 0;
666 }
667
668 static void check_duplex(struct net_device *dev)
669 {
670 struct netdev_private *np = (struct netdev_private *)dev->priv;
671 long ioaddr = dev->base_addr;
672 int mii_reg5 = mdio_read(dev, np->phys[0], 5);
673 int negotiated = mii_reg5 & np->advertising;
674 int duplex;
675
676 if (np->duplex_lock || mii_reg5 == 0xffff)
677 return;
678 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
679 if (np->full_duplex != duplex) {
680 np->full_duplex = duplex;
681 if (debug)
682 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
683 "negotiated capability %4.4x.\n", dev->name,
684 duplex ? "full" : "half", np->phys[0], negotiated);
685 writew(duplex ? 0x20 : 0, ioaddr + MACCtrl0);
686 }
687 }
688
689 static void netdev_timer(unsigned long data)
690 {
691 struct net_device *dev = (struct net_device *)data;
692 struct netdev_private *np = (struct netdev_private *)dev->priv;
693 long ioaddr = dev->base_addr;
694 int next_tick = 10*HZ;
695
696 if (debug > 3) {
697 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
698 "Tx %x Rx %x.\n",
699 dev->name, readw(ioaddr + IntrEnable),
700 readb(ioaddr + TxStatus), readl(ioaddr + RxStatus));
701 }
702 check_duplex(dev);
703 np->timer.expires = jiffies + next_tick;
704 add_timer(&np->timer);
705 }
706
707 static void tx_timeout(struct net_device *dev)
708 {
709 struct netdev_private *np = (struct netdev_private *)dev->priv;
710 long ioaddr = dev->base_addr;
711
712 printk(KERN_WARNING "%s: Transmit timed out, status %2.2x,"
713 " resetting...\n", dev->name, readb(ioaddr + TxStatus));
714
715 #ifndef __alpha__
716 {
717 int i;
718 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)np->rx_ring);
719 for (i = 0; i < RX_RING_SIZE; i++)
720 printk(" %8.8x", (unsigned int)np->rx_ring[i].status);
721 printk("\n"KERN_DEBUG" Tx ring %8.8x: ", (int)np->tx_ring);
722 for (i = 0; i < TX_RING_SIZE; i++)
723 printk(" %4.4x", np->tx_ring[i].status);
724 printk("\n");
725 }
726 #endif
727
728 /* Perhaps we should reinitialize the hardware here. */
729 dev->if_port = 0;
730 /* Stop and restart the chip's Tx processes . */
731
732 /* Trigger an immediate transmit demand. */
733 writew(IntrRxDone | IntrRxDMADone | IntrPCIErr | IntrDrvRqst | IntrTxDone
734 | StatsMax | LinkChange, ioaddr + IntrEnable);
735
736 dev->trans_start = jiffies;
737 np->stats.tx_errors++;
738 return;
739 }
740
741
742 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
743 static void init_ring(struct net_device *dev)
744 {
745 struct netdev_private *np = (struct netdev_private *)dev->priv;
746 int i;
747
748 np->tx_full = 0;
749 np->cur_rx = np->cur_tx = 0;
750 np->dirty_rx = np->dirty_tx = 0;
751
752 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
753 np->rx_head_desc = &np->rx_ring[0];
754
755 /* Initialize all Rx descriptors. */
756 for (i = 0; i < RX_RING_SIZE; i++) {
757 np->rx_ring[i].next_desc = virt_to_le32desc(&np->rx_ring[i+1]);
758 np->rx_ring[i].status = 0;
759 np->rx_ring[i].frag[0].length = 0;
760 np->rx_skbuff[i] = 0;
761 }
762 /* Wrap the ring. */
763 np->rx_ring[i-1].next_desc = virt_to_le32desc(&np->rx_ring[0]);
764
765 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
766 for (i = 0; i < RX_RING_SIZE; i++) {
767 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
768 np->rx_skbuff[i] = skb;
769 if (skb == NULL)
770 break;
771 skb->dev = dev; /* Mark as being used by this device. */
772 skb_reserve(skb, 2); /* 16 byte align the IP header. */
773 np->rx_ring[i].frag[0].addr = virt_to_le32desc(skb->tail);
774 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
775 }
776 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
777
778 for (i = 0; i < TX_RING_SIZE; i++) {
779 np->tx_skbuff[i] = 0;
780 np->tx_ring[i].status = 0;
781 }
782 return;
783 }
784
785 static int start_tx(struct sk_buff *skb, struct net_device *dev)
786 {
787 struct netdev_private *np = (struct netdev_private *)dev->priv;
788 struct netdev_desc *txdesc;
789 unsigned entry;
790
791 /* Note: Ordering is important here, set the field with the
792 "ownership" bit last, and only then increment cur_tx. */
793
794 /* Calculate the next Tx descriptor entry. */
795 entry = np->cur_tx % TX_RING_SIZE;
796 np->tx_skbuff[entry] = skb;
797 txdesc = &np->tx_ring[entry];
798
799 txdesc->next_desc = 0;
800 /* Note: disable the interrupt generation here before releasing. */
801 txdesc->status =
802 cpu_to_le32((entry<<2) | DescIntrOnDMADone | DescIntrOnTx);
803 txdesc->frag[0].addr = virt_to_le32desc(skb->data);
804 txdesc->frag[0].length = cpu_to_le32(skb->len | LastFrag);
805 if (np->last_tx)
806 np->last_tx->next_desc = virt_to_le32desc(txdesc);
807 np->last_tx = txdesc;
808 np->cur_tx++;
809
810 /* On some architectures: explicitly flush cache lines here. */
811
812 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1) {
813 /* do nothing */
814 } else {
815 np->tx_full = 1;
816 netif_stop_queue(dev);
817 }
818 /* Side effect: The read wakes the potentially-idle transmit channel. */
819 if (readl(dev->base_addr + TxListPtr) == 0)
820 writel(virt_to_bus(&np->tx_ring[entry]), dev->base_addr + TxListPtr);
821
822 dev->trans_start = jiffies;
823
824 if (debug > 4) {
825 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
826 dev->name, np->cur_tx, entry);
827 }
828 return 0;
829 }
830
831 /* The interrupt handler does all of the Rx thread work and cleans up
832 after the Tx thread. */
833 static void intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
834 {
835 struct net_device *dev = (struct net_device *)dev_instance;
836 struct netdev_private *np;
837 long ioaddr;
838 int boguscnt = max_interrupt_work;
839
840 ioaddr = dev->base_addr;
841 np = (struct netdev_private *)dev->priv;
842 spin_lock(&np->lock);
843
844 do {
845 int intr_status = readw(ioaddr + IntrStatus);
846 writew(intr_status & (IntrRxDone | IntrRxDMADone | IntrPCIErr |
847 IntrDrvRqst |IntrTxDone|IntrTxDMADone |
848 StatsMax | LinkChange),
849 ioaddr + IntrStatus);
850
851 if (debug > 4)
852 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
853 dev->name, intr_status);
854
855 if (intr_status == 0)
856 break;
857
858 if (intr_status & (IntrRxDone|IntrRxDMADone))
859 netdev_rx(dev);
860
861 if (intr_status & IntrTxDone) {
862 int boguscnt = 32;
863 int tx_status = readw(ioaddr + TxStatus);
864 while (tx_status & 0x80) {
865 if (debug > 4)
866 printk("%s: Transmit status is %2.2x.\n",
867 dev->name, tx_status);
868 if (tx_status & 0x1e) {
869 np->stats.tx_errors++;
870 if (tx_status & 0x10) np->stats.tx_fifo_errors++;
871 #ifdef ETHER_STATS
872 if (tx_status & 0x08) np->stats.collisions16++;
873 #else
874 if (tx_status & 0x08) np->stats.collisions++;
875 #endif
876 if (tx_status & 0x04) np->stats.tx_fifo_errors++;
877 if (tx_status & 0x02) np->stats.tx_window_errors++;
878 /* This reset has not been verified!. */
879 if (tx_status & 0x10) { /* Reset the Tx. */
880 writew(0x001c, ioaddr + ASICCtrl + 2);
881 #if 0 /* Do we need to reset the Tx pointer here? */
882 writel(virt_to_bus(&np->tx_ring[np->dirty_tx]),
883 dev->base_addr + TxListPtr);
884 #endif
885 }
886 if (tx_status & 0x1e) /* Restart the Tx. */
887 writew(TxEnable, ioaddr + MACCtrl1);
888 }
889 /* Yup, this is a documentation bug. It cost me *hours*. */
890 writew(0, ioaddr + TxStatus);
891 tx_status = readb(ioaddr + TxStatus);
892 if (--boguscnt < 0)
893 break;
894 }
895 }
896 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
897 int entry = np->dirty_tx % TX_RING_SIZE;
898 if ( ! (np->tx_ring[entry].status & 0x00010000))
899 break;
900 /* Free the original skb. */
901 dev_kfree_skb_irq(np->tx_skbuff[entry]);
902 np->tx_skbuff[entry] = 0;
903 }
904 if (np->tx_full
905 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
906 /* The ring is no longer full, clear tbusy. */
907 np->tx_full = 0;
908 netif_wake_queue(dev);
909 }
910
911 /* Abnormal error summary/uncommon events handlers. */
912 if (intr_status & (IntrDrvRqst | IntrPCIErr | LinkChange | StatsMax))
913 netdev_error(dev, intr_status);
914
915 if (--boguscnt < 0) {
916 get_stats(dev);
917 printk(KERN_WARNING "%s: Too much work at interrupt, "
918 "status=0x%4.4x / 0x%4.4x.\n",
919 dev->name, intr_status, readw(ioaddr + IntrClear));
920 /* Re-enable us in 3.2msec. */
921 writew(1000, ioaddr + DownCounter);
922 writew(IntrDrvRqst, ioaddr + IntrEnable);
923 break;
924 }
925 } while (1);
926
927 if (debug > 3)
928 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
929 dev->name, readw(ioaddr + IntrStatus));
930
931 spin_unlock(&np->lock);
932 }
933
934 /* This routine is logically part of the interrupt handler, but separated
935 for clarity and better register allocation. */
936 static int netdev_rx(struct net_device *dev)
937 {
938 struct netdev_private *np = (struct netdev_private *)dev->priv;
939 int entry = np->cur_rx % RX_RING_SIZE;
940 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
941
942 if (debug > 4) {
943 printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n",
944 entry, np->rx_ring[entry].status);
945 }
946
947 /* If EOP is set on the next entry, it's a new packet. Send it up. */
948 while (np->rx_head_desc->status & DescOwn) {
949 struct netdev_desc *desc = np->rx_head_desc;
950 u32 frame_status = le32_to_cpu(desc->status);
951 int pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
952
953 if (debug > 4)
954 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
955 frame_status);
956 if (--boguscnt < 0)
957 break;
958 if (frame_status & 0x001f4000) {
959 /* There was a error. */
960 if (debug > 2)
961 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
962 frame_status);
963 np->stats.rx_errors++;
964 if (frame_status & 0x00100000) np->stats.rx_length_errors++;
965 if (frame_status & 0x00010000) np->stats.rx_fifo_errors++;
966 if (frame_status & 0x00060000) np->stats.rx_frame_errors++;
967 if (frame_status & 0x00080000) np->stats.rx_crc_errors++;
968 if (frame_status & 0x00100000) {
969 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
970 " status %8.8x.\n",
971 dev->name, frame_status);
972 }
973 } else {
974 struct sk_buff *skb;
975
976 #ifndef final_version
977 if (debug > 4)
978 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
979 ", bogus_cnt %d.\n",
980 pkt_len, boguscnt);
981 #endif
982 /* Check if the packet is long enough to accept without copying
983 to a minimally-sized skbuff. */
984 if (pkt_len < rx_copybreak
985 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
986 skb->dev = dev;
987 skb_reserve(skb, 2); /* 16 byte align the IP header */
988 eth_copy_and_sum(skb, np->rx_skbuff[entry]->tail, pkt_len, 0);
989 skb_put(skb, pkt_len);
990 } else {
991 skb_put(skb = np->rx_skbuff[entry], pkt_len);
992 np->rx_skbuff[entry] = NULL;
993 }
994 skb->protocol = eth_type_trans(skb, dev);
995 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
996 netif_rx(skb);
997 dev->last_rx = jiffies;
998 }
999 entry = (++np->cur_rx) % RX_RING_SIZE;
1000 np->rx_head_desc = &np->rx_ring[entry];
1001 }
1002
1003 /* Refill the Rx ring buffers. */
1004 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1005 struct sk_buff *skb;
1006 entry = np->dirty_rx % RX_RING_SIZE;
1007 if (np->rx_skbuff[entry] == NULL) {
1008 skb = dev_alloc_skb(np->rx_buf_sz);
1009 np->rx_skbuff[entry] = skb;
1010 if (skb == NULL)
1011 break; /* Better luck next round. */
1012 skb->dev = dev; /* Mark as being used by this device. */
1013 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1014 np->rx_ring[entry].frag[0].addr = virt_to_le32desc(skb->tail);
1015 }
1016 /* Perhaps we need not reset this field. */
1017 np->rx_ring[entry].frag[0].length =
1018 cpu_to_le32(np->rx_buf_sz | LastFrag);
1019 np->rx_ring[entry].status = 0;
1020 }
1021
1022 /* No need to restart Rx engine, it will poll. */
1023 return 0;
1024 }
1025
1026 static void netdev_error(struct net_device *dev, int intr_status)
1027 {
1028 long ioaddr = dev->base_addr;
1029 struct netdev_private *np = (struct netdev_private *)dev->priv;
1030
1031 if (intr_status & IntrDrvRqst) {
1032 /* Stop the down counter and turn interrupts back on. */
1033 printk("%s: Turning interrupts back on.\n", dev->name);
1034 writew(0, ioaddr + DownCounter);
1035 writew(IntrRxDone | IntrRxDMADone | IntrPCIErr | IntrDrvRqst |
1036 IntrTxDone | StatsMax | LinkChange, ioaddr + IntrEnable);
1037 }
1038 if (intr_status & LinkChange) {
1039 printk(KERN_ERR "%s: Link changed: Autonegotiation advertising"
1040 " %4.4x partner %4.4x.\n", dev->name,
1041 mdio_read(dev, np->phys[0], 4),
1042 mdio_read(dev, np->phys[0], 5));
1043 check_duplex(dev);
1044 }
1045 if (intr_status & StatsMax) {
1046 get_stats(dev);
1047 }
1048 if (intr_status & IntrPCIErr) {
1049 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1050 dev->name, intr_status);
1051 /* We must do a global reset of DMA to continue. */
1052 }
1053 }
1054
1055 static struct net_device_stats *get_stats(struct net_device *dev)
1056 {
1057 long ioaddr = dev->base_addr;
1058 struct netdev_private *np = (struct netdev_private *)dev->priv;
1059 int i;
1060
1061 /* We should lock this segment of code for SMP eventually, although
1062 the vulnerability window is very small and statistics are
1063 non-critical. */
1064 /* The chip only need report frame silently dropped. */
1065 np->stats.rx_missed_errors += readb(ioaddr + RxMissed);
1066 np->stats.tx_packets += readw(ioaddr + TxFramesOK);
1067 np->stats.rx_packets += readw(ioaddr + RxFramesOK);
1068 np->stats.collisions += readb(ioaddr + StatsLateColl);
1069 np->stats.collisions += readb(ioaddr + StatsMultiColl);
1070 np->stats.collisions += readb(ioaddr + StatsOneColl);
1071 readb(ioaddr + StatsCarrierError);
1072 readb(ioaddr + StatsTxDefer);
1073 for (i = StatsTxDefer; i <= StatsMcastRx; i++)
1074 readb(ioaddr + i);
1075 np->stats.tx_bytes += readw(ioaddr + TxOctetsLow);
1076 np->stats.tx_bytes += readw(ioaddr + TxOctetsHigh) << 16;
1077 np->stats.rx_bytes += readw(ioaddr + RxOctetsLow);
1078 np->stats.rx_bytes += readw(ioaddr + RxOctetsHigh) << 16;
1079
1080 return &np->stats;
1081 }
1082
1083 /* The little-endian AUTODIN II ethernet CRC calculations.
1084 A big-endian version is also available.
1085 This is slow but compact code. Do not use this routine for bulk data,
1086 use a table-based routine instead.
1087 This is common code and should be moved to net/core/crc.c.
1088 Chips may use the upper or lower CRC bits, and may reverse and/or invert
1089 them. Select the endian-ness that results in minimal calculations.
1090 */
1091 static unsigned const ethernet_polynomial_le = 0xedb88320U;
1092 static inline unsigned ether_crc_le(int length, unsigned char *data)
1093 {
1094 unsigned int crc = 0xffffffff; /* Initial value. */
1095 while(--length >= 0) {
1096 unsigned char current_octet = *data++;
1097 int bit;
1098 for (bit = 8; --bit >= 0; current_octet >>= 1) {
1099 if ((crc ^ current_octet) & 1) {
1100 crc >>= 1;
1101 crc ^= ethernet_polynomial_le;
1102 } else
1103 crc >>= 1;
1104 }
1105 }
1106 return crc;
1107 }
1108
1109 static void set_rx_mode(struct net_device *dev)
1110 {
1111 long ioaddr = dev->base_addr;
1112 u16 mc_filter[4]; /* Multicast hash filter */
1113 u32 rx_mode;
1114 int i;
1115
1116 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1117 /* Unconditionally log net taps. */
1118 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1119 memset(mc_filter, 0xff, sizeof(mc_filter));
1120 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1121 } else if ((dev->mc_count > multicast_filter_limit)
1122 || (dev->flags & IFF_ALLMULTI)) {
1123 /* Too many to match, or accept all multicasts. */
1124 memset(mc_filter, 0xff, sizeof(mc_filter));
1125 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1126 } else if (dev->mc_count) {
1127 struct dev_mc_list *mclist;
1128 memset(mc_filter, 0, sizeof(mc_filter));
1129 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1130 i++, mclist = mclist->next) {
1131 set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f,
1132 mc_filter);
1133 }
1134 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1135 } else {
1136 writeb(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1137 return;
1138 }
1139 for (i = 0; i < 4; i++)
1140 writew(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1141 writeb(rx_mode, ioaddr + RxMode);
1142 }
1143
1144 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1145 {
1146 u16 *data = (u16 *)&rq->ifr_data;
1147
1148 switch(cmd) {
1149 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1150 data[0] = ((struct netdev_private *)dev->priv)->phys[0] & 0x1f;
1151 /* Fall Through */
1152 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1153 data[3] = mdio_read(dev, data[0] & 0x1f, data[1] & 0x1f);
1154 return 0;
1155 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1156 if (!capable(CAP_NET_ADMIN))
1157 return -EPERM;
1158 mdio_write(dev, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1159 return 0;
1160 default:
1161 return -EOPNOTSUPP;
1162 }
1163 }
1164
1165 static int netdev_close(struct net_device *dev)
1166 {
1167 long ioaddr = dev->base_addr;
1168 struct netdev_private *np = (struct netdev_private *)dev->priv;
1169 int i;
1170
1171 netif_stop_queue(dev);
1172
1173 if (debug > 1) {
1174 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1175 "Rx %4.4x Int %2.2x.\n",
1176 dev->name, readb(ioaddr + TxStatus),
1177 readl(ioaddr + RxStatus), readw(ioaddr + IntrStatus));
1178 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1179 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1180 }
1181
1182 /* Disable interrupts by clearing the interrupt mask. */
1183 writew(0x0000, ioaddr + IntrEnable);
1184
1185 /* Stop the chip's Tx and Rx processes. */
1186 writew(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1187
1188 #ifdef __i386__
1189 if (debug > 2) {
1190 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1191 (int)virt_to_bus(np->tx_ring));
1192 for (i = 0; i < TX_RING_SIZE; i++)
1193 printk(" #%d desc. %4.4x %8.8x %8.8x.\n",
1194 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1195 np->tx_ring[i].frag[0].length);
1196 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1197 (int)virt_to_bus(np->rx_ring));
1198 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1199 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1200 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1201 np->rx_ring[i].frag[0].length);
1202 }
1203 }
1204 #endif /* __i386__ debugging only */
1205
1206 free_irq(dev->irq, dev);
1207
1208 del_timer_sync(&np->timer);
1209
1210 /* Free all the skbuffs in the Rx queue. */
1211 for (i = 0; i < RX_RING_SIZE; i++) {
1212 np->rx_ring[i].status = 0;
1213 np->rx_ring[i].frag[0].addr = 0xBADF00D0; /* An invalid address. */
1214 if (np->rx_skbuff[i]) {
1215 dev_kfree_skb(np->rx_skbuff[i]);
1216 }
1217 np->rx_skbuff[i] = 0;
1218 }
1219 for (i = 0; i < TX_RING_SIZE; i++) {
1220 if (np->tx_skbuff[i])
1221 dev_kfree_skb(np->tx_skbuff[i]);
1222 np->tx_skbuff[i] = 0;
1223 }
1224
1225 return 0;
1226 }
1227
1228 static void __devexit sundance_remove1 (struct pci_dev *pdev)
1229 {
1230 struct net_device *dev = pdev->driver_data;
1231
1232 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1233 while (dev) {
1234 struct netdev_private *np = (void *)(dev->priv);
1235 unregister_netdev(dev);
1236 #ifdef USE_IO_OPS
1237 release_region(dev->base_addr, pci_id_tbl[np->chip_id].io_size);
1238 #else
1239 release_mem_region(pci_resource_start(pdev, 1),
1240 pci_id_tbl[np->chip_id].io_size);
1241 iounmap((char *)(dev->base_addr));
1242 #endif
1243 kfree(dev);
1244 }
1245
1246 pdev->driver_data = NULL;
1247 }
1248
1249 static struct pci_driver sundance_driver = {
1250 name: "sundance",
1251 id_table: sundance_pci_tbl,
1252 probe: sundance_probe1,
1253 remove: sundance_remove1,
1254 };
1255
1256 static int __init sundance_init(void)
1257 {
1258 return pci_module_init(&sundance_driver);
1259 }
1260
1261 static void __exit sundance_exit(void)
1262 {
1263 pci_unregister_driver(&sundance_driver);
1264 }
1265
1266 module_init(sundance_init);
1267 module_exit(sundance_exit);
1268
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