1 #ifndef TLAN_H
2 #define TLAN_H
3 /********************************************************************
4 *
5 * Linux ThunderLAN Driver
6 *
7 * tlan.h
8 * by James Banks
9 *
10 * (C) 1997-1998 Caldera, Inc.
11 * (C) 1999-2000 Torben Mathiasen
12 *
13 * This software may be used and distributed according to the terms
14 * of the GNU Public License, incorporated herein by reference.
15 *
16 ** This file is best viewed/edited with tabstop=4, colums>=132
17 *
18 *
19 * Dec 10, 1999 Torben Mathiasen <torben.mathiasen@compaq.com>
20 * New Maintainer
21 *
22 ********************************************************************/
23
24
25 #include <asm/io.h>
26 #include <asm/types.h>
27 #include <linux/netdevice.h>
28
29
30
31 /*****************************************************************
32 * TLan Definitions
33 *
34 ****************************************************************/
35
36 #define FALSE 0
37 #define TRUE 1
38
39 #define TLAN_MIN_FRAME_SIZE 60
40 #define TLAN_MAX_FRAME_SIZE 1536
41
42 #define TLAN_NUM_RX_LISTS 4
43 #define TLAN_NUM_TX_LISTS 8
44
45 #define TLAN_IGNORE 0
46 #define TLAN_RECORD 1
47
48 #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printk(KERN_DEBUG "TLAN: " format, ##args );
49 #define TLAN_DEBUG_GNRL 0x0001
50 #define TLAN_DEBUG_TX 0x0002
51 #define TLAN_DEBUG_RX 0x0004
52 #define TLAN_DEBUG_LIST 0x0008
53 #define TLAN_DEBUG_PROBE 0x0010
54
55 #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */
56
57
58
59 /*****************************************************************
60 * Device Identification Definitions
61 *
62 ****************************************************************/
63
64 #define PCI_DEVICE_ID_NETELLIGENT_10 0xAE34
65 #define PCI_DEVICE_ID_NETELLIGENT_10_100 0xAE32
66 #define PCI_DEVICE_ID_NETFLEX_3P_INTEGRATED 0xAE35
67 #define PCI_DEVICE_ID_NETFLEX_3P 0xF130
68 #define PCI_DEVICE_ID_NETFLEX_3P_BNC 0xF150
69 #define PCI_DEVICE_ID_NETELLIGENT_10_100_PROLIANT 0xAE43
70 #define PCI_DEVICE_ID_NETELLIGENT_10_100_DUAL 0xAE40
71 #define PCI_DEVICE_ID_DESKPRO_4000_5233MMX 0xB011
72 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
73 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
74 #ifndef PCI_DEVICE_ID_OLICOM_OC2183
75 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
76 #endif
77 #ifndef PCI_DEVICE_ID_OLICOM_OC2325
78 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
79 #endif
80 #ifndef PCI_DEVICE_ID_OLICOM_OC2326
81 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
82 #endif
83
84 typedef struct tlan_adapter_entry {
85 u16 vendorId;
86 u16 deviceId;
87 char *deviceLabel;
88 u32 flags;
89 u16 addrOfs;
90 } TLanAdapterEntry;
91
92 #define TLAN_ADAPTER_NONE 0x00000000
93 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
94 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
95 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004
96 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
97
98 #define TLAN_SPEED_DEFAULT 0
99 #define TLAN_SPEED_10 10
100 #define TLAN_SPEED_100 100
101
102 #define TLAN_DUPLEX_DEFAULT 0
103 #define TLAN_DUPLEX_HALF 1
104 #define TLAN_DUPLEX_FULL 2
105
106
107
108 /*****************************************************************
109 * EISA Definitions
110 *
111 ****************************************************************/
112
113 #define EISA_ID 0xc80 /* EISA ID Registers */
114 #define EISA_ID0 0xc80 /* EISA ID Register 0 */
115 #define EISA_ID1 0xc81 /* EISA ID Register 1 */
116 #define EISA_ID2 0xc82 /* EISA ID Register 2 */
117 #define EISA_ID3 0xc83 /* EISA ID Register 3 */
118 #define EISA_CR 0xc84 /* EISA Control Register */
119 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
120 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
121 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
122 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
123 #define EISA_APROM 0xc90 /* Ethernet Address PROM */
124
125
126
127 /*****************************************************************
128 * Rx/Tx List Definitions
129 *
130 ****************************************************************/
131
132 #define TLAN_BUFFERS_PER_LIST 10
133 #define TLAN_LAST_BUFFER 0x80000000
134 #define TLAN_CSTAT_UNUSED 0x8000
135 #define TLAN_CSTAT_FRM_CMP 0x4000
136 #define TLAN_CSTAT_READY 0x3000
137 #define TLAN_CSTAT_EOC 0x0800
138 #define TLAN_CSTAT_RX_ERROR 0x0400
139 #define TLAN_CSTAT_PASS_CRC 0x0200
140 #define TLAN_CSTAT_DP_PR 0x0100
141
142
143 typedef struct tlan_buffer_ref_tag {
144 u32 count;
145 u32 address;
146 } TLanBufferRef;
147
148
149 typedef struct tlan_list_tag {
150 u32 forward;
151 u16 cStat;
152 u16 frameSize;
153 TLanBufferRef buffer[TLAN_BUFFERS_PER_LIST];
154 } TLanList;
155
156
157 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
158
159
160
161
162 /*****************************************************************
163 * PHY definitions
164 *
165 ****************************************************************/
166
167 #define TLAN_PHY_MAX_ADDR 0x1F
168 #define TLAN_PHY_NONE 0x20
169
170
171
172
173 /*****************************************************************
174 * TLAN Private Information Structure
175 *
176 ****************************************************************/
177
178 typedef struct tlan_private_tag {
179 struct net_device *nextDevice;
180 void *dmaStorage;
181 u8 *padBuffer;
182 TLanList *rxList;
183 u8 *rxBuffer;
184 u32 rxHead;
185 u32 rxTail;
186 u32 rxEocCount;
187 TLanList *txList;
188 u8 *txBuffer;
189 u32 txHead;
190 u32 txInProgress;
191 u32 txTail;
192 u32 txBusyCount;
193 u32 phyOnline;
194 u32 timerSetAt;
195 u32 timerType;
196 struct timer_list timer;
197 struct net_device_stats stats;
198 struct board *adapter;
199 u32 adapterRev;
200 u32 aui;
201 u32 debug;
202 u32 duplex;
203 u32 phy[2];
204 u32 phyNum;
205 u32 speed;
206 u8 tlanRev;
207 u8 tlanFullDuplex;
208 char devName[8];
209 spinlock_t lock;
210 u8 link;
211 u8 is_eisa;
212 } TLanPrivateInfo;
213
214
215
216
217 /*****************************************************************
218 * TLan Driver Timer Definitions
219 *
220 ****************************************************************/
221
222 #define TLAN_TIMER_LINK_BEAT 1
223 #define TLAN_TIMER_ACTIVITY 2
224 #define TLAN_TIMER_PHY_PDOWN 3
225 #define TLAN_TIMER_PHY_PUP 4
226 #define TLAN_TIMER_PHY_RESET 5
227 #define TLAN_TIMER_PHY_START_LINK 6
228 #define TLAN_TIMER_PHY_FINISH_AN 7
229 #define TLAN_TIMER_FINISH_RESET 8
230
231 #define TLAN_TIMER_ACT_DELAY (HZ/10)
232
233
234
235
236 /*****************************************************************
237 * TLan Driver Eeprom Definitions
238 *
239 ****************************************************************/
240
241 #define TLAN_EEPROM_ACK 0
242 #define TLAN_EEPROM_STOP 1
243
244
245
246
247 /*****************************************************************
248 * Host Register Offsets and Contents
249 *
250 ****************************************************************/
251
252 #define TLAN_HOST_CMD 0x00
253 #define TLAN_HC_GO 0x80000000
254 #define TLAN_HC_STOP 0x40000000
255 #define TLAN_HC_ACK 0x20000000
256 #define TLAN_HC_CS_MASK 0x1FE00000
257 #define TLAN_HC_EOC 0x00100000
258 #define TLAN_HC_RT 0x00080000
259 #define TLAN_HC_NES 0x00040000
260 #define TLAN_HC_AD_RST 0x00008000
261 #define TLAN_HC_LD_TMR 0x00004000
262 #define TLAN_HC_LD_THR 0x00002000
263 #define TLAN_HC_REQ_INT 0x00001000
264 #define TLAN_HC_INT_OFF 0x00000800
265 #define TLAN_HC_INT_ON 0x00000400
266 #define TLAN_HC_AC_MASK 0x000000FF
267 #define TLAN_CH_PARM 0x04
268 #define TLAN_DIO_ADR 0x08
269 #define TLAN_DA_ADR_INC 0x8000
270 #define TLAN_DA_RAM_ADR 0x4000
271 #define TLAN_HOST_INT 0x0A
272 #define TLAN_HI_IV_MASK 0x1FE0
273 #define TLAN_HI_IT_MASK 0x001C
274 #define TLAN_DIO_DATA 0x0C
275
276
277 /* ThunderLAN Internal Register DIO Offsets */
278
279 #define TLAN_NET_CMD 0x00
280 #define TLAN_NET_CMD_NRESET 0x80
281 #define TLAN_NET_CMD_NWRAP 0x40
282 #define TLAN_NET_CMD_CSF 0x20
283 #define TLAN_NET_CMD_CAF 0x10
284 #define TLAN_NET_CMD_NOBRX 0x08
285 #define TLAN_NET_CMD_DUPLEX 0x04
286 #define TLAN_NET_CMD_TRFRAM 0x02
287 #define TLAN_NET_CMD_TXPACE 0x01
288 #define TLAN_NET_SIO 0x01
289 #define TLAN_NET_SIO_MINTEN 0x80
290 #define TLAN_NET_SIO_ECLOK 0x40
291 #define TLAN_NET_SIO_ETXEN 0x20
292 #define TLAN_NET_SIO_EDATA 0x10
293 #define TLAN_NET_SIO_NMRST 0x08
294 #define TLAN_NET_SIO_MCLK 0x04
295 #define TLAN_NET_SIO_MTXEN 0x02
296 #define TLAN_NET_SIO_MDATA 0x01
297 #define TLAN_NET_STS 0x02
298 #define TLAN_NET_STS_MIRQ 0x80
299 #define TLAN_NET_STS_HBEAT 0x40
300 #define TLAN_NET_STS_TXSTOP 0x20
301 #define TLAN_NET_STS_RXSTOP 0x10
302 #define TLAN_NET_STS_RSRVD 0x0F
303 #define TLAN_NET_MASK 0x03
304 #define TLAN_NET_MASK_MASK7 0x80
305 #define TLAN_NET_MASK_MASK6 0x40
306 #define TLAN_NET_MASK_MASK5 0x20
307 #define TLAN_NET_MASK_MASK4 0x10
308 #define TLAN_NET_MASK_RSRVD 0x0F
309 #define TLAN_NET_CONFIG 0x04
310 #define TLAN_NET_CFG_RCLK 0x8000
311 #define TLAN_NET_CFG_TCLK 0x4000
312 #define TLAN_NET_CFG_BIT 0x2000
313 #define TLAN_NET_CFG_RXCRC 0x1000
314 #define TLAN_NET_CFG_PEF 0x0800
315 #define TLAN_NET_CFG_1FRAG 0x0400
316 #define TLAN_NET_CFG_1CHAN 0x0200
317 #define TLAN_NET_CFG_MTEST 0x0100
318 #define TLAN_NET_CFG_PHY_EN 0x0080
319 #define TLAN_NET_CFG_MSMASK 0x007F
320 #define TLAN_MAN_TEST 0x06
321 #define TLAN_DEF_VENDOR_ID 0x08
322 #define TLAN_DEF_DEVICE_ID 0x0A
323 #define TLAN_DEF_REVISION 0x0C
324 #define TLAN_DEF_SUBCLASS 0x0D
325 #define TLAN_DEF_MIN_LAT 0x0E
326 #define TLAN_DEF_MAX_LAT 0x0F
327 #define TLAN_AREG_0 0x10
328 #define TLAN_AREG_1 0x16
329 #define TLAN_AREG_2 0x1C
330 #define TLAN_AREG_3 0x22
331 #define TLAN_HASH_1 0x28
332 #define TLAN_HASH_2 0x2C
333 #define TLAN_GOOD_TX_FRMS 0x30
334 #define TLAN_TX_UNDERUNS 0x33
335 #define TLAN_GOOD_RX_FRMS 0x34
336 #define TLAN_RX_OVERRUNS 0x37
337 #define TLAN_DEFERRED_TX 0x38
338 #define TLAN_CRC_ERRORS 0x3A
339 #define TLAN_CODE_ERRORS 0x3B
340 #define TLAN_MULTICOL_FRMS 0x3C
341 #define TLAN_SINGLECOL_FRMS 0x3E
342 #define TLAN_EXCESSCOL_FRMS 0x40
343 #define TLAN_LATE_COLS 0x41
344 #define TLAN_CARRIER_LOSS 0x42
345 #define TLAN_ACOMMIT 0x43
346 #define TLAN_LED_REG 0x44
347 #define TLAN_LED_ACT 0x10
348 #define TLAN_LED_LINK 0x01
349 #define TLAN_BSIZE_REG 0x45
350 #define TLAN_MAX_RX 0x46
351 #define TLAN_INT_DIS 0x48
352 #define TLAN_ID_TX_EOC 0x04
353 #define TLAN_ID_RX_EOF 0x02
354 #define TLAN_ID_RX_EOC 0x01
355
356
357
358 /* ThunderLAN Interrupt Codes */
359
360 #define TLAN_INT_NUMBER_OF_INTS 8
361
362 #define TLAN_INT_NONE 0x0000
363 #define TLAN_INT_TX_EOF 0x0001
364 #define TLAN_INT_STAT_OVERFLOW 0x0002
365 #define TLAN_INT_RX_EOF 0x0003
366 #define TLAN_INT_DUMMY 0x0004
367 #define TLAN_INT_TX_EOC 0x0005
368 #define TLAN_INT_STATUS_CHECK 0x0006
369 #define TLAN_INT_RX_EOC 0x0007
370
371
372
373 /* ThunderLAN MII Registers */
374
375 /* Generic MII/PHY Registers */
376
377 #define MII_GEN_CTL 0x00
378 #define MII_GC_RESET 0x8000
379 #define MII_GC_LOOPBK 0x4000
380 #define MII_GC_SPEEDSEL 0x2000
381 #define MII_GC_AUTOENB 0x1000
382 #define MII_GC_PDOWN 0x0800
383 #define MII_GC_ISOLATE 0x0400
384 #define MII_GC_AUTORSRT 0x0200
385 #define MII_GC_DUPLEX 0x0100
386 #define MII_GC_COLTEST 0x0080
387 #define MII_GC_RESERVED 0x007F
388 #define MII_GEN_STS 0x01
389 #define MII_GS_100BT4 0x8000
390 #define MII_GS_100BTXFD 0x4000
391 #define MII_GS_100BTXHD 0x2000
392 #define MII_GS_10BTFD 0x1000
393 #define MII_GS_10BTHD 0x0800
394 #define MII_GS_RESERVED 0x07C0
395 #define MII_GS_AUTOCMPLT 0x0020
396 #define MII_GS_RFLT 0x0010
397 #define MII_GS_AUTONEG 0x0008
398 #define MII_GS_LINK 0x0004
399 #define MII_GS_JABBER 0x0002
400 #define MII_GS_EXTCAP 0x0001
401 #define MII_GEN_ID_HI 0x02
402 #define MII_GEN_ID_LO 0x03
403 #define MII_GIL_OUI 0xFC00
404 #define MII_GIL_MODEL 0x03F0
405 #define MII_GIL_REVISION 0x000F
406 #define MII_AN_ADV 0x04
407 #define MII_AN_LPA 0x05
408 #define MII_AN_EXP 0x06
409
410 /* ThunderLAN Specific MII/PHY Registers */
411
412 #define TLAN_TLPHY_ID 0x10
413 #define TLAN_TLPHY_CTL 0x11
414 #define TLAN_TC_IGLINK 0x8000
415 #define TLAN_TC_SWAPOL 0x4000
416 #define TLAN_TC_AUISEL 0x2000
417 #define TLAN_TC_SQEEN 0x1000
418 #define TLAN_TC_MTEST 0x0800
419 #define TLAN_TC_RESERVED 0x07F8
420 #define TLAN_TC_NFEW 0x0004
421 #define TLAN_TC_INTEN 0x0002
422 #define TLAN_TC_TINT 0x0001
423 #define TLAN_TLPHY_STS 0x12
424 #define TLAN_TS_MINT 0x8000
425 #define TLAN_TS_PHOK 0x4000
426 #define TLAN_TS_POLOK 0x2000
427 #define TLAN_TS_TPENERGY 0x1000
428 #define TLAN_TS_RESERVED 0x0FFF
429 #define TLAN_TLPHY_PAR 0x19
430 #define TLAN_PHY_CIM_STAT 0x0020
431 #define TLAN_PHY_SPEED_100 0x0040
432 #define TLAN_PHY_DUPLEX_FULL 0x0080
433 #define TLAN_PHY_AN_EN_STAT 0x0400
434
435 /* National Sem. & Level1 PHY id's */
436 #define NAT_SEM_ID1 0x2000
437 #define NAT_SEM_ID2 0x5C01
438 #define LEVEL1_ID1 0x7810
439 #define LEVEL1_ID2 0x0000
440
441 #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0
442
443 /* Routines to access internal registers. */
444
445 inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr)
446 {
447 outw(internal_addr, base_addr + TLAN_DIO_ADR);
448 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
449
450 } /* TLan_DioRead8 */
451
452
453
454
455 inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr)
456 {
457 outw(internal_addr, base_addr + TLAN_DIO_ADR);
458 return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)));
459
460 } /* TLan_DioRead16 */
461
462
463
464
465 inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr)
466 {
467 outw(internal_addr, base_addr + TLAN_DIO_ADR);
468 return (inl(base_addr + TLAN_DIO_DATA));
469
470 } /* TLan_DioRead32 */
471
472
473
474
475 inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data)
476 {
477 outw(internal_addr, base_addr + TLAN_DIO_ADR);
478 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3));
479
480 }
481
482
483
484
485 inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data)
486 {
487 outw(internal_addr, base_addr + TLAN_DIO_ADR);
488 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
489
490 }
491
492
493
494
495 inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data)
496 {
497 outw(internal_addr, base_addr + TLAN_DIO_ADR);
498 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
499
500 }
501
502
503
504 #if 0
505 inline void TLan_ClearBit(u8 bit, u16 port)
506 {
507 outb_p(inb_p(port) & ~bit, port);
508 }
509
510
511
512
513 inline int TLan_GetBit(u8 bit, u16 port)
514 {
515 return ((int) (inb_p(port) & bit));
516 }
517
518
519
520
521 inline void TLan_SetBit(u8 bit, u16 port)
522 {
523 outb_p(inb_p(port) | bit, port);
524 }
525 #endif
526
527 #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port)
528 #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit))
529 #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port)
530
531 #ifdef I_LIKE_A_FAST_HASH_FUNCTION
532 /* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */
533 /* the code below is about seven times as fast as the original code */
534 inline u32 TLan_HashFunc( u8 *a )
535 {
536 u8 hash;
537
538 hash = (a[0]^a[3]); /* & 077 */
539 hash ^= ((a[0]^a[3])>>6); /* & 003 */
540 hash ^= ((a[1]^a[4])<<2); /* & 074 */
541 hash ^= ((a[1]^a[4])>>4); /* & 017 */
542 hash ^= ((a[2]^a[5])<<4); /* & 060 */
543 hash ^= ((a[2]^a[5])>>2); /* & 077 */
544
545 return (hash & 077);
546 }
547
548 #else /* original code */
549
550 inline u32 xor( u32 a, u32 b )
551 {
552 return ( ( a && ! b ) || ( ! a && b ) );
553 }
554 #define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) )
555 #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) )
556
557 inline u32 TLan_HashFunc( u8 *a )
558 {
559 u32 hash;
560
561 hash = XOR8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), DA(a,36), DA(a,42) );
562 hash |= XOR8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), DA(a,37), DA(a,43) ) << 1;
563 hash |= XOR8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), DA(a,38), DA(a,44) ) << 2;
564 hash |= XOR8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), DA(a,39), DA(a,45) ) << 3;
565 hash |= XOR8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), DA(a,40), DA(a,46) ) << 4;
566 hash |= XOR8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), DA(a,41), DA(a,47) ) << 5;
567
568 return hash;
569
570 }
571
572 #endif /* I_LIKE_A_FAST_HASH_FUNCTION */
573 #endif
574
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