1 /* winbond-840.c: A Linux PCI network adapter skeleton device driver. */
2 /*
3 Written 1998-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright infomation.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35
36 TODO:
37 * according to the documentation, the chip supports big endian
38 descriptors. Remove cpu_to_le32, enable BE descriptors.
39 */
40
41 /* These identify the driver base version and may not be removed. */
42 static const char version1[] =
43 "winbond-840.c:v1.01 (2.4 port) 5/15/2000 Donald Becker <becker@scyld.com>\n";
44 static const char version2[] =
45 " http://www.scyld.com/network/drivers.html\n";
46
47 /* Automatically extracted configuration info:
48 probe-func: winbond840_probe
49 config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
50
51 c-help-name: Winbond W89c840 PCI Ethernet support
52 c-help-symbol: CONFIG_WINBOND_840
53 c-help: This driver is for the Winbond W89c840 chip. It also works with
54 c-help: the TX9882 chip on the Compex RL100-ATX board.
55 c-help: More specific information and updates are available from
56 c-help: http://www.scyld.com/network/drivers.html
57 */
58
59 /* The user-configurable values.
60 These may be modified when a driver module is loaded.*/
61
62 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
63 static int max_interrupt_work = 20;
64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The '840 uses a 64 element hash table based on the Ethernet CRC. */
66 static int multicast_filter_limit = 32;
67
68 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
69 Setting to > 1518 effectively disables this feature. */
70 static int rx_copybreak = 0;
71
72 /* Used to pass the media type, etc.
73 Both 'options[]' and 'full_duplex[]' should exist for driver
74 interoperability.
75 The media type is usually passed in 'options[]'.
76 */
77 #define MAX_UNITS 8 /* More are supported, limit only on options */
78 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
79 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
80
81 /* Operational parameters that are set at compile time. */
82
83 /* Keep the ring sizes a power of two for compile efficiency.
84 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
85 Making the Tx ring too large decreases the effectiveness of channel
86 bonding and packet priority.
87 There are no ill effects from too-large receive rings. */
88 #define TX_RING_SIZE 16
89 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
90 #define RX_RING_SIZE 32
91
92 /* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
93 To avoid overflowing we don't queue again until we have room for a
94 full-size packet.
95 */
96 #define TX_FIFO_SIZE (2048)
97 #define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
98
99 #define TX_BUFLIMIT (1024-128)
100
101 /* Operational parameters that usually are not changed. */
102 /* Time in jiffies before concluding the transmitter is hung. */
103 #define TX_TIMEOUT (2*HZ)
104
105 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
106
107 #ifndef __KERNEL__
108 #define __KERNEL__
109 #endif
110 #if !defined(__OPTIMIZE__)
111 #warning You must compile this file with the correct options!
112 #warning See the last lines of the source file.
113 #error You must compile this driver with "-O".
114 #endif
115
116 /* Include files, designed to support most kernel versions 2.0.0 and later. */
117 #include <linux/module.h>
118 #include <linux/kernel.h>
119 #include <linux/string.h>
120 #include <linux/timer.h>
121 #include <linux/errno.h>
122 #include <linux/ioport.h>
123 #include <linux/malloc.h>
124 #include <linux/interrupt.h>
125 #include <linux/pci.h>
126 #include <linux/netdevice.h>
127 #include <linux/etherdevice.h>
128 #include <linux/skbuff.h>
129 #include <linux/init.h>
130 #include <asm/processor.h> /* Processor type for cache alignment. */
131 #include <asm/bitops.h>
132 #include <asm/io.h>
133 #include <asm/delay.h>
134
135 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
136 MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
137 MODULE_PARM(max_interrupt_work, "i");
138 MODULE_PARM(debug, "i");
139 MODULE_PARM(rx_copybreak, "i");
140 MODULE_PARM(multicast_filter_limit, "i");
141 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
142 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
143
144 /*
145 Theory of Operation
146
147 I. Board Compatibility
148
149 This driver is for the Winbond w89c840 chip.
150
151 II. Board-specific settings
152
153 None.
154
155 III. Driver operation
156
157 This chip is very similar to the Digital 21*4* "Tulip" family. The first
158 twelve registers and the descriptor format are nearly identical. Read a
159 Tulip manual for operational details.
160
161 A significant difference is that the multicast filter and station address are
162 stored in registers rather than loaded through a pseudo-transmit packet.
163
164 Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
165 full-sized packet we must use both data buffers in a descriptor. Thus the
166 driver uses ring mode where descriptors are implicitly sequential in memory,
167 rather than using the second descriptor address as a chain pointer to
168 subsequent descriptors.
169
170 IV. Notes
171
172 If you are going to almost clone a Tulip, why not go all the way and avoid
173 the need for a new driver?
174
175 IVb. References
176
177 http://www.scyld.com/expert/100mbps.html
178 http://www.scyld.com/expert/NWay.html
179 http://www.winbond.com.tw/
180
181 IVc. Errata
182
183 A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
184 correctly detect a full FIFO, and queuing more than 2048 bytes may result in
185 silent data corruption.
186
187 */
188
189
190
191 /*
192 PCI probe table.
193 */
194 enum pci_id_flags_bits {
195 /* Set PCI command register bits before calling probe1(). */
196 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
197 /* Read and map the single following PCI BAR. */
198 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
199 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
200 };
201 enum chip_capability_flags {CanHaveMII=1, HasBrokenTx=2};
202 #ifdef USE_IO_OPS
203 #define W840_FLAGS (PCI_USES_IO | PCI_ADDR0 | PCI_USES_MASTER)
204 #else
205 #define W840_FLAGS (PCI_USES_MEM | PCI_ADDR1 | PCI_USES_MASTER)
206 #endif
207
208 static struct pci_device_id w840_pci_tbl[] __devinitdata = {
209 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
210 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
211 { 0, }
212 };
213 MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
214
215 struct pci_id_info {
216 const char *name;
217 struct match_info {
218 int pci, pci_mask, subsystem, subsystem_mask;
219 int revision, revision_mask; /* Only 8 bits. */
220 } id;
221 enum pci_id_flags_bits pci_flags;
222 int io_size; /* Needed for I/O region check or ioremap(). */
223 int drv_flags; /* Driver use, intended as capability flags. */
224 };
225 static struct pci_id_info pci_id_tbl[] = {
226 {"Winbond W89c840", { 0x08401050, 0xffffffff, },
227 W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
228 {"Compex RL100-ATX", { 0x201111F6, 0xffffffff,},
229 W840_FLAGS, 128, CanHaveMII | HasBrokenTx},
230 {0,}, /* 0 terminated list. */
231 };
232
233 /* This driver was written to use PCI memory space, however some x86 systems
234 work only with I/O space accesses. Pass -DUSE_IO_OPS to use PCI I/O space
235 accesses instead of memory space. */
236
237 #ifdef USE_IO_OPS
238 #undef readb
239 #undef readw
240 #undef readl
241 #undef writeb
242 #undef writew
243 #undef writel
244 #define readb inb
245 #define readw inw
246 #define readl inl
247 #define writeb outb
248 #define writew outw
249 #define writel outl
250 #endif
251
252 /* Offsets to the Command and Status Registers, "CSRs".
253 While similar to the Tulip, these registers are longword aligned.
254 Note: It's not useful to define symbolic names for every register bit in
255 the device. The name can only partially document the semantics and make
256 the driver longer and more difficult to read.
257 */
258 enum w840_offsets {
259 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
260 RxRingPtr=0x0C, TxRingPtr=0x10,
261 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
262 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
263 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
264 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
265 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
266 };
267
268 /* Bits in the interrupt status/enable registers. */
269 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
270 enum intr_status_bits {
271 NormalIntr=0x10000, AbnormalIntr=0x8000,
272 IntrPCIErr=0x2000, TimerInt=0x800,
273 IntrRxDied=0x100, RxNoBuf=0x80, IntrRxDone=0x40,
274 TxFIFOUnderflow=0x20, RxErrIntr=0x10,
275 TxIdle=0x04, IntrTxStopped=0x02, IntrTxDone=0x01,
276 };
277
278 /* Bits in the NetworkConfig register. */
279 enum rx_mode_bits {
280 AcceptErr=0x80, AcceptRunt=0x40,
281 AcceptBroadcast=0x20, AcceptMulticast=0x10,
282 AcceptAllPhys=0x08, AcceptMyPhys=0x02,
283 };
284
285 enum mii_reg_bits {
286 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
287 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
288 };
289
290 /* The Tulip Rx and Tx buffer descriptors. */
291 struct w840_rx_desc {
292 s32 status;
293 s32 length;
294 u32 buffer1;
295 u32 buffer2;
296 };
297
298 struct w840_tx_desc {
299 s32 status;
300 s32 length;
301 u32 buffer1, buffer2; /* We use only buffer 1. */
302 };
303
304 /* Bits in network_desc.status */
305 enum desc_status_bits {
306 DescOwn=0x80000000, DescEndRing=0x02000000, DescUseLink=0x01000000,
307 DescWholePkt=0x60000000, DescStartPkt=0x20000000, DescEndPkt=0x40000000,
308 };
309
310 /* Bits in w840_tx_desc.length */
311 enum desc_length_bits {
312 DescIntr=0x80000000,
313 };
314
315 #define PRIV_ALIGN 15 /* Required alignment mask */
316 struct netdev_private {
317 struct w840_rx_desc *rx_ring;
318 dma_addr_t rx_addr[RX_RING_SIZE];
319 struct w840_tx_desc *tx_ring;
320 dma_addr_t tx_addr[RX_RING_SIZE];
321 dma_addr_t ring_dma_addr;
322 struct pci_dev *pdev;
323 /* The addresses of receive-in-place skbuffs. */
324 struct sk_buff* rx_skbuff[RX_RING_SIZE];
325 /* The saved address of a sent-in-place packet/buffer, for later free(). */
326 struct sk_buff* tx_skbuff[TX_RING_SIZE];
327 struct net_device_stats stats;
328 struct timer_list timer; /* Media monitoring timer. */
329 /* Frequently used values: keep some adjacent for cache effect. */
330 spinlock_t lock;
331 int chip_id, drv_flags;
332 int csr6;
333 struct w840_rx_desc *rx_head_desc;
334 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
335 unsigned int rx_buf_sz; /* Based on MTU+slack. */
336 unsigned int cur_tx, dirty_tx;
337 int tx_q_bytes;
338 unsigned int tx_full:1; /* The Tx queue is full. */
339 /* These values are keep track of the transceiver/media in use. */
340 unsigned int full_duplex:1; /* Full-duplex operation requested. */
341 unsigned int duplex_lock:1;
342 unsigned int medialock:1; /* Do not sense media. */
343 unsigned int default_port:4; /* Last dev->if_port value. */
344 /* MII transceiver section. */
345 int mii_cnt; /* MII device addresses. */
346 u16 advertising; /* NWay media advertisement */
347 unsigned char phys[2]; /* MII device addresses. */
348 };
349
350 static int eeprom_read(long ioaddr, int location);
351 static int mdio_read(struct net_device *dev, int phy_id, int location);
352 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
353 static int netdev_open(struct net_device *dev);
354 static void check_duplex(struct net_device *dev);
355 static void netdev_timer(unsigned long data);
356 static void init_rxtx_rings(struct net_device *dev);
357 static void free_rxtx_rings(struct netdev_private *np);
358 static void init_registers(struct net_device *dev);
359 static void tx_timeout(struct net_device *dev);
360 static int alloc_ring(struct net_device *dev);
361 static int start_tx(struct sk_buff *skb, struct net_device *dev);
362 static void intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
363 static void netdev_error(struct net_device *dev, int intr_status);
364 static int netdev_rx(struct net_device *dev);
365 static inline unsigned ether_crc(int length, unsigned char *data);
366 static void set_rx_mode(struct net_device *dev);
367 static struct net_device_stats *get_stats(struct net_device *dev);
368 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
369 static int netdev_close(struct net_device *dev);
370
371
372
373 static int __devinit w840_probe1 (struct pci_dev *pdev,
374 const struct pci_device_id *ent)
375 {
376 struct net_device *dev;
377 struct netdev_private *np;
378 static int find_cnt;
379 int chip_idx = ent->driver_data;
380 int irq = pdev->irq;
381 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
382 long ioaddr;
383
384 if (pci_enable_device(pdev))
385 return -EIO;
386 pci_set_master(pdev);
387
388 if(!pci_dma_supported(pdev,0xFFFFffff)) {
389 printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n",
390 pdev->name);
391 return -EIO;
392 }
393 dev = init_etherdev(NULL, sizeof(*np));
394 if (!dev)
395 return -ENOMEM;
396 SET_MODULE_OWNER(dev);
397
398 #ifdef USE_IO_OPS
399 ioaddr = pci_resource_start(pdev, 0);
400 if (!request_region(ioaddr, pci_id_tbl[chip_idx].io_size, dev->name))
401 goto err_out_netdev;
402 #else
403 ioaddr = pci_resource_start(pdev, 1);
404 if (!request_mem_region(ioaddr, pci_id_tbl[chip_idx].io_size, dev->name))
405 goto err_out_netdev;
406 ioaddr = (long) ioremap (ioaddr, pci_id_tbl[chip_idx].io_size);
407 if (!ioaddr)
408 goto err_out_iomem;
409 #endif
410
411 printk(KERN_INFO "%s: %s at 0x%lx, ",
412 dev->name, pci_id_tbl[chip_idx].name, ioaddr);
413
414 /* Warning: broken for big-endian machines. */
415 for (i = 0; i < 3; i++)
416 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(eeprom_read(ioaddr, i));
417
418 for (i = 0; i < 5; i++)
419 printk("%2.2x:", dev->dev_addr[i]);
420 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
421
422 /* Reset the chip to erase previous misconfiguration.
423 No hold time required! */
424 writel(0x00000001, ioaddr + PCIBusCfg);
425
426 dev->base_addr = ioaddr;
427 dev->irq = irq;
428
429 np = dev->priv;
430 np->chip_id = chip_idx;
431 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
432 np->pdev = pdev;
433 spin_lock_init(&np->lock);
434
435 pdev->driver_data = dev;
436
437 if (dev->mem_start)
438 option = dev->mem_start;
439
440 /* The lower four bits are the media type. */
441 if (option > 0) {
442 if (option & 0x200)
443 np->full_duplex = 1;
444 np->default_port = option & 15;
445 if (np->default_port)
446 np->medialock = 1;
447 }
448 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
449 np->full_duplex = 1;
450
451 if (np->full_duplex)
452 np->duplex_lock = 1;
453
454 /* The chip-specific entries in the device structure. */
455 dev->open = &netdev_open;
456 dev->hard_start_xmit = &start_tx;
457 dev->stop = &netdev_close;
458 dev->get_stats = &get_stats;
459 dev->set_multicast_list = &set_rx_mode;
460 dev->do_ioctl = &mii_ioctl;
461 dev->tx_timeout = &tx_timeout;
462 dev->watchdog_timeo = TX_TIMEOUT;
463
464 if (np->drv_flags & CanHaveMII) {
465 int phy, phy_idx = 0;
466 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
467 int mii_status = mdio_read(dev, phy, 1);
468 if (mii_status != 0xffff && mii_status != 0x0000) {
469 np->phys[phy_idx++] = phy;
470 np->advertising = mdio_read(dev, phy, 4);
471 printk(KERN_INFO "%s: MII PHY found at address %d, status "
472 "0x%4.4x advertising %4.4x.\n",
473 dev->name, phy, mii_status, np->advertising);
474 }
475 }
476 np->mii_cnt = phy_idx;
477 if (phy_idx == 0) {
478 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
479 "not operate correctly.\n", dev->name);
480 }
481 }
482
483 find_cnt++;
484 return 0;
485
486 #ifndef USE_IO_OPS
487 err_out_iomem:
488 release_mem_region(pci_resource_start(pdev, 1),
489 pci_id_tbl[chip_idx].io_size);
490 #endif
491 err_out_netdev:
492 unregister_netdev (dev);
493 kfree (dev);
494 return -ENODEV;
495 }
496
497
498 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
499 often serial bit streams generated by the host processor.
500 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
501
502 /* Delay between EEPROM clock transitions.
503 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
504 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
505 made udelay() unreliable.
506 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
507 depricated.
508 */
509 #define eeprom_delay(ee_addr) readl(ee_addr)
510
511 enum EEPROM_Ctrl_Bits {
512 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
513 EE_ChipSelect=0x801, EE_DataIn=0x08,
514 };
515
516 /* The EEPROM commands include the alway-set leading bit. */
517 enum EEPROM_Cmds {
518 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
519 };
520
521 static int eeprom_read(long addr, int location)
522 {
523 int i;
524 int retval = 0;
525 int ee_addr = addr + EECtrl;
526 int read_cmd = location | EE_ReadCmd;
527 writel(EE_ChipSelect, ee_addr);
528
529 /* Shift the read command bits out. */
530 for (i = 10; i >= 0; i--) {
531 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
532 writel(dataval, ee_addr);
533 eeprom_delay(ee_addr);
534 writel(dataval | EE_ShiftClk, ee_addr);
535 eeprom_delay(ee_addr);
536 }
537 writel(EE_ChipSelect, ee_addr);
538
539 for (i = 16; i > 0; i--) {
540 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
541 eeprom_delay(ee_addr);
542 retval = (retval << 1) | ((readl(ee_addr) & EE_DataIn) ? 1 : 0);
543 writel(EE_ChipSelect, ee_addr);
544 eeprom_delay(ee_addr);
545 }
546
547 /* Terminate the EEPROM access. */
548 writel(0, ee_addr);
549 return retval;
550 }
551
552 /* MII transceiver control section.
553 Read and write the MII registers using software-generated serial
554 MDIO protocol. See the MII specifications or DP83840A data sheet
555 for details.
556
557 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
558 met by back-to-back 33Mhz PCI cycles. */
559 #define mdio_delay(mdio_addr) readl(mdio_addr)
560
561 /* Set iff a MII transceiver on any interface requires mdio preamble.
562 This only set with older tranceivers, so the extra
563 code size of a per-interface flag is not worthwhile. */
564 static char mii_preamble_required = 1;
565
566 #define MDIO_WRITE0 (MDIO_EnbOutput)
567 #define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
568
569 /* Generate the preamble required for initial synchronization and
570 a few older transceivers. */
571 static void mdio_sync(long mdio_addr)
572 {
573 int bits = 32;
574
575 /* Establish sync by sending at least 32 logic ones. */
576 while (--bits >= 0) {
577 writel(MDIO_WRITE1, mdio_addr);
578 mdio_delay(mdio_addr);
579 writel(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
580 mdio_delay(mdio_addr);
581 }
582 }
583
584 static int mdio_read(struct net_device *dev, int phy_id, int location)
585 {
586 long mdio_addr = dev->base_addr + MIICtrl;
587 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
588 int i, retval = 0;
589
590 if (mii_preamble_required)
591 mdio_sync(mdio_addr);
592
593 /* Shift the read command bits out. */
594 for (i = 15; i >= 0; i--) {
595 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
596
597 writel(dataval, mdio_addr);
598 mdio_delay(mdio_addr);
599 writel(dataval | MDIO_ShiftClk, mdio_addr);
600 mdio_delay(mdio_addr);
601 }
602 /* Read the two transition, 16 data, and wire-idle bits. */
603 for (i = 20; i > 0; i--) {
604 writel(MDIO_EnbIn, mdio_addr);
605 mdio_delay(mdio_addr);
606 retval = (retval << 1) | ((readl(mdio_addr) & MDIO_DataIn) ? 1 : 0);
607 writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
608 mdio_delay(mdio_addr);
609 }
610 return (retval>>1) & 0xffff;
611 }
612
613 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
614 {
615 struct netdev_private *np = (struct netdev_private *)dev->priv;
616 long mdio_addr = dev->base_addr + MIICtrl;
617 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
618 int i;
619
620 if (location == 4 && phy_id == np->phys[0])
621 np->advertising = value;
622
623 if (mii_preamble_required)
624 mdio_sync(mdio_addr);
625
626 /* Shift the command bits out. */
627 for (i = 31; i >= 0; i--) {
628 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
629
630 writel(dataval, mdio_addr);
631 mdio_delay(mdio_addr);
632 writel(dataval | MDIO_ShiftClk, mdio_addr);
633 mdio_delay(mdio_addr);
634 }
635 /* Clear out extra bits. */
636 for (i = 2; i > 0; i--) {
637 writel(MDIO_EnbIn, mdio_addr);
638 mdio_delay(mdio_addr);
639 writel(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
640 mdio_delay(mdio_addr);
641 }
642 return;
643 }
644
645
646 static int netdev_open(struct net_device *dev)
647 {
648 struct netdev_private *np = (struct netdev_private *)dev->priv;
649 long ioaddr = dev->base_addr;
650 int i;
651
652 writel(0x00000001, ioaddr + PCIBusCfg); /* Reset */
653
654 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
655 if (i)
656 return i;
657
658 if (debug > 1)
659 printk(KERN_DEBUG "%s: w89c840_open() irq %d.\n",
660 dev->name, dev->irq);
661
662 if((i=alloc_ring(dev)))
663 return i;
664
665 init_registers(dev);
666
667 netif_start_queue(dev);
668 if (debug > 2)
669 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
670
671 /* Set the timer to check for link beat. */
672 init_timer(&np->timer);
673 np->timer.expires = jiffies + 3*HZ;
674 np->timer.data = (unsigned long)dev;
675 np->timer.function = &netdev_timer; /* timer handler */
676 add_timer(&np->timer);
677
678 return 0;
679 }
680
681 static void check_duplex(struct net_device *dev)
682 {
683 struct netdev_private *np = (struct netdev_private *)dev->priv;
684 int mii_reg5 = mdio_read(dev, np->phys[0], 5);
685 int negotiated = mii_reg5 & np->advertising;
686 int duplex;
687
688 if (np->duplex_lock || mii_reg5 == 0xffff)
689 return;
690 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
691 if (np->full_duplex != duplex) {
692 np->full_duplex = duplex;
693 if (debug)
694 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
695 "negotiated capability %4.4x.\n", dev->name,
696 duplex ? "full" : "half", np->phys[0], negotiated);
697 np->csr6 &= ~0x200;
698 np->csr6 |= duplex ? 0x200 : 0;
699 }
700 }
701
702 static void netdev_timer(unsigned long data)
703 {
704 struct net_device *dev = (struct net_device *)data;
705 struct netdev_private *np = (struct netdev_private *)dev->priv;
706 long ioaddr = dev->base_addr;
707 int next_tick = 10*HZ;
708 int old_csr6 = np->csr6;
709
710 if (debug > 2)
711 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
712 "config %8.8x.\n",
713 dev->name, (int)readl(ioaddr + IntrStatus),
714 (int)readl(ioaddr + NetworkConfig));
715 spin_lock_irq(&np->lock);
716 check_duplex(dev);
717 if (np->csr6 != old_csr6) {
718 writel(np->csr6 & ~0x0002, ioaddr + NetworkConfig);
719 writel(np->csr6 | 0x2002, ioaddr + NetworkConfig);
720 }
721 spin_unlock_irq(&np->lock);
722 np->timer.expires = jiffies + next_tick;
723 add_timer(&np->timer);
724 }
725
726 static void init_rxtx_rings(struct net_device *dev)
727 {
728 struct netdev_private *np = (struct netdev_private *)dev->priv;
729 int i;
730
731 np->rx_head_desc = &np->rx_ring[0];
732 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
733
734 /* Initial all Rx descriptors. */
735 for (i = 0; i < RX_RING_SIZE; i++) {
736 np->rx_ring[i].length = cpu_to_le32(np->rx_buf_sz);
737 np->rx_ring[i].status = 0;
738 np->rx_skbuff[i] = 0;
739 }
740 /* Mark the last entry as wrapping the ring. */
741 np->rx_ring[i-1].length |= cpu_to_le32(DescEndRing);
742
743 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
744 for (i = 0; i < RX_RING_SIZE; i++) {
745 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
746 np->rx_skbuff[i] = skb;
747 if (skb == NULL)
748 break;
749 skb->dev = dev; /* Mark as being used by this device. */
750 np->rx_addr[i] = pci_map_single(np->pdev,skb->tail,
751 skb->len,PCI_DMA_FROMDEVICE);
752
753 np->rx_ring[i].buffer1 = cpu_to_le32(np->rx_addr[i]);
754 np->rx_ring[i].status = cpu_to_le32(DescOwn);
755 }
756
757 np->cur_rx = 0;
758 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
759
760 /* Initialize the Tx descriptors */
761 for (i = 0; i < TX_RING_SIZE; i++) {
762 np->tx_skbuff[i] = 0;
763 np->tx_ring[i].status = 0;
764 }
765 np->tx_full = 0;
766 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
767
768 writel(np->ring_dma_addr, dev->base_addr + RxRingPtr);
769 writel(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
770 dev->base_addr + TxRingPtr);
771
772 }
773
774 static void free_rxtx_rings(struct netdev_private* np)
775 {
776 int i;
777 /* Free all the skbuffs in the Rx queue. */
778 for (i = 0; i < RX_RING_SIZE; i++) {
779 np->rx_ring[i].status = 0;
780 if (np->rx_skbuff[i]) {
781 pci_unmap_single(np->pdev,
782 np->rx_addr[i],
783 np->rx_skbuff[i]->len,
784 PCI_DMA_FROMDEVICE);
785 dev_kfree_skb(np->rx_skbuff[i]);
786 }
787 np->rx_skbuff[i] = 0;
788 }
789 for (i = 0; i < TX_RING_SIZE; i++) {
790 if (np->tx_skbuff[i]) {
791 pci_unmap_single(np->pdev,
792 np->tx_addr[i],
793 np->tx_skbuff[i]->len,
794 PCI_DMA_TODEVICE);
795 dev_kfree_skb(np->tx_skbuff[i]);
796 }
797 np->tx_skbuff[i] = 0;
798 }
799 }
800
801 static void init_registers(struct net_device *dev)
802 {
803 struct netdev_private *np = (struct netdev_private *)dev->priv;
804 long ioaddr = dev->base_addr;
805 int i;
806
807 for (i = 0; i < 6; i++)
808 writeb(dev->dev_addr[i], ioaddr + StationAddr + i);
809
810 /* Initialize other registers. */
811 /* Configure the PCI bus bursts and FIFO thresholds.
812 486: Set 8 longword cache alignment, 8 longword burst.
813 586: Set 16 longword cache alignment, no burst limit.
814 Cache alignment bits 15:14 Burst length 13:8
815 0000 <not allowed> 0000 align to cache 0800 8 longwords
816 4000 8 longwords 0100 1 longword 1000 16 longwords
817 8000 16 longwords 0200 2 longwords 2000 32 longwords
818 C000 32 longwords 0400 4 longwords
819 Wait the specified 50 PCI cycles after a reset by initializing
820 Tx and Rx queues and the address filter list. */
821 #if defined(__powerpc__) /* Big-endian */
822 writel(0x00100080 | 0xE010, ioaddr + PCIBusCfg);
823 #elif defined(__alpha__)
824 writel(0xE010, ioaddr + PCIBusCfg);
825 #elif defined(__i386__)
826 #if defined(MODULE)
827 writel(0xE010, ioaddr + PCIBusCfg);
828 #else
829 /* When not a module we can work around broken '486 PCI boards. */
830 #define x86 boot_cpu_data.x86
831 writel((x86 <= 4 ? 0x4810 : 0xE010), ioaddr + PCIBusCfg);
832 if (x86 <= 4)
833 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache "
834 "alignment to %x.\n", dev->name,
835 (x86 <= 4 ? 0x4810 : 0x8010));
836 #endif
837 #else
838 writel(0xE010, ioaddr + PCIBusCfg);
839 #warning Processor architecture undefined!
840 #endif
841
842 if (dev->if_port == 0)
843 dev->if_port = np->default_port;
844
845 /* Fast Ethernet; 128 byte Tx threshold;
846 Transmit on; Receive on; */
847 np->csr6 = 0x20022002;
848 check_duplex(dev);
849 set_rx_mode(dev);
850 writel(0, ioaddr + RxStartDemand);
851
852 /* Clear and Enable interrupts by setting the interrupt mask. */
853 writel(0x1A0F5, ioaddr + IntrStatus);
854 writel(0x1A0F5, ioaddr + IntrEnable);
855
856 }
857
858 static void tx_timeout(struct net_device *dev)
859 {
860 struct netdev_private *np = (struct netdev_private *)dev->priv;
861 long ioaddr = dev->base_addr;
862
863 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
864 " resetting...\n", dev->name, (int)readl(ioaddr + IntrStatus));
865
866 #ifndef __alpha__
867 {
868 int i;
869 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)np->rx_ring);
870 for (i = 0; i < RX_RING_SIZE; i++)
871 printk(" %8.8x", (unsigned int)np->rx_ring[i].status);
872 printk("\n"KERN_DEBUG" Tx ring %8.8x: ", (int)np->tx_ring);
873 for (i = 0; i < TX_RING_SIZE; i++)
874 printk(" %8.8x", np->tx_ring[i].status);
875 printk("\n");
876 }
877 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d.\n",
878 np->cur_tx, np->dirty_tx, np->tx_full,np->tx_q_bytes);
879 printk(KERN_DEBUG "Tx Descriptor addr %xh.\n",readl(ioaddr+0x4C));
880
881 #endif
882 spin_lock_irq(&np->lock);
883 /*
884 * Under high load dirty_tx and the internal tx descriptor pointer
885 * come out of sync, thus perform a software reset and reinitialize
886 * everything.
887 */
888
889 writel(1, dev->base_addr+PCIBusCfg);
890 udelay(1);
891
892 free_rxtx_rings(np);
893 init_rxtx_rings(dev);
894 init_registers(dev);
895 set_rx_mode(dev);
896
897 spin_unlock_irq(&np->lock);
898
899 netif_wake_queue(dev);
900 dev->trans_start = jiffies;
901 np->stats.tx_errors++;
902 return;
903 }
904
905 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
906 static int alloc_ring(struct net_device *dev)
907 {
908 struct netdev_private *np = (struct netdev_private *)dev->priv;
909
910 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
911
912 np->rx_ring = pci_alloc_consistent(np->pdev,
913 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
914 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
915 &np->ring_dma_addr);
916 if(!np->rx_ring)
917 return -ENOMEM;
918 init_rxtx_rings(dev);
919 return 0;
920 }
921
922
923 static int start_tx(struct sk_buff *skb, struct net_device *dev)
924 {
925 struct netdev_private *np = (struct netdev_private *)dev->priv;
926 unsigned entry;
927 int len1, len2;
928
929 /* Caution: the write order is important here, set the field
930 with the "ownership" bits last. */
931
932 /* Calculate the next Tx descriptor entry. */
933 entry = np->cur_tx % TX_RING_SIZE;
934
935 np->tx_skbuff[entry] = skb;
936 np->tx_addr[entry] = pci_map_single(np->pdev,
937 skb->data,skb->len, PCI_DMA_TODEVICE);
938 np->tx_ring[entry].buffer1 = cpu_to_le32(np->tx_addr[entry]);
939 len2 = 0;
940 len1 = skb->len;
941 if(len1 > TX_BUFLIMIT) {
942 len1 = TX_BUFLIMIT;
943 len2 = skb->len-len1;
944 np->tx_ring[entry].buffer2 = cpu_to_le32(np->tx_addr[entry]+TX_BUFLIMIT);
945 }
946 np->tx_ring[entry].length = cpu_to_le32(DescWholePkt | (len2 << 11) | len1);
947 if (entry >= TX_RING_SIZE-1) /* Wrap ring */
948 np->tx_ring[entry].length |= cpu_to_le32(DescIntr | DescEndRing);
949 np->cur_tx++;
950
951 /* The spinlock protects against 2 races:
952 * - tx_q_bytes is updated by this function and intr_handler
953 * - our hardware is extremely fast and finishes the packet between
954 * our check for "queue full" and netif_stop_queue.
955 * Thus setting DescOwn and netif_stop_queue must be atomic.
956 */
957 spin_lock_irq(&np->lock);
958
959 wmb(); /* flush length, buffer1, buffer2 */
960 np->tx_ring[entry].status = cpu_to_le32(DescOwn);
961 wmb(); /* flush status and kick the hardware */
962 writel(0, dev->base_addr + TxStartDemand);
963
964 np->tx_q_bytes += skb->len;
965 /* Work around horrible bug in the chip by marking the queue as full
966 when we do not have FIFO room for a maximum sized packet. */
967 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN)
968 np->tx_full = 1;
969 else if ((np->drv_flags & HasBrokenTx)
970 && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)
971 np->tx_full = 1;
972 if (np->tx_full)
973 netif_stop_queue(dev);
974
975 dev->trans_start = jiffies;
976 spin_unlock_irq(&np->lock);
977
978 if (debug > 4) {
979 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
980 dev->name, np->cur_tx, entry);
981 }
982 return 0;
983 }
984
985 /* The interrupt handler does all of the Rx thread work and cleans up
986 after the Tx thread. */
987 static void intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
988 {
989 struct net_device *dev = (struct net_device *)dev_instance;
990 struct netdev_private *np = (struct netdev_private *)dev->priv;
991 long ioaddr = dev->base_addr;
992 int work_limit = max_interrupt_work;
993
994 spin_lock(&np->lock);
995
996 do {
997 u32 intr_status = readl(ioaddr + IntrStatus);
998
999 /* Acknowledge all of the current interrupt sources ASAP. */
1000 writel(intr_status & 0x001ffff, ioaddr + IntrStatus);
1001
1002 if (debug > 4)
1003 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1004 dev->name, intr_status);
1005
1006 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1007 break;
1008
1009 if (intr_status & (IntrRxDone | RxNoBuf))
1010 netdev_rx(dev);
1011
1012 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1013 int entry = np->dirty_tx % TX_RING_SIZE;
1014 int tx_status = le32_to_cpu(np->tx_ring[entry].status);
1015
1016 if (tx_status < 0)
1017 break;
1018 if (tx_status & 0x8000) { /* There was an error, log it. */
1019 #ifndef final_version
1020 if (debug > 1)
1021 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1022 dev->name, tx_status);
1023 #endif
1024 np->stats.tx_errors++;
1025 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1026 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1027 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1028 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1029 if ((tx_status & 0x0080) && np->full_duplex == 0)
1030 np->stats.tx_heartbeat_errors++;
1031 #ifdef ETHER_STATS
1032 if (tx_status & 0x0100) np->stats.collisions16++;
1033 #endif
1034 } else {
1035 #ifdef ETHER_STATS
1036 if (tx_status & 0x0001) np->stats.tx_deferred++;
1037 #endif
1038 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1039 np->stats.collisions += (tx_status >> 3) & 15;
1040 np->stats.tx_packets++;
1041 }
1042 /* Free the original skb. */
1043 pci_unmap_single(np->pdev,np->tx_addr[entry],
1044 np->tx_skbuff[entry]->len,
1045 PCI_DMA_TODEVICE);
1046 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1047 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1048 np->tx_skbuff[entry] = 0;
1049 }
1050 if (np->tx_full &&
1051 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4
1052 && np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1053 /* The ring is no longer full, clear tbusy. */
1054 np->tx_full = 0;
1055 netif_wake_queue(dev);
1056 }
1057
1058 /* Abnormal error summary/uncommon events handlers. */
1059 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | IntrPCIErr |
1060 TimerInt | IntrTxStopped))
1061 netdev_error(dev, intr_status);
1062
1063 if (--work_limit < 0) {
1064 printk(KERN_WARNING "%s: Too much work at interrupt, "
1065 "status=0x%4.4x.\n", dev->name, intr_status);
1066 /* Set the timer to re-enable the other interrupts after
1067 10*82usec ticks. */
1068 writel(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1069 writel(10, ioaddr + GPTimer);
1070 break;
1071 }
1072 } while (1);
1073
1074 if (debug > 3)
1075 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1076 dev->name, (int)readl(ioaddr + IntrStatus));
1077
1078 spin_unlock(&np->lock);
1079 }
1080
1081 /* This routine is logically part of the interrupt handler, but separated
1082 for clarity and better register allocation. */
1083 static int netdev_rx(struct net_device *dev)
1084 {
1085 struct netdev_private *np = (struct netdev_private *)dev->priv;
1086 int entry = np->cur_rx % RX_RING_SIZE;
1087 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1088
1089 if (debug > 4) {
1090 printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n",
1091 entry, np->rx_ring[entry].status);
1092 }
1093
1094 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1095 while (--work_limit >= 0) {
1096 struct w840_rx_desc *desc = np->rx_head_desc;
1097 s32 status = le32_to_cpu(desc->status);
1098
1099 if (debug > 4)
1100 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1101 status);
1102 if (status < 0)
1103 break;
1104 if ((status & 0x38008300) != 0x0300) {
1105 if ((status & 0x38000300) != 0x0300) {
1106 /* Ingore earlier buffers. */
1107 if ((status & 0xffff) != 0x7fff) {
1108 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1109 "multiple buffers, entry %#x status %4.4x!\n",
1110 dev->name, np->cur_rx, status);
1111 np->stats.rx_length_errors++;
1112 }
1113 } else if (status & 0x8000) {
1114 /* There was a fatal error. */
1115 if (debug > 2)
1116 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1117 dev->name, status);
1118 np->stats.rx_errors++; /* end of a packet.*/
1119 if (status & 0x0890) np->stats.rx_length_errors++;
1120 if (status & 0x004C) np->stats.rx_frame_errors++;
1121 if (status & 0x0002) np->stats.rx_crc_errors++;
1122 }
1123 } else {
1124 struct sk_buff *skb;
1125 /* Omit the four octet CRC from the length. */
1126 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1127
1128 #ifndef final_version
1129 if (debug > 4)
1130 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1131 " status %x.\n", pkt_len, status);
1132 #endif
1133 /* Check if the packet is long enough to accept without copying
1134 to a minimally-sized skbuff. */
1135 if (pkt_len < rx_copybreak
1136 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1137 skb->dev = dev;
1138 skb_reserve(skb, 2); /* 16 byte align the IP header */
1139 pci_dma_sync_single(np->pdev,np->rx_addr[entry],
1140 np->rx_skbuff[entry]->len,
1141 PCI_DMA_FROMDEVICE);
1142 /* Call copy + cksum if available. */
1143 #if HAS_IP_COPYSUM
1144 eth_copy_and_sum(skb, np->rx_skbuff[entry]->tail, pkt_len, 0);
1145 skb_put(skb, pkt_len);
1146 #else
1147 memcpy(skb_put(skb, pkt_len), np->rx_skbuff[entry]->tail,
1148 pkt_len);
1149 #endif
1150 } else {
1151 pci_unmap_single(np->pdev,np->rx_addr[entry],
1152 np->rx_skbuff[entry]->len,
1153 PCI_DMA_FROMDEVICE);
1154 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1155 np->rx_skbuff[entry] = NULL;
1156 }
1157 #ifndef final_version /* Remove after testing. */
1158 /* You will want this info for the initial debug. */
1159 if (debug > 5)
1160 printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:"
1161 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x "
1162 "%d.%d.%d.%d.\n",
1163 skb->data[0], skb->data[1], skb->data[2], skb->data[3],
1164 skb->data[4], skb->data[5], skb->data[6], skb->data[7],
1165 skb->data[8], skb->data[9], skb->data[10],
1166 skb->data[11], skb->data[12], skb->data[13],
1167 skb->data[14], skb->data[15], skb->data[16],
1168 skb->data[17]);
1169 #endif
1170 skb->protocol = eth_type_trans(skb, dev);
1171 netif_rx(skb);
1172 dev->last_rx = jiffies;
1173 np->stats.rx_packets++;
1174 np->stats.rx_bytes += pkt_len;
1175 }
1176 entry = (++np->cur_rx) % RX_RING_SIZE;
1177 np->rx_head_desc = &np->rx_ring[entry];
1178 }
1179
1180 /* Refill the Rx ring buffers. */
1181 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1182 struct sk_buff *skb;
1183 entry = np->dirty_rx % RX_RING_SIZE;
1184 if (np->rx_skbuff[entry] == NULL) {
1185 skb = dev_alloc_skb(np->rx_buf_sz);
1186 np->rx_skbuff[entry] = skb;
1187 if (skb == NULL)
1188 break; /* Better luck next round. */
1189 skb->dev = dev; /* Mark as being used by this device. */
1190 np->rx_addr[entry] = pci_map_single(np->pdev,
1191 skb->tail,
1192 skb->len, PCI_DMA_FROMDEVICE);
1193 np->rx_ring[entry].buffer1 = cpu_to_le32(np->rx_addr[entry]);
1194 }
1195 wmb();
1196 np->rx_ring[entry].status = cpu_to_le32(DescOwn);
1197 }
1198
1199 return 0;
1200 }
1201
1202 static void netdev_error(struct net_device *dev, int intr_status)
1203 {
1204 long ioaddr = dev->base_addr;
1205 struct netdev_private *np = (struct netdev_private *)dev->priv;
1206
1207 if (debug > 2)
1208 printk(KERN_DEBUG "%s: Abnormal event, %8.8x.\n",
1209 dev->name, intr_status);
1210 if (intr_status == 0xffffffff)
1211 return;
1212 if (intr_status & TxFIFOUnderflow) {
1213 /* Bump up the Tx threshold */
1214 #if 0
1215 /* This causes lots of dropped packets,
1216 * and under high load even tx_timeouts
1217 */
1218 np->csr6 += 0x4000;
1219 #else
1220 int cur = (np->csr6 >> 14)&0x7f;
1221 if (cur < 64)
1222 cur *= 2;
1223 else
1224 cur = 0; /* load full packet before starting */
1225 np->csr6 &= ~(0x7F << 14);
1226 np->csr6 |= cur<<14;
1227 #endif
1228 printk(KERN_DEBUG "%s: Tx underflow, increasing threshold to %8.8x.\n",
1229 dev->name, np->csr6);
1230 writel(np->csr6, ioaddr + NetworkConfig);
1231 }
1232 if (intr_status & IntrRxDied) { /* Missed a Rx frame. */
1233 np->stats.rx_errors++;
1234 }
1235 if (intr_status & TimerInt) {
1236 /* Re-enable other interrupts. */
1237 writel(0x1A0F5, ioaddr + IntrEnable);
1238 }
1239 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1240 writel(0, ioaddr + RxStartDemand);
1241 }
1242
1243 static struct net_device_stats *get_stats(struct net_device *dev)
1244 {
1245 long ioaddr = dev->base_addr;
1246 struct netdev_private *np = (struct netdev_private *)dev->priv;
1247
1248 /* The chip only need report frame silently dropped. */
1249 if (netif_running(dev))
1250 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1251
1252 return &np->stats;
1253 }
1254
1255 static unsigned const ethernet_polynomial = 0x04c11db7U;
1256 static inline u32 ether_crc(int length, unsigned char *data)
1257 {
1258 int crc = -1;
1259
1260 while(--length >= 0) {
1261 unsigned char current_octet = *data++;
1262 int bit;
1263 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1264 crc = (crc << 1) ^
1265 ((crc < 0) ^ (current_octet & 1) ? ethernet_polynomial : 0);
1266 }
1267 }
1268 return crc;
1269 }
1270
1271 static void set_rx_mode(struct net_device *dev)
1272 {
1273 struct netdev_private *np = (struct netdev_private *)dev->priv;
1274 long ioaddr = dev->base_addr;
1275 u32 mc_filter[2]; /* Multicast hash filter */
1276 u32 rx_mode;
1277
1278 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1279 /* Unconditionally log net taps. */
1280 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1281 memset(mc_filter, 0xff, sizeof(mc_filter));
1282 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAllPhys
1283 | AcceptMyPhys;
1284 } else if ((dev->mc_count > multicast_filter_limit)
1285 || (dev->flags & IFF_ALLMULTI)) {
1286 /* Too many to match, or accept all multicasts. */
1287 memset(mc_filter, 0xff, sizeof(mc_filter));
1288 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1289 } else {
1290 struct dev_mc_list *mclist;
1291 int i;
1292 memset(mc_filter, 0, sizeof(mc_filter));
1293 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1294 i++, mclist = mclist->next) {
1295 set_bit((ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F,
1296 mc_filter);
1297 }
1298 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1299 }
1300 writel(mc_filter[0], ioaddr + MulticastFilter0);
1301 writel(mc_filter[1], ioaddr + MulticastFilter1);
1302 np->csr6 &= ~0x00F8;
1303 np->csr6 |= rx_mode;
1304 writel(np->csr6, ioaddr + NetworkConfig);
1305 }
1306
1307 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1308 {
1309 u16 *data = (u16 *)&rq->ifr_data;
1310
1311 switch(cmd) {
1312 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
1313 data[0] = ((struct netdev_private *)dev->priv)->phys[0] & 0x1f;
1314 /* Fall Through */
1315 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
1316 data[3] = mdio_read(dev, data[0] & 0x1f, data[1] & 0x1f);
1317 return 0;
1318 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
1319 if (!capable(CAP_NET_ADMIN))
1320 return -EPERM;
1321 mdio_write(dev, data[0] & 0x1f, data[1] & 0x1f, data[2]);
1322 return 0;
1323 default:
1324 return -EOPNOTSUPP;
1325 }
1326 }
1327
1328 static int netdev_close(struct net_device *dev)
1329 {
1330 long ioaddr = dev->base_addr;
1331 struct netdev_private *np = (struct netdev_private *)dev->priv;
1332 int i;
1333
1334 netif_stop_queue(dev);
1335
1336 if (debug > 1) {
1337 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %8.8x "
1338 "Config %8.8x.\n", dev->name, (int)readl(ioaddr + IntrStatus),
1339 (int)readl(ioaddr + NetworkConfig));
1340 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1341 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1342 }
1343
1344 /* Disable interrupts by clearing the interrupt mask. */
1345 writel(0x0000, ioaddr + IntrEnable);
1346
1347 /* Stop the chip's Tx and Rx processes. */
1348 writel(np->csr6 &= ~0x20FA, ioaddr + NetworkConfig);
1349
1350 if (readl(ioaddr + NetworkConfig) != 0xffffffff)
1351 np->stats.rx_missed_errors += readl(ioaddr + RxMissed) & 0xffff;
1352
1353 #ifdef __i386__
1354 if (debug > 2) {
1355 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1356 (int)np->tx_ring);
1357 for (i = 0; i < TX_RING_SIZE; i++)
1358 printk(" #%d desc. %4.4x %4.4x %8.8x.\n",
1359 i, np->tx_ring[i].length,
1360 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1361 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1362 (int)np->rx_ring);
1363 for (i = 0; i < RX_RING_SIZE; i++) {
1364 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1365 i, np->rx_ring[i].length,
1366 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1367 }
1368 }
1369 #endif /* __i386__ debugging only */
1370
1371 free_irq(dev->irq, dev);
1372
1373 del_timer_sync(&np->timer);
1374
1375 free_rxtx_rings(np);
1376
1377 return 0;
1378 }
1379
1380 static void __devexit w840_remove1 (struct pci_dev *pdev)
1381 {
1382 struct net_device *dev = pdev->driver_data;
1383
1384 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1385 if (dev) {
1386 struct netdev_private *np = (void *)(dev->priv);
1387 unregister_netdev(dev);
1388 #ifdef USE_IO_OPS
1389 release_region(dev->base_addr, pci_id_tbl[np->chip_id].io_size);
1390 #else
1391 release_mem_region(pci_resource_start(pdev, 1),
1392 pci_id_tbl[np->chip_id].io_size);
1393 iounmap((char *)(dev->base_addr));
1394 #endif
1395 kfree(dev);
1396 }
1397
1398 pdev->driver_data = NULL;
1399 }
1400
1401 static struct pci_driver w840_driver = {
1402 name: "winbond-840",
1403 id_table: w840_pci_tbl,
1404 probe: w840_probe1,
1405 remove: w840_remove1,
1406 };
1407
1408 static int __init w840_init(void)
1409 {
1410 return pci_module_init(&w840_driver);
1411 }
1412
1413 static void __exit w840_exit(void)
1414 {
1415 pci_unregister_driver(&w840_driver);
1416 }
1417
1418 module_init(w840_init);
1419 module_exit(w840_exit);
1420
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