1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@suse.cz>
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/malloc.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
22 #include <linux/pm.h>
23 #include <linux/slab.h>
24 #include <linux/kmod.h> /* for hotplug_path */
25
26 #include <asm/page.h>
27 #include <asm/dma.h> /* isa_dma_bridge_buggy */
28
29 #undef DEBUG
30
31 #ifdef DEBUG
32 #define DBG(x...) printk(x)
33 #else
34 #define DBG(x...)
35 #endif
36
37 LIST_HEAD(pci_root_buses);
38 LIST_HEAD(pci_devices);
39
40 /**
41 * pci_find_slot - locate PCI device from a given PCI slot
42 * @bus: number of PCI bus on which desired PCI device resides
43 * @devfn: number of PCI slot in which desired PCI device resides
44 *
45 * Given a PCI bus and slot number, the desired PCI device is
46 * located in system global list of PCI devices. If the device
47 * is found, a pointer to its data structure is returned. If no
48 * device is found, %NULL is returned.
49 */
50 struct pci_dev *
51 pci_find_slot(unsigned int bus, unsigned int devfn)
52 {
53 struct pci_dev *dev;
54
55 pci_for_each_dev(dev) {
56 if (dev->bus->number == bus && dev->devfn == devfn)
57 return dev;
58 }
59 return NULL;
60 }
61
62
63 struct pci_dev *
64 pci_find_subsys(unsigned int vendor, unsigned int device,
65 unsigned int ss_vendor, unsigned int ss_device,
66 const struct pci_dev *from)
67 {
68 struct list_head *n = from ? from->global_list.next : pci_devices.next;
69
70 while (n != &pci_devices) {
71 struct pci_dev *dev = pci_dev_g(n);
72 if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
73 (device == PCI_ANY_ID || dev->device == device) &&
74 (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
75 (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
76 return dev;
77 n = n->next;
78 }
79 return NULL;
80 }
81
82
83 /**
84 * pci_find_device - begin or continue searching for a PCI device by vendor/device id
85 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
86 * @device: PCI device id to match, or %PCI_ANY_ID to match all vendor ids
87 * @from: Previous PCI device found in search, or %NULL for new search.
88 *
89 * Iterates through the list of known PCI devices. If a PCI device is
90 * found with a matching @vendor and @device, a pointer to its device structure is
91 * returned. Otherwise, %NULL is returned.
92 *
93 * A new search is initiated by passing %NULL to the @from argument.
94 * Otherwise if @from is not null, searches continue from that point.
95 */
96 struct pci_dev *
97 pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
98 {
99 return pci_find_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
100 }
101
102
103 /**
104 * pci_find_class - begin or continue searching for a PCI device by class
105 * @class: search for a PCI device with this class designation
106 * @from: Previous PCI device found in search, or %NULL for new search.
107 *
108 * Iterates through the list of known PCI devices. If a PCI device is
109 * found with a matching @class, a pointer to its device structure is
110 * returned. Otherwise, %NULL is returned.
111 *
112 * A new search is initiated by passing %NULL to the @from argument.
113 * Otherwise if @from is not null, searches continue from that point.
114 */
115 struct pci_dev *
116 pci_find_class(unsigned int class, const struct pci_dev *from)
117 {
118 struct list_head *n = from ? from->global_list.next : pci_devices.next;
119
120 while (n != &pci_devices) {
121 struct pci_dev *dev = pci_dev_g(n);
122 if (dev->class == class)
123 return dev;
124 n = n->next;
125 }
126 return NULL;
127 }
128
129
130 int
131 pci_find_capability(struct pci_dev *dev, int cap)
132 {
133 u16 status;
134 u8 pos, id;
135 int ttl = 48;
136
137 pci_read_config_word(dev, PCI_STATUS, &status);
138 if (!(status & PCI_STATUS_CAP_LIST))
139 return 0;
140 switch (dev->hdr_type) {
141 case PCI_HEADER_TYPE_NORMAL:
142 case PCI_HEADER_TYPE_BRIDGE:
143 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
144 break;
145 case PCI_HEADER_TYPE_CARDBUS:
146 pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos);
147 break;
148 default:
149 return 0;
150 }
151 while (ttl-- && pos >= 0x40) {
152 pos &= ~3;
153 pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
154 if (id == 0xff)
155 break;
156 if (id == cap)
157 return pos;
158 pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
159 }
160 return 0;
161 }
162
163
164 /**
165 * pci_find_parent_resource - return resource region of parent bus of given region
166 * @dev: PCI device structure contains resources to be searched
167 * @res: child resource record for which parent is sought
168 *
169 * For given resource region of given device, return the resource
170 * region of parent bus the given region is contained in or where
171 * it should be allocated from.
172 */
173 struct resource *
174 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
175 {
176 const struct pci_bus *bus = dev->bus;
177 int i;
178 struct resource *best = NULL;
179
180 for(i=0; i<4; i++) {
181 struct resource *r = bus->resource[i];
182 if (!r)
183 continue;
184 if (res->start && !(res->start >= r->start && res->end <= r->end))
185 continue; /* Not contained */
186 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
187 continue; /* Wrong type */
188 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
189 return r; /* Exact match */
190 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
191 best = r; /* Approximating prefetchable by non-prefetchable */
192 }
193 return best;
194 }
195
196 /**
197 * pci_set_power_state - Set power management state of a device.
198 * @dev: PCI device for which PM is set
199 * @new_state: new power management statement (0 == D0, 3 == D3, etc.)
200 *
201 * Set power management state of a device. For transitions from state D3
202 * it isn't as straightforward as one could assume since many devices forget
203 * their configuration space during wakeup. Returns old power state.
204 */
205 int
206 pci_set_power_state(struct pci_dev *dev, int new_state)
207 {
208 u32 base[5], romaddr;
209 u16 pci_command, pwr_command;
210 u8 pci_latency, pci_cacheline;
211 int i, old_state;
212 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
213
214 if (!pm)
215 return 0;
216 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pwr_command);
217 old_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
218 if (old_state == new_state)
219 return old_state;
220 DBG("PCI: %s goes from D%d to D%d\n", dev->slot_name, old_state, new_state);
221 if (old_state == 3) {
222 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
223 pci_write_config_word(dev, PCI_COMMAND, pci_command & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
224 for (i = 0; i < 5; i++)
225 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + i*4, &base[i]);
226 pci_read_config_dword(dev, PCI_ROM_ADDRESS, &romaddr);
227 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &pci_latency);
228 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_cacheline);
229 pci_write_config_word(dev, pm + PCI_PM_CTRL, new_state);
230 for (i = 0; i < 5; i++)
231 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + i*4, base[i]);
232 pci_write_config_dword(dev, PCI_ROM_ADDRESS, romaddr);
233 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
234 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cacheline);
235 pci_write_config_byte(dev, PCI_LATENCY_TIMER, pci_latency);
236 pci_write_config_word(dev, PCI_COMMAND, pci_command);
237 } else
238 pci_write_config_word(dev, pm + PCI_PM_CTRL, (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | new_state);
239 return old_state;
240 }
241
242 /**
243 * pci_enable_device - Initialize device before it's used by a driver.
244 * @dev: PCI device to be initialized
245 *
246 * Initialize device before it's used by a driver. Ask low-level code
247 * to enable I/O and memory. Wake up the device if it was suspended.
248 * Beware, this function can fail.
249 */
250 int
251 pci_enable_device(struct pci_dev *dev)
252 {
253 int err;
254
255 if ((err = pcibios_enable_device(dev)) < 0)
256 return err;
257 pci_set_power_state(dev, 0);
258 return 0;
259 }
260
261 int
262 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
263 {
264 u8 pin;
265
266 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
267 if (!pin)
268 return -1;
269 pin--;
270 while (dev->bus->self) {
271 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
272 dev = dev->bus->self;
273 }
274 *bridge = dev;
275 return pin;
276 }
277
278 /*
279 * Registration of PCI drivers and handling of hot-pluggable devices.
280 */
281
282 static LIST_HEAD(pci_drivers);
283
284 const struct pci_device_id *
285 pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev)
286 {
287 while (ids->vendor || ids->subvendor || ids->class_mask) {
288 if ((ids->vendor == PCI_ANY_ID || ids->vendor == dev->vendor) &&
289 (ids->device == PCI_ANY_ID || ids->device == dev->device) &&
290 (ids->subvendor == PCI_ANY_ID || ids->subvendor == dev->subsystem_vendor) &&
291 (ids->subdevice == PCI_ANY_ID || ids->subdevice == dev->subsystem_device) &&
292 !((ids->class ^ dev->class) & ids->class_mask))
293 return ids;
294 ids++;
295 }
296 return NULL;
297 }
298
299 static int
300 pci_announce_device(struct pci_driver *drv, struct pci_dev *dev)
301 {
302 const struct pci_device_id *id;
303 int ret = 0;
304
305 if (drv->id_table) {
306 id = pci_match_device(drv->id_table, dev);
307 if (!id) {
308 ret = 0;
309 goto out;
310 }
311 } else
312 id = NULL;
313
314 dev_probe_lock();
315 if (drv->probe(dev, id) >= 0) {
316 dev->driver = drv;
317 ret = 1;
318 }
319 dev_probe_unlock();
320 out:
321 return ret;
322 }
323
324 int
325 pci_register_driver(struct pci_driver *drv)
326 {
327 struct pci_dev *dev;
328 int count = 0;
329
330 list_add_tail(&drv->node, &pci_drivers);
331 pci_for_each_dev(dev) {
332 if (!pci_dev_driver(dev))
333 count += pci_announce_device(drv, dev);
334 }
335 return count;
336 }
337
338 void
339 pci_unregister_driver(struct pci_driver *drv)
340 {
341 struct pci_dev *dev;
342
343 list_del(&drv->node);
344 pci_for_each_dev(dev) {
345 if (dev->driver == drv) {
346 if (drv->remove)
347 drv->remove(dev);
348 dev->driver = NULL;
349 }
350 }
351 }
352
353 #ifdef CONFIG_HOTPLUG
354
355 #ifndef FALSE
356 #define FALSE (0)
357 #define TRUE (!FALSE)
358 #endif
359
360 static void
361 run_sbin_hotplug(struct pci_dev *pdev, int insert)
362 {
363 int i;
364 char *argv[3], *envp[8];
365 char id[20], sub_id[24], bus_id[24], class_id[20];
366
367 if (!hotplug_path[0])
368 return;
369
370 sprintf(class_id, "PCI_CLASS=%04X", pdev->class);
371 sprintf(id, "PCI_ID=%04X:%04X", pdev->vendor, pdev->device);
372 sprintf(sub_id, "PCI_SUBSYS_ID=%04X:%04X", pdev->subsystem_vendor, pdev->subsystem_device);
373 sprintf(bus_id, "PCI_SLOT_NAME=%s", pdev->slot_name);
374
375 i = 0;
376 argv[i++] = hotplug_path;
377 argv[i++] = "pci";
378 argv[i] = 0;
379
380 i = 0;
381 /* minimal command environment */
382 envp[i++] = "HOME=/";
383 envp[i++] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin";
384
385 /* other stuff we want to pass to /sbin/hotplug */
386 envp[i++] = class_id;
387 envp[i++] = id;
388 envp[i++] = sub_id;
389 envp[i++] = bus_id;
390 if (insert)
391 envp[i++] = "ACTION=add";
392 else
393 envp[i++] = "ACTION=remove";
394 envp[i] = 0;
395
396 call_usermodehelper (argv [0], argv, envp);
397 }
398
399 void
400 pci_insert_device(struct pci_dev *dev, struct pci_bus *bus)
401 {
402 struct list_head *ln;
403
404 list_add_tail(&dev->bus_list, &bus->devices);
405 list_add_tail(&dev->global_list, &pci_devices);
406 #ifdef CONFIG_PROC_FS
407 pci_proc_attach_device(dev);
408 #endif
409 for(ln=pci_drivers.next; ln != &pci_drivers; ln=ln->next) {
410 struct pci_driver *drv = list_entry(ln, struct pci_driver, node);
411 if (drv->remove && pci_announce_device(drv, dev))
412 break;
413 }
414
415 /* notify userspace of new hotplug device */
416 run_sbin_hotplug(dev, TRUE);
417 }
418
419 static void
420 pci_free_resources(struct pci_dev *dev)
421 {
422 int i;
423
424 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
425 struct resource *res = dev->resource + i;
426 if (res->parent)
427 release_resource(res);
428 }
429 }
430
431 void
432 pci_remove_device(struct pci_dev *dev)
433 {
434 if (dev->driver) {
435 if (dev->driver->remove)
436 dev->driver->remove(dev);
437 dev->driver = NULL;
438 }
439 list_del(&dev->bus_list);
440 list_del(&dev->global_list);
441 pci_free_resources(dev);
442 #ifdef CONFIG_PROC_FS
443 pci_proc_detach_device(dev);
444 #endif
445
446 /* notify userspace of hotplug device removal */
447 run_sbin_hotplug(dev, FALSE);
448 }
449
450 #endif
451
452 static struct pci_driver pci_compat_driver = {
453 name: "compat"
454 };
455
456 struct pci_driver *
457 pci_dev_driver(const struct pci_dev *dev)
458 {
459 if (dev->driver)
460 return dev->driver;
461 else {
462 int i;
463 for(i=0; i<=PCI_ROM_RESOURCE; i++)
464 if (dev->resource[i].flags & IORESOURCE_BUSY)
465 return &pci_compat_driver;
466 }
467 return NULL;
468 }
469
470
471 /*
472 * This interrupt-safe spinlock protects all accesses to PCI
473 * configuration space.
474 */
475
476 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
477
478 /*
479 * Wrappers for all PCI configuration access functions. They just check
480 * alignment, do locking and call the low-level functions pointed to
481 * by pci_dev->ops.
482 */
483
484 #define PCI_byte_BAD 0
485 #define PCI_word_BAD (pos & 1)
486 #define PCI_dword_BAD (pos & 3)
487
488 #define PCI_OP(rw,size,type) \
489 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
490 { \
491 int res; \
492 unsigned long flags; \
493 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
494 spin_lock_irqsave(&pci_lock, flags); \
495 res = dev->bus->ops->rw##_##size(dev, pos, value); \
496 spin_unlock_irqrestore(&pci_lock, flags); \
497 return res; \
498 }
499
500 PCI_OP(read, byte, u8 *)
501 PCI_OP(read, word, u16 *)
502 PCI_OP(read, dword, u32 *)
503 PCI_OP(write, byte, u8)
504 PCI_OP(write, word, u16)
505 PCI_OP(write, dword, u32)
506
507
508 void
509 pci_set_master(struct pci_dev *dev)
510 {
511 u16 cmd;
512
513 pci_read_config_word(dev, PCI_COMMAND, &cmd);
514 if (! (cmd & PCI_COMMAND_MASTER)) {
515 DBG("PCI: Enabling bus mastering for device %s\n", dev->slot_name);
516 cmd |= PCI_COMMAND_MASTER;
517 pci_write_config_word(dev, PCI_COMMAND, cmd);
518 }
519 pcibios_set_master(dev);
520 }
521
522 /*
523 * Translate the low bits of the PCI base
524 * to the resource type
525 */
526 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
527 {
528 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
529 return IORESOURCE_IO;
530
531 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
532 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
533
534 return IORESOURCE_MEM;
535 }
536
537 /*
538 * Find the extent of a PCI decode..
539 */
540 static u32 pci_size(u32 base, unsigned long mask)
541 {
542 u32 size = mask & base; /* Find the significant bits */
543 size = size & ~(size-1); /* Get the lowest of them to find the decode size */
544 return size-1; /* extent = size - 1 */
545 }
546
547 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
548 {
549 unsigned int pos, reg, next;
550 u32 l, sz;
551 struct resource *res;
552
553 for(pos=0; pos<howmany; pos = next) {
554 next = pos+1;
555 res = &dev->resource[pos];
556 res->name = dev->name;
557 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
558 pci_read_config_dword(dev, reg, &l);
559 pci_write_config_dword(dev, reg, ~0);
560 pci_read_config_dword(dev, reg, &sz);
561 pci_write_config_dword(dev, reg, l);
562 if (!sz || sz == 0xffffffff)
563 continue;
564 if (l == 0xffffffff)
565 l = 0;
566 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
567 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
568 sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
569 } else {
570 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
571 sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
572 }
573 res->end = res->start + (unsigned long) sz;
574 res->flags |= (l & 0xf) | pci_calc_resource_flags(l);
575 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
576 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
577 pci_read_config_dword(dev, reg+4, &l);
578 next++;
579 #if BITS_PER_LONG == 64
580 res->start |= ((unsigned long) l) << 32;
581 res->end = res->start + sz;
582 pci_write_config_dword(dev, reg+4, ~0);
583 pci_read_config_dword(dev, reg+4, &sz);
584 pci_write_config_dword(dev, reg+4, l);
585 if (~sz)
586 res->end = res->start + 0xffffffff +
587 (((unsigned long) ~sz) << 32);
588 #else
589 if (l) {
590 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", dev->slot_name);
591 res->start = 0;
592 res->flags = 0;
593 continue;
594 }
595 #endif
596 }
597 }
598 if (rom) {
599 dev->rom_base_reg = rom;
600 res = &dev->resource[PCI_ROM_RESOURCE];
601 pci_read_config_dword(dev, rom, &l);
602 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
603 pci_read_config_dword(dev, rom, &sz);
604 pci_write_config_dword(dev, rom, l);
605 if (l == 0xffffffff)
606 l = 0;
607 if (sz && sz != 0xffffffff) {
608 res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
609 IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
610 res->start = l & PCI_ROM_ADDRESS_MASK;
611 sz = pci_size(sz, PCI_ROM_ADDRESS_MASK);
612 res->end = res->start + (unsigned long) sz;
613 }
614 res->name = dev->name;
615 }
616 }
617
618 void __init pci_read_bridge_bases(struct pci_bus *child)
619 {
620 struct pci_dev *dev = child->self;
621 u8 io_base_lo, io_limit_lo;
622 u16 mem_base_lo, mem_limit_lo, io_base_hi, io_limit_hi;
623 u32 mem_base_hi, mem_limit_hi;
624 unsigned long base, limit;
625 struct resource *res;
626 int i;
627
628 if (!dev) /* It's a host bus, nothing to read */
629 return;
630
631 for(i=0; i<3; i++)
632 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
633
634 res = child->resource[0];
635 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
636 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
637 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
638 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
639 base = ((io_base_lo & PCI_IO_RANGE_MASK) << 8) | (io_base_hi << 16);
640 limit = ((io_limit_lo & PCI_IO_RANGE_MASK) << 8) | (io_limit_hi << 16);
641 if (base && base <= limit) {
642 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
643 res->start = base;
644 res->end = limit + 0xfff;
645 res->name = child->name;
646 } else {
647 /*
648 * Ugh. We don't know enough about this bridge. Just assume
649 * that it's entirely transparent.
650 */
651 printk("Unknown bridge resource %d: assuming transparent\n", 0);
652 child->resource[0] = child->parent->resource[0];
653 }
654
655 res = child->resource[1];
656 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
657 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
658 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
659 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
660 if (base && base <= limit) {
661 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
662 res->start = base;
663 res->end = limit + 0xfffff;
664 res->name = child->name;
665 } else {
666 /* See comment above. Same thing */
667 printk("Unknown bridge resource %d: assuming transparent\n", 1);
668 child->resource[1] = child->parent->resource[1];
669 }
670
671 res = child->resource[2];
672 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
673 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
674 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
675 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
676 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
677 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
678 #if BITS_PER_LONG == 64
679 base |= ((long) mem_base_hi) << 32;
680 limit |= ((long) mem_limit_hi) << 32;
681 #else
682 if (mem_base_hi || mem_limit_hi) {
683 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
684 return;
685 }
686 #endif
687 if (base && base <= limit) {
688 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
689 res->start = base;
690 res->end = limit + 0xfffff;
691 res->name = child->name;
692 } else {
693 /* See comments above */
694 printk("Unknown bridge resource %d: assuming transparent\n", 2);
695 child->resource[2] = child->parent->resource[2];
696 }
697 }
698
699 static struct pci_bus * __init pci_alloc_bus(void)
700 {
701 struct pci_bus *b;
702
703 b = kmalloc(sizeof(*b), GFP_KERNEL);
704 if (b) {
705 memset(b, 0, sizeof(*b));
706 INIT_LIST_HEAD(&b->children);
707 INIT_LIST_HEAD(&b->devices);
708 }
709 return b;
710 }
711
712 static struct pci_bus * __init pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
713 {
714 struct pci_bus *child;
715 int i;
716
717 /*
718 * Allocate a new bus, and inherit stuff from the parent..
719 */
720 child = pci_alloc_bus();
721
722 list_add_tail(&child->node, &parent->children);
723 child->self = dev;
724 dev->subordinate = child;
725 child->parent = parent;
726 child->ops = parent->ops;
727 child->sysdata = parent->sysdata;
728
729 /*
730 * Set up the primary, secondary and subordinate
731 * bus numbers.
732 */
733 child->number = child->secondary = busnr;
734 child->primary = parent->secondary;
735 child->subordinate = 0xff;
736
737 /* Set up default resource pointers.. */
738 for (i = 0; i < 4; i++)
739 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
740
741 return child;
742 }
743
744 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus);
745
746 /*
747 * If it's a bridge, configure it and scan the bus behind it.
748 * For CardBus bridges, we don't scan behind as the devices will
749 * be handled by the bridge driver itself.
750 *
751 * We need to process bridges in two passes -- first we scan those
752 * already configured by the BIOS and after we are done with all of
753 * them, we proceed to assigning numbers to the remaining buses in
754 * order to avoid overlaps between old and new bus numbers.
755 */
756 static int __init pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
757 {
758 unsigned int buses;
759 unsigned short cr;
760 struct pci_bus *child;
761 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
762
763 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
764 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", dev->slot_name, buses & 0xffffff, pass);
765 if ((buses & 0xffff00) && !pcibios_assign_all_busses()) {
766 /*
767 * Bus already configured by firmware, process it in the first
768 * pass and just note the configuration.
769 */
770 if (pass)
771 return max;
772 child = pci_add_new_bus(bus, dev, 0);
773 child->primary = buses & 0xFF;
774 child->secondary = (buses >> 8) & 0xFF;
775 child->subordinate = (buses >> 16) & 0xFF;
776 child->number = child->secondary;
777 if (!is_cardbus) {
778 unsigned int cmax = pci_do_scan_bus(child);
779 if (cmax > max) max = cmax;
780 } else {
781 unsigned int cmax = child->subordinate;
782 if (cmax > max) max = cmax;
783 }
784 } else {
785 /*
786 * We need to assign a number to this bus which we always
787 * do in the second pass. We also keep all address decoders
788 * on the bridge disabled during scanning. FIXME: Why?
789 */
790 if (!pass)
791 return max;
792 pci_read_config_word(dev, PCI_COMMAND, &cr);
793 pci_write_config_word(dev, PCI_COMMAND, 0x0000);
794 pci_write_config_word(dev, PCI_STATUS, 0xffff);
795
796 child = pci_add_new_bus(bus, dev, ++max);
797 buses = (buses & 0xff000000)
798 | ((unsigned int)(child->primary) << 0)
799 | ((unsigned int)(child->secondary) << 8)
800 | ((unsigned int)(child->subordinate) << 16);
801 /*
802 * We need to blast all three values with a single write.
803 */
804 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
805 if (!is_cardbus) {
806 /* Now we can scan all subordinate buses... */
807 max = pci_do_scan_bus(child);
808 } else {
809 /*
810 * For CardBus bridges, we leave 4 bus numbers
811 * as cards with a PCI-to-PCI bridge can be
812 * inserted later.
813 */
814 max += 3;
815 }
816 /*
817 * Set the subordinate bus number to its real value.
818 */
819 child->subordinate = max;
820 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
821 pci_write_config_word(dev, PCI_COMMAND, cr);
822 }
823 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
824 return max;
825 }
826
827 /*
828 * Read interrupt line and base address registers.
829 * The architecture-dependent code can tweak these, of course.
830 */
831 static void pci_read_irq(struct pci_dev *dev)
832 {
833 unsigned char irq;
834
835 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
836 if (irq)
837 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
838 dev->irq = irq;
839 }
840
841 /*
842 * Fill in class and map information of a device
843 */
844 int pci_setup_device(struct pci_dev * dev)
845 {
846 u32 class;
847
848 sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
849 sprintf(dev->name, "PCI device %04x:%04x", dev->vendor, dev->device);
850
851 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
852 class >>= 8; /* upper 3 bytes */
853 dev->class = class;
854 class >>= 8;
855
856 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
857
858 switch (dev->hdr_type) { /* header type */
859 case PCI_HEADER_TYPE_NORMAL: /* standard header */
860 if (class == PCI_CLASS_BRIDGE_PCI)
861 goto bad;
862 pci_read_irq(dev);
863 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
864 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
865 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
866 break;
867
868 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
869 if (class != PCI_CLASS_BRIDGE_PCI)
870 goto bad;
871 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
872 break;
873
874 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
875 if (class != PCI_CLASS_BRIDGE_CARDBUS)
876 goto bad;
877 pci_read_irq(dev);
878 pci_read_bases(dev, 1, 0);
879 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
880 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
881 break;
882
883 default: /* unknown header */
884 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
885 dev->slot_name, dev->hdr_type);
886 return -1;
887
888 bad:
889 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
890 dev->slot_name, class, dev->hdr_type);
891 dev->class = PCI_CLASS_NOT_DEFINED;
892 }
893
894 /* We found a fine healthy device, go go go... */
895 return 0;
896 }
897
898 /*
899 * Read the config data for a PCI device, sanity-check it
900 * and fill in the dev structure...
901 */
902 static struct pci_dev * __init pci_scan_device(struct pci_dev *temp)
903 {
904 struct pci_dev *dev;
905 u32 l;
906
907 if (pci_read_config_dword(temp, PCI_VENDOR_ID, &l))
908 return NULL;
909
910 /* some broken boards return 0 or ~0 if a slot is empty: */
911 if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
912 return NULL;
913
914 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
915 if (!dev)
916 return NULL;
917
918 memcpy(dev, temp, sizeof(*dev));
919 dev->vendor = l & 0xffff;
920 dev->device = (l >> 16) & 0xffff;
921
922 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
923 set this higher, assuming the system even supports it. */
924 dev->dma_mask = 0xffffffff;
925 if (pci_setup_device(dev) < 0) {
926 kfree(dev);
927 dev = NULL;
928 }
929 return dev;
930 }
931
932 struct pci_dev * __init pci_scan_slot(struct pci_dev *temp)
933 {
934 struct pci_bus *bus = temp->bus;
935 struct pci_dev *dev;
936 struct pci_dev *first_dev = NULL;
937 int func = 0;
938 int is_multi = 0;
939 u8 hdr_type;
940
941 for (func = 0; func < 8; func++, temp->devfn++) {
942 if (func && !is_multi) /* not a multi-function device */
943 continue;
944 if (pci_read_config_byte(temp, PCI_HEADER_TYPE, &hdr_type))
945 continue;
946 temp->hdr_type = hdr_type & 0x7f;
947
948 dev = pci_scan_device(temp);
949 if (!dev)
950 continue;
951 pci_name_device(dev);
952 if (!func) {
953 is_multi = hdr_type & 0x80;
954 first_dev = dev;
955 }
956
957 /*
958 * Link the device to both the global PCI device chain and
959 * the per-bus list of devices.
960 */
961 list_add_tail(&dev->global_list, &pci_devices);
962 list_add_tail(&dev->bus_list, &bus->devices);
963
964 /* Fix up broken headers */
965 pci_fixup_device(PCI_FIXUP_HEADER, dev);
966 }
967 return first_dev;
968 }
969
970 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus)
971 {
972 unsigned int devfn, max, pass;
973 struct list_head *ln;
974 struct pci_dev *dev, dev0;
975
976 DBG("Scanning bus %02x\n", bus->number);
977 max = bus->secondary;
978
979 /* Create a device template */
980 memset(&dev0, 0, sizeof(dev0));
981 dev0.bus = bus;
982 dev0.sysdata = bus->sysdata;
983
984 /* Go find them, Rover! */
985 for (devfn = 0; devfn < 0x100; devfn += 8) {
986 dev0.devfn = devfn;
987 pci_scan_slot(&dev0);
988 }
989
990 /*
991 * After performing arch-dependent fixup of the bus, look behind
992 * all PCI-to-PCI bridges on this bus.
993 */
994 DBG("Fixups for bus %02x\n", bus->number);
995 pcibios_fixup_bus(bus);
996 for (pass=0; pass < 2; pass++)
997 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
998 dev = pci_dev_b(ln);
999 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1000 max = pci_scan_bridge(bus, dev, max, pass);
1001 }
1002
1003 /*
1004 * We've scanned the bus and so we know all about what's on
1005 * the other side of any bridges that may be on this bus plus
1006 * any devices.
1007 *
1008 * Return how far we've got finding sub-buses.
1009 */
1010 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
1011 return max;
1012 }
1013
1014 int __init pci_bus_exists(const struct list_head *list, int nr)
1015 {
1016 const struct list_head *l;
1017
1018 for(l=list->next; l != list; l = l->next) {
1019 const struct pci_bus *b = pci_bus_b(l);
1020 if (b->number == nr || pci_bus_exists(&b->children, nr))
1021 return 1;
1022 }
1023 return 0;
1024 }
1025
1026 struct pci_bus * __init pci_alloc_primary_bus(int bus)
1027 {
1028 struct pci_bus *b;
1029
1030 if (pci_bus_exists(&pci_root_buses, bus)) {
1031 /* If we already got to this bus through a different bridge, ignore it */
1032 DBG("PCI: Bus %02x already known\n", bus);
1033 return NULL;
1034 }
1035
1036 b = pci_alloc_bus();
1037 list_add_tail(&b->node, &pci_root_buses);
1038
1039 b->number = b->secondary = bus;
1040 b->resource[0] = &ioport_resource;
1041 b->resource[1] = &iomem_resource;
1042 return b;
1043 }
1044
1045 struct pci_bus * __init pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
1046 {
1047 struct pci_bus *b = pci_alloc_primary_bus(bus);
1048 if (b) {
1049 b->sysdata = sysdata;
1050 b->ops = ops;
1051 b->subordinate = pci_do_scan_bus(b);
1052 }
1053 return b;
1054 }
1055
1056 #ifdef CONFIG_PM
1057
1058 /*
1059 * PCI Power management..
1060 *
1061 * This needs to be done centralized, so that we power manage PCI
1062 * devices in the right order: we should not shut down PCI bridges
1063 * before we've shut down the devices behind them, and we should
1064 * not wake up devices before we've woken up the bridge to the
1065 * device.. Eh?
1066 *
1067 * We do not touch devices that don't have a driver that exports
1068 * a suspend/resume function. That is just too dangerous. If the default
1069 * PCI suspend/resume functions work for a device, the driver can
1070 * easily implement them (ie just have a suspend function that calls
1071 * the pci_set_power_state() function).
1072 */
1073 static int pci_pm_suspend_device(struct pci_dev *dev)
1074 {
1075 if (dev) {
1076 struct pci_driver *driver = dev->driver;
1077 if (driver && driver->suspend)
1078 driver->suspend(dev);
1079 }
1080 return 0;
1081 }
1082
1083 static int pci_pm_resume_device(struct pci_dev *dev)
1084 {
1085 if (dev) {
1086 struct pci_driver *driver = dev->driver;
1087 if (driver && driver->resume)
1088 driver->resume(dev);
1089 }
1090 return 0;
1091 }
1092
1093
1094 /* take care to suspend/resume bridges only once */
1095
1096 static int pci_pm_suspend_bus(struct pci_bus *bus)
1097 {
1098 struct list_head *list;
1099
1100 /* Walk the bus children list */
1101 list_for_each(list, &bus->children)
1102 pci_pm_suspend_bus(pci_bus_b(list));
1103
1104 /* Walk the device children list */
1105 list_for_each(list, &bus->devices)
1106 pci_pm_suspend_device(pci_dev_b(list));
1107 return 0;
1108 }
1109
1110 static int pci_pm_resume_bus(struct pci_bus *bus)
1111 {
1112 struct list_head *list;
1113
1114 /* Walk the device children list */
1115 list_for_each(list, &bus->devices)
1116 pci_pm_resume_device(pci_dev_b(list));
1117
1118 /* And then walk the bus children */
1119 list_for_each(list, &bus->children)
1120 pci_pm_resume_bus(pci_bus_b(list));
1121 return 0;
1122 }
1123
1124 static int pci_pm_suspend(void)
1125 {
1126 struct list_head *list;
1127 struct pci_bus *bus;
1128
1129 list_for_each(list, &pci_root_buses) {
1130 bus = pci_bus_b(list);
1131 pci_pm_suspend_bus(bus);
1132 pci_pm_suspend_device(bus->self);
1133 }
1134 return 0;
1135 }
1136
1137 static int pci_pm_resume(void)
1138 {
1139 struct list_head *list;
1140 struct pci_bus *bus;
1141
1142 list_for_each(list, &pci_root_buses) {
1143 bus = pci_bus_b(list);
1144 pci_pm_resume_device(bus->self);
1145 pci_pm_resume_bus(bus);
1146 }
1147 return 0;
1148 }
1149
1150 static int pci_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
1151 {
1152 switch (rqst) {
1153 case PM_SUSPEND:
1154 return pci_pm_suspend();
1155 case PM_RESUME:
1156 return pci_pm_resume();
1157 }
1158 return 0;
1159 }
1160 #endif
1161
1162 void __init pci_init(void)
1163 {
1164 struct pci_dev *dev;
1165
1166 pcibios_init();
1167
1168 pci_for_each_dev(dev) {
1169 pci_fixup_device(PCI_FIXUP_FINAL, dev);
1170 }
1171
1172 #ifdef CONFIG_PM
1173 pm_register(PM_PCI_DEV, 0, pci_pm_callback);
1174 #endif
1175 }
1176
1177 static int __init pci_setup(char *str)
1178 {
1179 while (str) {
1180 char *k = strchr(str, ',');
1181 if (k)
1182 *k++ = 0;
1183 if (*str && (str = pcibios_setup(str)) && *str) {
1184 /* PCI layer options should be handled here */
1185 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
1186 }
1187 str = k;
1188 }
1189 return 1;
1190 }
1191
1192 __setup("pci=", pci_setup);
1193
1194
1195 EXPORT_SYMBOL(pci_read_config_byte);
1196 EXPORT_SYMBOL(pci_read_config_word);
1197 EXPORT_SYMBOL(pci_read_config_dword);
1198 EXPORT_SYMBOL(pci_write_config_byte);
1199 EXPORT_SYMBOL(pci_write_config_word);
1200 EXPORT_SYMBOL(pci_write_config_dword);
1201 EXPORT_SYMBOL(pci_devices);
1202 EXPORT_SYMBOL(pci_root_buses);
1203 EXPORT_SYMBOL(pci_enable_device);
1204 EXPORT_SYMBOL(pci_find_capability);
1205 EXPORT_SYMBOL(pci_find_class);
1206 EXPORT_SYMBOL(pci_find_device);
1207 EXPORT_SYMBOL(pci_find_slot);
1208 EXPORT_SYMBOL(pci_find_subsys);
1209 EXPORT_SYMBOL(pci_set_master);
1210 EXPORT_SYMBOL(pci_set_power_state);
1211 EXPORT_SYMBOL(pci_assign_resource);
1212 EXPORT_SYMBOL(pci_register_driver);
1213 EXPORT_SYMBOL(pci_unregister_driver);
1214 EXPORT_SYMBOL(pci_dev_driver);
1215 EXPORT_SYMBOL(pci_match_device);
1216 EXPORT_SYMBOL(pci_find_parent_resource);
1217
1218 #ifdef CONFIG_HOTPLUG
1219 EXPORT_SYMBOL(pci_setup_device);
1220 EXPORT_SYMBOL(pci_insert_device);
1221 EXPORT_SYMBOL(pci_remove_device);
1222 #endif
1223
1224 /* Obsolete functions */
1225
1226 EXPORT_SYMBOL(pcibios_present);
1227 EXPORT_SYMBOL(pcibios_read_config_byte);
1228 EXPORT_SYMBOL(pcibios_read_config_word);
1229 EXPORT_SYMBOL(pcibios_read_config_dword);
1230 EXPORT_SYMBOL(pcibios_write_config_byte);
1231 EXPORT_SYMBOL(pcibios_write_config_word);
1232 EXPORT_SYMBOL(pcibios_write_config_dword);
1233 EXPORT_SYMBOL(pcibios_find_class);
1234 EXPORT_SYMBOL(pcibios_find_device);
1235
1236 /* Quirk info */
1237
1238 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1239 EXPORT_SYMBOL(pci_pci_problems);
1240
1241
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