1 /*
2 * ti113x.h 1.16 1999/10/25 20:03:34
3 *
4 * The contents of this file are subject to the Mozilla Public License
5 * Version 1.1 (the "License"); you may not use this file except in
6 * compliance with the License. You may obtain a copy of the License
7 * at http://www.mozilla.org/MPL/
8 *
9 * Software distributed under the License is distributed on an "AS IS"
10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11 * the License for the specific language governing rights and
12 * limitations under the License.
13 *
14 * The initial developer of the original code is David A. Hinds
15 * <dhinds@pcmcia.sourceforge.org>. Portions created by David A. Hinds
16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
17 *
18 * Alternatively, the contents of this file may be used under the
19 * terms of the GNU Public License version 2 (the "GPL"), in which
20 * case the provisions of the GPL are applicable instead of the
21 * above. If you wish to allow the use of your version of this file
22 * only under the terms of the GPL and not to allow others to use
23 * your version of this file under the MPL, indicate your decision by
24 * deleting the provisions above and replace them with the notice and
25 * other provisions required by the GPL. If you do not delete the
26 * provisions above, a recipient may use your version of this file
27 * under either the MPL or the GPL.
28 */
29
30 #ifndef _LINUX_TI113X_H
31 #define _LINUX_TI113X_H
32
33 #include <linux/config.h>
34
35 /* Register definitions for TI 113X PCI-to-CardBus bridges */
36
37 /* System Control Register */
38 #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
39 #define TI113X_SCR_SMIROUTE 0x04000000
40 #define TI113X_SCR_SMISTATUS 0x02000000
41 #define TI113X_SCR_SMIENB 0x01000000
42 #define TI113X_SCR_VCCPROT 0x00200000
43 #define TI113X_SCR_REDUCEZV 0x00100000
44 #define TI113X_SCR_CDREQEN 0x00080000
45 #define TI113X_SCR_CDMACHAN 0x00070000
46 #define TI113X_SCR_SOCACTIVE 0x00002000
47 #define TI113X_SCR_PWRSTREAM 0x00000800
48 #define TI113X_SCR_DELAYUP 0x00000400
49 #define TI113X_SCR_DELAYDOWN 0x00000200
50 #define TI113X_SCR_INTERROGATE 0x00000100
51 #define TI113X_SCR_CLKRUN_SEL 0x00000080
52 #define TI113X_SCR_PWRSAVINGS 0x00000040
53 #define TI113X_SCR_SUBSYSRW 0x00000020
54 #define TI113X_SCR_CB_DPAR 0x00000010
55 #define TI113X_SCR_CDMA_EN 0x00000008
56 #define TI113X_SCR_ASYNC_IRQ 0x00000004
57 #define TI113X_SCR_KEEPCLK 0x00000002
58 #define TI113X_SCR_CLKRUN_ENA 0x00000001
59
60 #define TI122X_SCR_SER_STEP 0xc0000000
61 #define TI122X_SCR_INTRTIE 0x20000000
62 #define TI122X_SCR_CBRSVD 0x00400000
63 #define TI122X_SCR_MRBURSTDN 0x00008000
64 #define TI122X_SCR_MRBURSTUP 0x00004000
65 #define TI122X_SCR_RIMUX 0x00000001
66
67 /* Multimedia Control Register */
68 #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
69 #define TI1250_MMC_ZVOUTEN 0x80
70 #define TI1250_MMC_PORTSEL 0x40
71 #define TI1250_MMC_ZVEN1 0x02
72 #define TI1250_MMC_ZVEN0 0x01
73
74 #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
75 #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
76 #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
77 #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
78 #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
79 #define TI122X_IRQMUX 0x008c /* 32 bit */
80
81 /* Retry Status Register */
82 #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
83 #define TI113X_RSR_PCIRETRY 0x80
84 #define TI113X_RSR_CBRETRY 0x40
85 #define TI113X_RSR_TEXP_CBB 0x20
86 #define TI113X_RSR_MEXP_CBB 0x10
87 #define TI113X_RSR_TEXP_CBA 0x08
88 #define TI113X_RSR_MEXP_CBA 0x04
89 #define TI113X_RSR_TEXP_PCI 0x02
90 #define TI113X_RSR_MEXP_PCI 0x01
91
92 /* Card Control Register */
93 #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
94 #define TI113X_CCR_RIENB 0x80
95 #define TI113X_CCR_ZVENABLE 0x40
96 #define TI113X_CCR_PCI_IRQ_ENA 0x20
97 #define TI113X_CCR_PCI_IREQ 0x10
98 #define TI113X_CCR_PCI_CSC 0x08
99 #define TI113X_CCR_SPKROUTEN 0x02
100 #define TI113X_CCR_IFG 0x01
101
102 #define TI1220_CCR_PORT_SEL 0x20
103 #define TI122X_CCR_AUD2MUX 0x04
104
105 /* Device Control Register */
106 #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
107 #define TI113X_DCR_5V_FORCE 0x40
108 #define TI113X_DCR_3V_FORCE 0x20
109 #define TI113X_DCR_IMODE_MASK 0x06
110 #define TI113X_DCR_IMODE_ISA 0x02
111 #define TI113X_DCR_IMODE_SERIAL 0x04
112
113 #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
114 #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
115
116 /* Buffer Control Register */
117 #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
118 #define TI113X_BCR_CB_READ_DEPTH 0x08
119 #define TI113X_BCR_CB_WRITE_DEPTH 0x04
120 #define TI113X_BCR_PCI_READ_DEPTH 0x02
121 #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
122
123 /* Diagnostic Register */
124 #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
125 #define TI1250_DIAG_TRUE_VALUE 0x80
126 #define TI1250_DIAG_PCI_IREQ 0x40
127 #define TI1250_DIAG_PCI_CSC 0x20
128 #define TI1250_DIAG_ASYNC_CSC 0x01
129
130 /* DMA Registers */
131 #define TI113X_DMA_0 0x0094 /* 32 bit */
132 #define TI113X_DMA_1 0x0098 /* 32 bit */
133
134 /* ExCA IO offset registers */
135 #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
136
137 #ifdef CONFIG_CARDBUS
138
139 /*
140 * Generic TI init - TI has an extension for the
141 * INTCTL register that sets the PCI CSC interrupt.
142 * Make sure we set it correctly at open and init
143 * time
144 * - open: disable the PCI CSC interrupt. This makes
145 * it possible to use the CSC interrupt to probe the
146 * ISA interrupts.
147 * - init: set the interrupt to match our PCI state.
148 * This makes us correctly get PCI CSC interrupt
149 * events.
150 */
151 static int ti_open(pci_socket_t *socket)
152 {
153 u8 new, reg = exca_readb(socket, I365_INTCTL);
154
155 new = reg & ~I365_INTR_ENA;
156 if (new != reg)
157 exca_writeb(socket, I365_INTCTL, new);
158 return 0;
159 }
160
161 static int ti_intctl(pci_socket_t *socket)
162 {
163 u8 new, reg = exca_readb(socket, I365_INTCTL);
164
165 new = reg & ~I365_INTR_ENA;
166 if (socket->cb_irq)
167 new |= I365_INTR_ENA;
168 if (new != reg)
169 exca_writeb(socket, I365_INTCTL, new);
170 return 0;
171 }
172
173 static int ti_init(pci_socket_t *socket)
174 {
175 yenta_init(socket);
176 ti_intctl(socket);
177 return 0;
178 }
179
180 static struct pci_socket_ops ti_ops = {
181 ti_open,
182 yenta_close,
183 ti_init,
184 yenta_suspend,
185 yenta_get_status,
186 yenta_get_socket,
187 yenta_set_socket,
188 yenta_get_io_map,
189 yenta_set_io_map,
190 yenta_get_mem_map,
191 yenta_set_mem_map,
192 yenta_proc_setup
193 };
194
195 #define ti_sysctl(socket) ((socket)->private[0])
196 #define ti_cardctl(socket) ((socket)->private[1])
197 #define ti_devctl(socket) ((socket)->private[2])
198
199 static int ti113x_open(pci_socket_t *socket)
200 {
201 ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
202 ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
203 ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
204
205 ti_cardctl(socket) &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
206 if (socket->cb_irq)
207 ti_cardctl(socket) |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
208 ti_open(socket);
209 return 0;
210 }
211
212 static int ti113x_init(pci_socket_t *socket)
213 {
214 yenta_init(socket);
215
216 config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
217 config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
218 config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
219 ti_intctl(socket);
220 return 0;
221 }
222
223 static struct pci_socket_ops ti113x_ops = {
224 ti113x_open,
225 yenta_close,
226 ti113x_init,
227 yenta_suspend,
228 yenta_get_status,
229 yenta_get_socket,
230 yenta_set_socket,
231 yenta_get_io_map,
232 yenta_set_io_map,
233 yenta_get_mem_map,
234 yenta_set_mem_map,
235 yenta_proc_setup
236 };
237
238 #define ti_diag(socket) ((socket)->private[0])
239
240 static int ti1250_open(pci_socket_t *socket)
241 {
242 ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
243
244 ti_diag(socket) &= ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
245 if (socket->cb_irq)
246 ti_diag(socket) |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
247 ti_open(socket);
248 return 0;
249 }
250
251 static int ti1250_init(pci_socket_t *socket)
252 {
253 yenta_init(socket);
254
255 config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
256 ti_intctl(socket);
257 return 0;
258 }
259
260 static struct pci_socket_ops ti1250_ops = {
261 ti1250_open,
262 yenta_close,
263 ti1250_init,
264 yenta_suspend,
265 yenta_get_status,
266 yenta_get_socket,
267 yenta_set_socket,
268 yenta_get_io_map,
269 yenta_set_io_map,
270 yenta_get_mem_map,
271 yenta_set_mem_map,
272 yenta_proc_setup
273 };
274
275 #endif /* CONFIG_CARDBUS */
276
277 #endif /* _LINUX_TI113X_H */
278
279
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