1 /*
2 * 53c710 driver. Modified from Drew Eckhardts driver
3 * for 53c810 by Richard Hirst [richard@sleepie.demon.co.uk]
4 *
5 * I have left the code for the 53c8xx family in here, because it didn't
6 * seem worth removing it. The possibility of IO_MAPPED chips rather
7 * than MEMORY_MAPPED remains, in case someone wants to add support for
8 * 53c710 chips on Intel PCs (some older machines have them on the
9 * motherboard).
10 *
11 * NOTE THERE MAY BE PROBLEMS WITH CASTS IN read8 AND Co.
12 */
13
14 /*
15 * NCR 53c{7,8}0x0 driver, header file
16 *
17 * Sponsored by
18 * iX Multiuser Multitasking Magazine
19 * Hannover, Germany
20 * hm@ix.de
21 *
22 * Copyright 1993, 1994, 1995 Drew Eckhardt
23 * Visionary Computing
24 * (Unix and Linux consulting and custom programming)
25 * drew@PoohSticks.ORG
26 * +1 (303) 786-7975
27 *
28 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
29 *
30 * PRE-ALPHA
31 *
32 * For more information, please consult
33 *
34 * NCR 53C700/53C700-66
35 * SCSI I/O Processor
36 * Data Manual
37 *
38 * NCR 53C810
39 * PCI-SCSI I/O Processor
40 * Data Manual
41 *
42 * NCR Microelectronics
43 * 1635 Aeroplaza Drive
44 * Colorado Springs, CO 80916
45 * +1 (719) 578-3400
46 *
47 * Toll free literature number
48 * +1 (800) 334-5454
49 *
50 */
51
52 #ifndef NCR53c710_H
53 #define NCR53c710_H
54 #include <linux/version.h>
55
56 /*
57 * Prevent name space pollution in hosts.c, and only provide the
58 * define we need to get the NCR53c7x0 driver into the host template
59 * array.
60 */
61
62 #include <scsi/scsicam.h>
63
64 extern int NCR53c7xx_abort(Scsi_Cmnd *);
65 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
66 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
67 extern int NCR53c7xx_reset(Scsi_Cmnd *, unsigned int);
68 #ifdef MODULE
69 extern int NCR53c7xx_release(struct Scsi_Host *);
70 #else
71 #define NCR53c7xx_release NULL
72 #endif
73
74 #define NCR53c7xx {NULL, NULL, NULL, NULL, \
75 "NCR53c{7,8}xx (rel 17)", NCR53c7xx_detect,\
76 NULL, /* info */ NULL, /* command, deprecated */ NULL, \
77 NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
78 NULL /* slave attach */, scsicam_bios_param, /* can queue */ 24, \
79 /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 3, \
80 /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
81
82 #ifndef HOSTS_C
83
84 /* SCSI control 0 rw, default = 0xc0 */
85 #define SCNTL0_REG 0x00
86 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
87 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
88 #define SCNTL0_STRT 0x20 /* Start Sequence */
89 #define SCNTL0_WATN 0x10 /* Select with ATN */
90 #define SCNTL0_EPC 0x08 /* Enable parity checking */
91 /* Bit 2 is reserved on 800 series chips */
92 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
93 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
94 #define SCNTL0_TRG 0x01 /* Target mode */
95
96 /* SCSI control 1 rw, default = 0x00 */
97
98 #define SCNTL1_REG 0x01
99 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
100 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
101 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
102 and reselection */
103 #define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
104 target mode only */
105 #define SCNTL1_CON 0x10 /* Connected */
106 #define SCNTL1_RST 0x08 /* SCSI RST/ */
107 #define SCNTL1_AESP 0x04 /* Force bad parity */
108 #define SCNTL1_SND_700 0x02 /* Start SCSI send */
109 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
110 arbitration immediately after
111 busfree is detected */
112 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
113 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
114
115 /* SCSI control 2 rw, */
116
117 #define SCNTL2_REG_800 0x02
118 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
119
120 /* SCSI control 3 rw */
121
122 #define SCNTL3_REG_800 0x03
123 #define SCNTL3_800_SCF_SHIFT 4
124 #define SCNTL3_800_SCF_MASK 0x70
125 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
126 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
127 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
128 /* 0x20 = SCLK/1.5
129 0x30 = SCLK/2
130 0x40 = SCLK/3 */
131
132 #define SCNTL3_800_CCF_SHIFT 0
133 #define SCNTL3_800_CCF_MASK 0x07
134 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
135 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
136 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
137 0x03 37.51 - 50
138 0x04 50.01 - 66 */
139
140 /*
141 * SCSI destination ID rw - the appropriate bit is set for the selected
142 * target ID. This is written by the SCSI SCRIPTS processor.
143 * default = 0x00
144 */
145 #define SDID_REG_700 0x02
146 #define SDID_REG_800 0x06
147
148 #define GP_REG_800 0x07 /* General purpose IO */
149 #define GP_800_IO1 0x02
150 #define GP_800_IO2 0x01
151
152 /* SCSI interrupt enable rw, default = 0x00 */
153 #define SIEN_REG_700 0x03
154 #define SIEN0_REG_800 0x40
155 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
156 #define SIEN_FC 0x40 /* Function complete */
157 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
158 #define SIEN_800_SEL 0x20 /* Selected */
159 #define SIEN_700_SEL 0x10 /* Selected or reselected */
160 #define SIEN_800_RESEL 0x10 /* Reselected */
161 #define SIEN_SGE 0x08 /* SCSI gross error */
162 #define SIEN_UDC 0x04 /* Unexpected disconnect */
163 #define SIEN_RST 0x02 /* SCSI RST/ received */
164 #define SIEN_PAR 0x01 /* Parity error */
165
166 /*
167 * SCSI chip ID rw
168 * NCR53c700 :
169 * When arbitrating, the highest bit is used, when reselection or selection
170 * occurs, the chip responds to all IDs for which a bit is set.
171 * default = 0x00
172 * NCR53c810 :
173 * Uses bit mapping
174 */
175 #define SCID_REG 0x04
176 /* Bit 7 is reserved on 800 series chips */
177 #define SCID_800_RRE 0x40 /* Enable response to reselection */
178 #define SCID_800_SRE 0x20 /* Enable response to selection */
179 /* Bits four and three are reserved on 800 series chips */
180 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
181
182 /* SCSI transfer rw, default = 0x00 */
183 #define SXFER_REG 0x05
184 #define SXFER_DHP 0x80 /* Disable halt on parity */
185
186 #define SXFER_TP2 0x40 /* Transfer period msb */
187 #define SXFER_TP1 0x20
188 #define SXFER_TP0 0x10 /* lsb */
189 #define SXFER_TP_MASK 0x70
190 /* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
191 #define SXFER_TP_SHIFT 5
192 #define SXFER_TP_4 0x00 /* Divisors */
193 #define SXFER_TP_5 0x10<<1
194 #define SXFER_TP_6 0x20<<1
195 #define SXFER_TP_7 0x30<<1
196 #define SXFER_TP_8 0x40<<1
197 #define SXFER_TP_9 0x50<<1
198 #define SXFER_TP_10 0x60<<1
199 #define SXFER_TP_11 0x70<<1
200
201 #define SXFER_MO3 0x08 /* Max offset msb */
202 #define SXFER_MO2 0x04
203 #define SXFER_MO1 0x02
204 #define SXFER_MO0 0x01 /* lsb */
205 #define SXFER_MO_MASK 0x0f
206 #define SXFER_MO_SHIFT 0
207
208 /*
209 * SCSI output data latch rw
210 * The contents of this register are driven onto the SCSI bus when
211 * the Assert Data Bus bit of the SCNTL1 register is set and
212 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
213 */
214 #define SODL_REG_700 0x06
215 #define SODL_REG_800 0x54
216
217
218 /*
219 * SCSI output control latch rw, default = 0
220 * Note that when the chip is being manually programmed as an initiator,
221 * the MSG, CD, and IO bits must be set correctly for the phase the target
222 * is driving the bus in. Otherwise no data transfer will occur due to
223 * phase mismatch.
224 */
225
226 #define SOCL_REG 0x07
227 #define SOCL_REQ 0x80 /* REQ */
228 #define SOCL_ACK 0x40 /* ACK */
229 #define SOCL_BSY 0x20 /* BSY */
230 #define SOCL_SEL 0x10 /* SEL */
231 #define SOCL_ATN 0x08 /* ATN */
232 #define SOCL_MSG 0x04 /* MSG */
233 #define SOCL_CD 0x02 /* C/D */
234 #define SOCL_IO 0x01 /* I/O */
235
236 /*
237 * SCSI first byte received latch ro
238 * This register contains the first byte received during a block MOVE
239 * SCSI SCRIPTS instruction, including
240 *
241 * Initiator mode Target mode
242 * Message in Command
243 * Status Message out
244 * Data in Data out
245 *
246 * It also contains the selecting or reselecting device's ID and our
247 * ID.
248 *
249 * Note that this is the register the various IF conditionals can
250 * operate on.
251 */
252 #define SFBR_REG 0x08
253
254 /*
255 * SCSI input data latch ro
256 * In initiator mode, data is latched into this register on the rising
257 * edge of REQ/. In target mode, data is latched on the rising edge of
258 * ACK/
259 */
260 #define SIDL_REG_700 0x09
261 #define SIDL_REG_800 0x50
262
263 /*
264 * SCSI bus data lines ro
265 * This register reflects the instantaneous status of the SCSI data
266 * lines. Note that SCNTL0 must be set to disable parity checking,
267 * otherwise reading this register will latch new parity.
268 */
269 #define SBDL_REG_700 0x0a
270 #define SBDL_REG_800 0x58
271
272 #define SSID_REG_800 0x0a
273 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
274 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
275
276
277 /*
278 * SCSI bus control lines rw,
279 * instantaneous readout of control lines
280 */
281 #define SBCL_REG 0x0b
282 #define SBCL_REQ 0x80 /* REQ ro */
283 #define SBCL_ACK 0x40 /* ACK ro */
284 #define SBCL_BSY 0x20 /* BSY ro */
285 #define SBCL_SEL 0x10 /* SEL ro */
286 #define SBCL_ATN 0x08 /* ATN ro */
287 #define SBCL_MSG 0x04 /* MSG ro */
288 #define SBCL_CD 0x02 /* C/D ro */
289 #define SBCL_IO 0x01 /* I/O ro */
290 #define SBCL_PHASE_CMDOUT SBCL_CD
291 #define SBCL_PHASE_DATAIN SBCL_IO
292 #define SBCL_PHASE_DATAOUT 0
293 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
294 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
295 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
296 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
297 /*
298 * Synchronous SCSI Clock Control bits
299 * 0 - set by DCNTL
300 * 1 - SCLK / 1.0
301 * 2 - SCLK / 1.5
302 * 3 - SCLK / 2.0
303 */
304 #define SBCL_SSCF1 0x02 /* wo, -66 only */
305 #define SBCL_SSCF0 0x01 /* wo, -66 only */
306 #define SBCL_SSCF_MASK 0x03
307
308 /*
309 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
310 * insure that 10 clocks elapse between the two
311 */
312 /* DMA status ro */
313 #define DSTAT_REG 0x0c
314 #define DSTAT_DFE 0x80 /* DMA FIFO empty */
315 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
316 #define DSTAT_800_BF 0x20 /* Bus Fault */
317 #define DSTAT_ABRT 0x10 /* Aborted - set on error */
318 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
319 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
320 set when INT instruction is
321 executed */
322 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
323 #define DSTAT_OPC 0x01 /* Illegal instruction */
324 #define DSTAT_800_IID 0x01 /* Same thing, different name */
325
326
327 /* NCR53c800 moves this stuff into SIST0 */
328 #define SSTAT0_REG 0x0d /* SCSI status 0 ro */
329 #define SIST0_REG_800 0x42
330 #define SSTAT0_MA 0x80 /* ini : phase mismatch,
331 * tgt : ATN/ asserted
332 */
333 #define SSTAT0_CMP 0x40 /* function complete */
334 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
335 #define SIST0_800_SEL 0x20 /* Selected */
336 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
337 #define SIST0_800_RSL 0x10 /* Reselected */
338 #define SSTAT0_SGE 0x08 /* SCSI gross error */
339 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
340 #define SSTAT0_RST 0x02 /* SCSI RST/ received */
341 #define SSTAT0_PAR 0x01 /* Parity error */
342
343 /* And uses SSTAT0 for what was SSTAT1 */
344
345 #define SSTAT1_REG 0x0e /* SCSI status 1 ro */
346 #define SSTAT1_ILF 0x80 /* SIDL full */
347 #define SSTAT1_ORF 0x40 /* SODR full */
348 #define SSTAT1_OLF 0x20 /* SODL full */
349 #define SSTAT1_AIP 0x10 /* Arbitration in progress */
350 #define SSTAT1_LOA 0x08 /* Lost arbitration */
351 #define SSTAT1_WOA 0x04 /* Won arbitration */
352 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
353 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
354
355 #define SSTAT2_REG 0x0f /* SCSI status 2 ro */
356 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
357 #define SSTAT2_FF2 0x40 /* data FIFO */
358 #define SSTAT2_FF1 0x20
359 #define SSTAT2_FF0 0x10
360 #define SSTAT2_FF_MASK 0xf0
361 #define SSTAT2_FF_SHIFT 4
362
363 /*
364 * Latched signals, latched on the leading edge of REQ/ for initiators,
365 * ACK/ for targets.
366 */
367 #define SSTAT2_SDP 0x08 /* SDP */
368 #define SSTAT2_MSG 0x04 /* MSG */
369 #define SSTAT2_CD 0x02 /* C/D */
370 #define SSTAT2_IO 0x01 /* I/O */
371 #define SSTAT2_PHASE_CMDOUT SSTAT2_CD
372 #define SSTAT2_PHASE_DATAIN SSTAT2_IO
373 #define SSTAT2_PHASE_DATAOUT 0
374 #define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
375 #define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG)
376 #define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO)
377 #define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
378
379
380 /* NCR53c700-66 only */
381 #define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
382 /* NCR53c710 and higher */
383 #define DSA_REG 0x10 /* DATA structure address */
384
385 #define CTEST0_REG_700 0x14 /* Chip test 0 ro */
386 #define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
387 /* 0x80 - 0x04 are reserved */
388 #define CTEST0_700_RTRG 0x02 /* Real target mode */
389 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
390 * SCSI bus to host, 0 =
391 * host to SCSI.
392 */
393
394 #define CTEST1_REG_700 0x15 /* Chip test 1 ro */
395 #define CTEST1_REG_800 0x19 /* Chip test 1 ro */
396 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
397 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
398 #define CTEST1_FMT1 0x20
399 #define CTEST1_FMT0 0x10
400
401 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
402 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
403 #define CTEST1_FFL1 0x02
404 #define CTEST1_FFL0 0x01
405
406 #define CTEST2_REG_700 0x16 /* Chip test 2 ro */
407 #define CTEST2_REG_800 0x1a /* Chip test 2 ro */
408
409 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
410 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
411 Reading this register clears */
412 #define CTEST2_800_CIO 0x20 /* Configured as IO */.
413 #define CTEST2_800_CM 0x10 /* Configured as memory */
414
415 /* 0x80 - 0x40 are reserved on 700 series chips */
416 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
417 * As an initiator, this bit is
418 * one when the synchronous offset
419 * is zero, as a target this bit
420 * is one when the synchronous
421 * offset is at the maximum
422 * defined in SXFER
423 */
424 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
425 * reading CTEST3 unloads a byte
426 * from the FIFO and sets this
427 */
428 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
429 * reading CTEST6 unloads a byte
430 * from the FIFO and sets this
431 */
432 #define CTEST2_TEOP 0x04 /* SCSI true end of process,
433 * indicates a totally finished
434 * transfer
435 */
436 #define CTEST2_DREQ 0x02 /* Data request signal */
437 /* 0x01 is reserved on 700 series chips */
438 #define CTEST2_800_DACK 0x01
439
440 /*
441 * Chip test 3 ro
442 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
443 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
444 * error results if a read is attempted on this register. Also note
445 * that 16 and 32 bit reads of this register will cause corruption.
446 */
447 #define CTEST3_REG_700 0x17
448 /* Chip test 3 rw */
449 #define CTEST3_REG_800 0x1b
450 #define CTEST3_800_V3 0x80 /* Chip revision */
451 #define CTEST3_800_V2 0x40
452 #define CTEST3_800_V1 0x20
453 #define CTEST3_800_V0 0x10
454 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
455 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
456 #define CTEST3_800_FM 0x02 /* Fetch mode pin */
457 /* bit 0 is reserved on 800 series chips */
458
459 #define CTEST4_REG_700 0x18 /* Chip test 4 rw */
460 #define CTEST4_REG_800 0x21 /* Chip test 4 rw */
461 /* 0x80 is reserved on 700 series chips */
462 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
463 #define CTEST4_ZMOD 0x40 /* High impedance mode */
464 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
465 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
466 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
467 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
468 * redirects writes from SODL
469 * to the SCSI FIFO.
470 */
471 #define CTEST4_800_MPEE 0x08 /* Enable parity checking
472 during master cycles on PCI
473 bus */
474
475 /*
476 * These bits send the contents of the CTEST6 register to the appropriate
477 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
478 * the high bit means the low two bits select the byte lane.
479 */
480 #define CTEST4_FBL2 0x04
481 #define CTEST4_FBL1 0x02
482 #define CTEST4_FBL0 0x01
483 #define CTEST4_FBL_MASK 0x07
484 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
485 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
486 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
487 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
488 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
489
490
491 #define CTEST5_REG_700 0x19 /* Chip test 5 rw */
492 #define CTEST5_REG_800 0x22 /* Chip test 5 rw */
493 /*
494 * Clock Address Incrementor. When set, it increments the
495 * DNAD register to the next bus size boundary. It automatically
496 * resets itself when the operation is complete.
497 */
498 #define CTEST5_ADCK 0x80
499 /*
500 * Clock Byte Counter. When set, it decrements the DBC register to
501 * the next bus size boundary.
502 */
503 #define CTEST5_BBCK 0x40
504 /*
505 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
506 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
507 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
508 * be cleared when a synchronous transfer fails. When written, it is
509 * automatically cleared after the SCSI synchronous offset counter is
510 * reset.
511 */
512 /* Bit 5 is reserved on 800 series chips */
513 #define CTEST5_700_ROFF 0x20
514 /*
515 * Master Control for Set or Reset pulses. When 1, causes the low
516 * four bits of register to set when set, 0 causes the low bits to
517 * clear when set.
518 */
519 #define CTEST5_MASR 0x10
520 #define CTEST5_DDIR 0x08 /* DMA direction */
521 /*
522 * Bits 2-0 are reserved on 800 series chips
523 */
524 #define CTEST5_700_EOP 0x04 /* End of process */
525 #define CTEST5_700_DREQ 0x02 /* Data request */
526 #define CTEST5_700_DACK 0x01 /* Data acknowledge */
527
528 /*
529 * Chip test 6 rw - writing to this register writes to the byte
530 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
531 * register.
532 */
533 #define CTEST6_REG_700 0x1a
534 #define CTEST6_REG_800 0x23
535
536 #define CTEST7_REG 0x1b /* Chip test 7 rw */
537 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
538 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
539 #define CTEST7_10_SC1 0x40 /* Snoop control bits */
540 #define CTEST7_10_SC0 0x20
541 #define CTEST7_10_SC_MASK 0x60
542 /* 0x20 is reserved on the NCR53c700 */
543 #define CTEST7_0060_FM 0x20 /* Fetch mode */
544 #define CTEST7_STD 0x10 /* Selection timeout disable */
545 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
546 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
547 #define CTEST7_10_TT1 0x02 /* Transfer type */
548 #define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
549 fetch */
550 #define CTEST7_DIFF 0x01 /* Differential mode */
551
552 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
553
554
555 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
556
557 #define DFIFO_REG 0x20 /* DMA FIFO rw */
558 /*
559 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
560 * moved into the CTEST8 register.
561 */
562 #define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
563 #define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
564 #define DFIFO_BO6 0x40
565 #define DFIFO_BO5 0x20
566 #define DFIFO_BO4 0x10
567 #define DFIFO_BO3 0x08
568 #define DFIFO_BO2 0x04
569 #define DFIFO_BO1 0x02
570 #define DFIFO_BO0 0x01
571 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
572 #define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
573
574 /*
575 * Interrupt status rw
576 * Note that this is the only register which can be read while SCSI
577 * SCRIPTS are being executed.
578 */
579 #define ISTAT_REG_700 0x21
580 #define ISTAT_REG_800 0x14
581 #define ISTAT_ABRT 0x80 /* Software abort, write
582 *1 to abort, wait for interrupt. */
583 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
584 #define ISTAT_10_SRST 0x40 /* software reset */
585 #define ISTAT_10_SIGP 0x20 /* signal script */
586 /* 0x10 is reserved on NCR53c700 series chips */
587 #define ISTAT_800_SEM 0x10 /* semaphore */
588 #define ISTAT_CON 0x08 /* 1 when connected */
589 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
590 #define ISTAT_700_PRE 0x04 /* Pointer register empty.
591 * Set to 1 when DSPS and DSP
592 * registers are empty in pipeline
593 * mode, always set otherwise.
594 */
595 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
596 * SCSI portion of SIOP see
597 * SSTAT0
598 */
599 #define ISTAT_DIP 0x01 /* DMA interrupt pending
600 * see DSTAT
601 */
602
603 /* NCR53c700-66 and NCR53c710 only */
604 #define CTEST8_REG 0x22 /* Chip test 8 rw */
605 #define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
606 * ie read from SCLK/ rather than CLK/
607 */
608 #define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
609 #define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
610 * pass through. This insures that
611 * bad parity won't reach the host
612 * bus.
613 */
614 #define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
615 * active negation, should only
616 * be used for slow SCSI
617 * non-differential.
618 */
619 #define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
620 #define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
621 * must be set for fast SCSI-II
622 * speeds.
623 */
624 #define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
625 * switching.
626 */
627 #define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
628 * The status of pending
629 * disconnect is maintained by
630 * the core, eliminating
631 * the possibility of missing a
632 * selection or reselection
633 * while waiting to fetch a
634 * WAIT DISCONNECT opcode.
635 */
636
637 #define CTEST8_10_V3 0x80 /* Chip revision */
638 #define CTEST8_10_V2 0x40
639 #define CTEST8_10_V1 0x20
640 #define CTEST8_10_V0 0x10
641 #define CTEST8_10_V_MASK 0xf0
642 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
643 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
644 #define CTEST8_10_FM 0x02 /* Fetch pin mode */
645 #define CTEST8_10_SM 0x01 /* Snoop pin mode */
646
647
648 /*
649 * The CTEST9 register may be used to differentiate between a
650 * NCR53c700 and a NCR53c710.
651 *
652 * Write 0xff to this register.
653 * Read it.
654 * If the contents are 0xff, it is a NCR53c700
655 * If the contents are 0x00, it is a NCR53c700-66 first revision
656 * If the contents are some other value, it is some other NCR53c700-66
657 */
658 #define CTEST9_REG_00 0x23 /* Chip test 9 ro */
659 #define LCRC_REG_10 0x23
660
661 /*
662 * 0x24 through 0x27 are the DMA byte counter register. Instructions
663 * write their high 8 bits into the DCMD register, the low 24 bits into
664 * the DBC register.
665 *
666 * Function is dependent on the command type being executed.
667 */
668
669
670 #define DBC_REG 0x24
671 /*
672 * For Block Move Instructions, DBC is a 24 bit quantity representing
673 * the number of bytes to transfer.
674 * For Transfer Control Instructions, DBC is bit fielded as follows :
675 */
676 /* Bits 20 - 23 should be clear */
677 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
678 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
679 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
680 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
681 /* Bits 8 - 15 are reserved on some implementations ? */
682 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
683 #define DBC_TCI_MASK_SHIFT 8
684 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
685 #define DBC_TCI_DATA_SHIFT 0
686
687 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
688 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
689 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
690 #define DBC_RWRI_ADDRESS_SHIFT 16
691
692
693 /*
694 * DMA command r/w
695 */
696 #define DCMD_REG 0x27
697 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
698 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
699 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
700 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
701 #define DCMD_BMI_MSG 0x04 /* instruction */
702
703 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
704 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
705 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
706
707 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
708
709 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
710 instruction */
711 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
712 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
713 #define DCMD_TCI_MSG 0x04 /* instruction */
714 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
715 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
716 #define DCMD_TCI_OP_CALL 0x08 /* CALL */
717 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
718 #define DCMD_TCI_OP_INT 0x18 /* INT */
719
720 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
721 instruction */
722 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
723 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
724 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
725 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
726
727 #define DCMD_RWRI_OP_MASK 0x07
728 #define DCMD_RWRI_OP_MOVE 0x00
729 #define DCMD_RWRI_OP_SHL 0x01
730 #define DCMD_RWRI_OP_OR 0x02
731 #define DCMD_RWRI_OP_XOR 0x03
732 #define DCMD_RWRI_OP_AND 0x04
733 #define DCMD_RWRI_OP_SHR 0x05
734 #define DCMD_RWRI_OP_ADD 0x06
735 #define DCMD_RWRI_OP_ADDC 0x07
736
737 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
738 (three words) */
739
740
741 #define DNAD_REG 0x28 /* through 0x2b DMA next address for
742 data */
743 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
744 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
745 save rw */
746 #define DMODE_REG_00 0x34 /* DMA mode rw */
747 #define DMODE_00_BL1 0x80 /* Burst length bits */
748 #define DMODE_00_BL0 0x40
749 #define DMODE_BL_MASK 0xc0
750 /* Burst lengths (800) */
751 #define DMODE_BL_2 0x00 /* 2 transfer */
752 #define DMODE_BL_4 0x40 /* 4 transfers */
753 #define DMODE_BL_8 0x80 /* 8 transfers */
754 #define DMODE_BL_16 0xc0 /* 16 transfers */
755
756 #define DMODE_10_BL_1 0x00 /* 1 transfer */
757 #define DMODE_10_BL_2 0x40 /* 2 transfers */
758 #define DMODE_10_BL_4 0x80 /* 4 transfers */
759 #define DMODE_10_BL_8 0xc0 /* 8 transfers */
760 #define DMODE_10_FC2 0x20 /* Driven to FC2 pin */
761 #define DMODE_10_FC1 0x10 /* Driven to FC1 pin */
762 #define DMODE_710_PD 0x08 /* Program/data on FC0 pin */
763 #define DMODE_710_UO 0x02 /* User prog. output */
764
765 #define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
766 #define DMODE_700_286 0x10 /* 286 mode */
767 #define DMODE_700_IOM 0x08 /* Transfer to IO port */
768 #define DMODE_700_FAM 0x04 /* Fixed address mode */
769 #define DMODE_700_PIPE 0x02 /* Pipeline mode disables
770 * automatic fetch / exec
771 */
772 #define DMODE_MAN 0x01 /* Manual start mode,
773 * requires a 1 to be written
774 * to the start DMA bit in the DCNTL
775 * register to run scripts
776 */
777
778 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
779
780 /* NCR53c800 series only */
781 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
782 /* NCR53c710 only */
783 #define SCRATCHB_REG_10 0x34 /* through 0x37 scratch B rw */
784
785 #define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
786 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
787 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
788 #define DMODE_800_ERL 0x08 /* Enable Read Line */
789
790 /* 35-38 are reserved on 700 and 700-66 series chips */
791 #define DIEN_REG 0x39 /* DMA interrupt enable rw */
792 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
793 #define DIEN_800_MDPE 0x40 /* Master data parity error */
794 #define DIEN_800_BF 0x20 /* BUS fault */
795 #define DIEN_700_BF 0x20 /* BUS fault */
796 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
797 #define DIEN_SSI 0x08 /* Enable single step interrupt */
798 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
799 * interrupt
800 */
801 /* 0x02 is reserved on 800 series chips */
802 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
803 #define DIEN_700_OPC 0x01 /* Enable illegal instruction
804 * interrupt
805 */
806 #define DIEN_800_IID 0x01 /* Same meaning, different name */
807
808 /*
809 * DMA watchdog timer rw
810 * set in 16 CLK input periods.
811 */
812 #define DWT_REG 0x3a
813
814 /* DMA control rw */
815 #define DCNTL_REG 0x3b
816 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
817 #define DCNTL_700_CF0 0x40
818 #define DCNTL_700_CF_MASK 0xc0
819 /* Clock divisors Divisor SCLK range (MHZ) */
820 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
821 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
822 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
823 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
824
825 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
826 #define DCNTL_SSM 0x10 /* Single step mode */
827 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
828 * after selection */
829 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
830 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
831 /* 0x02 is reserved */
832 #define DCNTL_00_RST 0x01 /* Software reset, resets everything
833 * but 286 mode bit in DMODE. On the
834 * NCR53c710, this bit moved to CTEST8
835 */
836 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
837 #define DCNTL_10_EA 0x20 /* Enable Ack - needed for MVME16x */
838
839 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
840
841
842 /* NCR53c700-66 only */
843 #define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
844 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
845 /* NCR53c710 only */
846 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
847
848 #define SIEN1_REG_800 0x41
849 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
850 #define SIEN1_800_GEN 0x02 /* general purpose timer */
851 #define SIEN1_800_HTH 0x01 /* handshake to handshake */
852
853 #define SIST1_REG_800 0x43
854 #define SIST1_800_STO 0x04 /* selection/reselection timeout */
855 #define SIST1_800_GEN 0x02 /* general purpose timer */
856 #define SIST1_800_HTH 0x01 /* handshake to handshake */
857
858 #define SLPAR_REG_800 0x44 /* Parity */
859
860 #define MACNTL_REG_800 0x46 /* Memory access control */
861 #define MACNTL_800_TYP3 0x80
862 #define MACNTL_800_TYP2 0x40
863 #define MACNTL_800_TYP1 0x20
864 #define MACNTL_800_TYP0 0x10
865 #define MACNTL_800_DWR 0x08
866 #define MACNTL_800_DRD 0x04
867 #define MACNTL_800_PSCPT 0x02
868 #define MACNTL_800_SCPTS 0x01
869
870 #define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
871
872 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
873 #define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
874 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
875 #define STIME0_800_HTH_SHIFT 4
876 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
877 #define STIME0_800_SEL_SHIFT 0
878
879 #define STIME1_REG_800 0x49
880 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
881
882 #define RESPID_REG_800 0x4a /* Response ID, bit fielded. 8
883 bits on narrow chips, 16 on WIDE */
884
885 #define STEST0_REG_800 0x4c
886 #define STEST0_800_SLT 0x08 /* Selection response logic test */
887 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
888 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
889 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
890
891 #define STEST1_REG_800 0x4d
892 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
893
894 #define STEST2_REG_800 0x4e
895 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
896 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
897 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
898 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
899 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
900 #define STEST2_800_LOW 0x01 /* SCSI low level mode */
901
902 #define STEST3_REG_800 0x4f
903 #define STEST3_800_TE 0x80 /* Enable active negation */
904 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
905 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
906 #define STEST3_800_DSI 0x10 /* Disable single initiator response */
907 #define STEST3_800_TTM 0x04 /* Time test mode */
908 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
909 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
910
911 #define OPTION_PARITY 0x1 /* Enable parity checking */
912 #define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
913 #define OPTION_700 0x8 /* Always run NCR53c700 scripts */
914 #define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
915 #define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
916 #define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
917 simple test code, return
918 DID_NO_CONNECT if any SCSI
919 commands are attempted. */
920 #define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
921 SCSI write is attempted */
922 #define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
923 each address and instruction
924 executed to debug buffer. */
925 #define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
926 instruction */
927 #define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
928 #define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
929 memory mapping */
930 #define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
931 I/O mapping */
932 #define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
933 #define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
934 #define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
935 #define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
936 #define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
937 #define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
938 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
939 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
940 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
941 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
942 #define OPTION_DEBUG_DSA 0x800000
943 #define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
944 #define OPTION_DEBUG_SDTR 0x2000000 /* Debug SDTR problem */
945 #define OPTION_DEBUG_MISMATCH 0x4000000 /* Debug phase mismatches */
946 #define OPTION_DISCONNECT 0x8000000 /* Allow disconnect */
947 #define OPTION_DEBUG_DISCONNECT 0x10000000
948 #define OPTION_ALWAYS_SYNCHRONOUS 0x20000000 /* Negotiate sync. transfers
949 on power up */
950 #define OPTION_DEBUG_QUEUES 0x80000000
951 #define OPTION_DEBUG_ALLOCATION 0x100000000LL
952 #define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL /* Sanity check SXFER and
953 SCNTL3 registers */
954 #define OPTION_NO_ASYNC 0x400000000LL /* Don't automagically send
955 SDTR for async transfers when
956 we haven't been told to do
957 a synchronous transfer. */
958 #define OPTION_NO_PRINT_RACE 0x800000000LL /* Don't print message when
959 the reselect/WAIT DISCONNECT
960 race condition hits */
961 #if !defined(PERM_OPTIONS)
962 #define PERM_OPTIONS 0
963 #endif
964
965 /*
966 * Some data which is accessed by the NCR chip must be 4-byte aligned.
967 * For some hosts the default is less than that (eg. 68K uses 2-byte).
968 * Alignment has only been forced where it is important; also if one
969 * 32 bit structure field is aligned then it is assumed that following
970 * 32 bit fields are also aligned. Take care when adding fields
971 * which are other than 32 bit.
972 */
973
974 struct NCR53c7x0_synchronous {
975 u32 select_indirect /* Value used for indirect selection */
976 __attribute__ ((aligned (4)));
977 u32 sscf_710; /* Used to set SSCF bits for 710 */
978 u32 script[8]; /* Size ?? Script used when target is
979 reselected */
980 unsigned char synchronous_want[5]; /* Per target desired SDTR */
981 /*
982 * Set_synchronous programs these, select_indirect and current settings after
983 * int_debug_should show a match.
984 */
985 unsigned char sxfer_sanity, scntl3_sanity;
986 };
987
988 #define CMD_FLAG_SDTR 1 /* Initiating synchronous
989 transfer negotiation */
990 #define CMD_FLAG_WDTR 2 /* Initiating wide transfer
991 negotiation */
992 #define CMD_FLAG_DID_SDTR 4 /* did SDTR */
993 #define CMD_FLAG_DID_WDTR 8 /* did WDTR */
994
995 struct NCR53c7x0_table_indirect {
996 u32 count;
997 void *address;
998 };
999
1000 enum ncr_event {
1001 EVENT_NONE = 0,
1002 /*
1003 * Order is IMPORTANT, since these must correspond to the event interrupts
1004 * in 53c7,8xx.scr
1005 */
1006
1007 EVENT_ISSUE_QUEUE = 0x5000000, /* 0 Command was added to issue queue */
1008 EVENT_START_QUEUE, /* 1 Command moved to start queue */
1009 EVENT_SELECT, /* 2 Command completed selection */
1010 EVENT_DISCONNECT, /* 3 Command disconnected */
1011 EVENT_RESELECT, /* 4 Command reselected */
1012 EVENT_COMPLETE, /* 5 Command completed */
1013 EVENT_IDLE, /* 6 */
1014 EVENT_SELECT_FAILED, /* 7 */
1015 EVENT_BEFORE_SELECT, /* 8 */
1016 EVENT_RESELECT_FAILED /* 9 */
1017 };
1018
1019 struct NCR53c7x0_event {
1020 enum ncr_event event; /* What type of event */
1021 unsigned char target;
1022 unsigned char lun;
1023 struct timeval time;
1024 u32 *dsa; /* What's in the DSA register now (virt) */
1025 /*
1026 * A few things from that SCSI pid so we know what happened after
1027 * the Scsi_Cmnd structure in question may have disappeared.
1028 */
1029 unsigned long pid; /* The SCSI PID which caused this
1030 event */
1031 unsigned char cmnd[12];
1032 };
1033
1034 /*
1035 * Things in the NCR53c7x0_cmd structure are split into two parts :
1036 *
1037 * 1. A fixed portion, for things which are not accessed directly by static NCR
1038 * code (ie, are referenced only by the Linux side of the driver,
1039 * or only by dynamically generated code).
1040 *
1041 * 2. The DSA portion, for things which are accessed directly by static NCR
1042 * code.
1043 *
1044 * This is a little ugly, but it
1045 * 1. Avoids conflicts between the NCR code's picture of the structure, and
1046 * Linux code's idea of what it looks like.
1047 *
1048 * 2. Minimizes the pain in the Linux side of the code needed
1049 * to calculate real dsa locations for things, etc.
1050 *
1051 */
1052
1053 struct NCR53c7x0_cmd {
1054 void *real; /* Real, unaligned address for
1055 free function */
1056 void (* free)(void *, int); /* Command to deallocate; NULL
1057 for structures allocated with
1058 scsi_register, etc. */
1059 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
1060 structure, Scsi_Cmnd points
1061 at NCR53c7x0_cmd using
1062 host_scribble structure */
1063
1064 int size; /* scsi_malloc'd size of this
1065 structure */
1066
1067 int flags; /* CMD_* flags */
1068
1069 unsigned char cmnd[12]; /* CDB, copied from Scsi_Cmnd */
1070 int result; /* Copy to Scsi_Cmnd when done */
1071
1072 struct { /* Private non-cached bounce buffer */
1073 unsigned char buf[256];
1074 u32 addr;
1075 u32 len;
1076 } bounce;
1077
1078 /*
1079 * SDTR and WIDE messages are an either/or affair
1080 * in this message, since we will go into message out and send
1081 * _the whole mess_ without dropping out of message out to
1082 * let the target go into message in after sending the first
1083 * message.
1084 */
1085
1086 unsigned char select[11]; /* Select message, includes
1087 IDENTIFY
1088 (optional) QUEUE TAG
1089 (optional) SDTR or WDTR
1090 */
1091
1092
1093 volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
1094 running, eventually finished */
1095
1096
1097 u32 *data_transfer_start; /* Start of data transfer routines */
1098 u32 *data_transfer_end; /* Address after end of data transfer o
1099 routines */
1100 /*
1101 * The following three fields were moved from the DSA proper to here
1102 * since only dynamically generated NCR code refers to them, meaning
1103 * we don't need dsa_* absolutes, and it is simpler to let the
1104 * host code refer to them directly.
1105 */
1106
1107 /*
1108 * HARD CODED : residual and saved_residual need to agree with the sizes
1109 * used in NCR53c7,8xx.scr.
1110 *
1111 * FIXME: we want to consider the case where we have odd-length
1112 * scatter/gather buffers and a WIDE transfer, in which case
1113 * we'll need to use the CHAIN MOVE instruction. Ick.
1114 */
1115 u32 residual[6] __attribute__ ((aligned (4)));
1116 /* Residual data transfer which
1117 allows pointer code to work
1118 right.
1119
1120 [0-1] : Conditional call to
1121 appropriate other transfer
1122 routine.
1123 [2-3] : Residual block transfer
1124 instruction.
1125 [4-5] : Jump to instruction
1126 after splice.
1127 */
1128 u32 saved_residual[6]; /* Copy of old residual, so we
1129 can get another partial
1130 transfer and still recover
1131 */
1132
1133 u32 saved_data_pointer; /* Saved data pointer */
1134
1135 u32 dsa_next_addr; /* _Address_ of dsa_next field
1136 in this dsa for RISCy
1137 style constant. */
1138
1139 u32 dsa_addr; /* Address of dsa; RISCy style
1140 constant */
1141
1142 u32 dsa[0]; /* Variable length (depending
1143 on host type, number of scatter /
1144 gather buffers, etc). */
1145 };
1146
1147 struct NCR53c7x0_break {
1148 u32 *address, old_instruction[2];
1149 struct NCR53c7x0_break *next;
1150 unsigned char old_size; /* Size of old instruction */
1151 };
1152
1153 /* Indicates that the NCR is not executing code */
1154 #define STATE_HALTED 0
1155 /*
1156 * Indicates that the NCR is executing the wait for select / reselect
1157 * script. Only used when running NCR53c700 compatible scripts, only
1158 * state during which an ABORT is _not_ considered an error condition.
1159 */
1160 #define STATE_WAITING 1
1161 /* Indicates that the NCR is executing other code. */
1162 #define STATE_RUNNING 2
1163 /*
1164 * Indicates that the NCR was being aborted.
1165 */
1166 #define STATE_ABORTING 3
1167 /* Indicates that the NCR was successfully aborted. */
1168 #define STATE_ABORTED 4
1169 /* Indicates that the NCR has been disabled due to a fatal error */
1170 #define STATE_DISABLED 5
1171
1172 /*
1173 * Where knowledge of SCSI SCRIPT(tm) specified values are needed
1174 * in an interrupt handler, an interrupt handler exists for each
1175 * different SCSI script so we don't have name space problems.
1176 *
1177 * Return values of these handlers are as follows :
1178 */
1179 #define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1180 #define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1181 #define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1182 #define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1183 #define SPECIFIC_INT_DONE 4 /* normal command completion */
1184 #define SPECIFIC_INT_BREAK 5 /* break point encountered */
1185
1186 struct NCR53c7x0_hostdata {
1187 int size; /* Size of entire Scsi_Host
1188 structure */
1189 int board; /* set to board type, useful if
1190 we have host specific things,
1191 ie, a general purpose I/O
1192 bit is being used to enable
1193 termination, etc. */
1194
1195 int chip; /* set to chip type; 700-66 is
1196 700-66, rest are last three
1197 digits of part number */
1198
1199 char valid_ids[8]; /* Valid SCSI ID's for adapter */
1200
1201 u32 *dsp; /* dsp to restart with after
1202 all stacked interrupts are
1203 handled. */
1204
1205 unsigned dsp_changed:1; /* Has dsp changed within this
1206 set of stacked interrupts ? */
1207
1208 unsigned char dstat; /* Most recent value of dstat */
1209 unsigned dstat_valid:1;
1210
1211 unsigned expecting_iid:1; /* Expect IID interrupt */
1212 unsigned expecting_sto:1; /* Expect STO interrupt */
1213
1214 /*
1215 * The code stays cleaner if we use variables with function
1216 * pointers and offsets that are unique for the different
1217 * scripts rather than having a slew of switch(hostdata->chip)
1218 * statements.
1219 *
1220 * It also means that the #defines from the SCSI SCRIPTS(tm)
1221 * don't have to be visible outside of the script-specific
1222 * instructions, preventing name space pollution.
1223 */
1224
1225 void (* init_fixup)(struct Scsi_Host *host);
1226 void (* init_save_regs)(struct Scsi_Host *host);
1227 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1228 void (* soft_reset)(struct Scsi_Host *host);
1229 int (* run_tests)(struct Scsi_Host *host);
1230
1231 /*
1232 * Called when DSTAT_SIR is set, indicating an interrupt generated
1233 * by the INT instruction, where values are unique for each SCSI
1234 * script. Should return one of the SPEC_* values.
1235 */
1236
1237 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1238
1239 int dsa_len; /* Size of DSA structure */
1240
1241 /*
1242 * Location of DSA fields for the SCSI SCRIPT corresponding to this
1243 * chip.
1244 */
1245
1246 s32 dsa_start;
1247 s32 dsa_end;
1248 s32 dsa_next;
1249 s32 dsa_prev;
1250 s32 dsa_cmnd;
1251 s32 dsa_select;
1252 s32 dsa_msgout;
1253 s32 dsa_cmdout;
1254 s32 dsa_dataout;
1255 s32 dsa_datain;
1256 s32 dsa_msgin;
1257 s32 dsa_msgout_other;
1258 s32 dsa_write_sync;
1259 s32 dsa_write_resume;
1260 s32 dsa_check_reselect;
1261 s32 dsa_status;
1262 s32 dsa_saved_pointer;
1263 s32 dsa_jump_dest;
1264
1265 /*
1266 * Important entry points that generic fixup code needs
1267 * to know about, fixed up.
1268 */
1269
1270 s32 E_accept_message;
1271 s32 E_command_complete;
1272 s32 E_data_transfer;
1273 s32 E_dsa_code_template;
1274 s32 E_dsa_code_template_end;
1275 s32 E_end_data_transfer;
1276 s32 E_msg_in;
1277 s32 E_initiator_abort;
1278 s32 E_other_transfer;
1279 s32 E_other_in;
1280 s32 E_other_out;
1281 s32 E_target_abort;
1282 s32 E_debug_break;
1283 s32 E_reject_message;
1284 s32 E_respond_message;
1285 s32 E_select;
1286 s32 E_select_msgout;
1287 s32 E_test_0;
1288 s32 E_test_1;
1289 s32 E_test_2;
1290 s32 E_test_3;
1291 s32 E_dsa_zero;
1292 s32 E_cmdout_cmdout;
1293 s32 E_wait_reselect;
1294 s32 E_dsa_code_begin;
1295
1296 long long options; /* Bitfielded set of options enabled */
1297 volatile u32 test_completed; /* Test completed */
1298 int test_running; /* Test currently running */
1299 s32 test_source
1300 __attribute__ ((aligned (4)));
1301 volatile s32 test_dest;
1302
1303 volatile int state; /* state of driver, only used for
1304 OPTION_700 */
1305
1306 unsigned char dmode; /*
1307 * set to the address of the DMODE
1308 * register for this chip.
1309 */
1310 unsigned char istat; /*
1311 * set to the address of the ISTAT
1312 * register for this chip.
1313 */
1314
1315 int scsi_clock; /*
1316 * SCSI clock in HZ. 0 may be used
1317 * for unknown, although this will
1318 * disable synchronous negotiation.
1319 */
1320
1321 volatile int intrs; /* Number of interrupts */
1322 volatile int resets; /* Number of SCSI resets */
1323 unsigned char saved_dmode;
1324 unsigned char saved_ctest4;
1325 unsigned char saved_ctest7;
1326 unsigned char saved_dcntl;
1327 unsigned char saved_scntl3;
1328
1329 unsigned char this_id_mask;
1330
1331 /* Debugger information */
1332 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1333 *breakpoint_current; /* Current breakpoint being stepped
1334 through, NULL if we are running
1335 normally. */
1336 #ifdef NCR_DEBUG
1337 int debug_size; /* Size of debug buffer */
1338 volatile int debug_count; /* Current data count */
1339 volatile char *debug_buf; /* Output ring buffer */
1340 volatile char *debug_write; /* Current write pointer */
1341 volatile char *debug_read; /* Current read pointer */
1342 #endif /* def NCR_DEBUG */
1343
1344 /* XXX - primitive debugging junk, remove when working ? */
1345 int debug_print_limit; /* Number of commands to print
1346 out exhaustive debugging
1347 information for if
1348 OPTION_DEBUG_DUMP is set */
1349
1350 unsigned char debug_lun_limit[16]; /* If OPTION_DEBUG_TARGET_LIMIT
1351 set, puke if commands are sent
1352 to other target/lun combinations */
1353
1354 int debug_count_limit; /* Number of commands to execute
1355 before puking to limit debugging
1356 output */
1357
1358
1359 volatile unsigned idle:1; /* set to 1 if idle */
1360
1361 /*
1362 * Table of synchronous+wide transfer parameters set on a per-target
1363 * basis.
1364 */
1365
1366 volatile struct NCR53c7x0_synchronous sync[16]
1367 __attribute__ ((aligned (4)));
1368
1369 volatile Scsi_Cmnd *issue_queue
1370 __attribute__ ((aligned (4)));
1371 /* waiting to be issued by
1372 Linux driver */
1373 volatile struct NCR53c7x0_cmd *running_list;
1374 /* commands running, maintained
1375 by Linux driver */
1376
1377 volatile struct NCR53c7x0_cmd *ncrcurrent; /* currently connected
1378 nexus, ONLY valid for
1379 NCR53c700/NCR53c700-66
1380 */
1381
1382 volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
1383 allocated at probe time,
1384 which we can use for
1385 initialization */
1386 volatile struct NCR53c7x0_cmd *free;
1387 int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
1388 based on number of
1389 scatter/gather segments, etc.
1390 */
1391 volatile int num_cmds; /* Number of commands
1392 allocated */
1393 volatile int extra_allocate;
1394 volatile unsigned char cmd_allocated[16]; /* Have we allocated commands
1395 for this target yet? If not,
1396 do so ASAP */
1397 volatile unsigned char busy[16][8]; /* number of commands
1398 executing on each target
1399 */
1400 /*
1401 * Eventually, I'll switch to a coroutine for calling
1402 * cmd->done(cmd), etc. so that we can overlap interrupt
1403 * processing with this code for maximum performance.
1404 */
1405
1406 volatile struct NCR53c7x0_cmd *finished_queue;
1407
1408 /* Shared variables between SCRIPT and host driver */
1409 volatile u32 *schedule
1410 __attribute__ ((aligned (4))); /* Array of JUMPs to dsa_begin
1411 routines of various DSAs.
1412 When not in use, replace
1413 with jump to next slot */
1414
1415
1416 volatile unsigned char msg_buf[16]; /* buffer for messages
1417 other than the command
1418 complete message */
1419
1420 /* Per-target default synchronous and WIDE messages */
1421 volatile unsigned char synchronous_want[16][5];
1422 volatile unsigned char wide_want[16][4];
1423
1424 /* Bit fielded set of targets we want to speak synchronously with */
1425 volatile u16 initiate_sdtr;
1426 /* Bit fielded set of targets we want to speak wide with */
1427 volatile u16 initiate_wdtr;
1428 /* Bit fielded list of targets we've talked to. */
1429 volatile u16 talked_to;
1430
1431 /* Array of bit-fielded lun lists that we need to request_sense */
1432 volatile unsigned char request_sense[16];
1433
1434 u32 addr_reconnect_dsa_head
1435 __attribute__ ((aligned (4))); /* RISCy style constant,
1436 address of following */
1437 volatile u32 reconnect_dsa_head;
1438 /* Data identifying nexus we are trying to match during reselection */
1439 volatile unsigned char reselected_identify; /* IDENTIFY message */
1440 volatile unsigned char reselected_tag; /* second byte of queue tag
1441 message or 0 */
1442
1443 /* These were static variables before we moved them */
1444
1445 s32 NCR53c7xx_zero
1446 __attribute__ ((aligned (4)));
1447 s32 NCR53c7xx_sink;
1448 u32 NOP_insn;
1449 char NCR53c7xx_msg_reject;
1450 char NCR53c7xx_msg_abort;
1451 char NCR53c7xx_msg_nop;
1452
1453 /*
1454 * Following item introduced by RGH to support NCRc710, which is
1455 * VERY brain-dead when it come to memory moves
1456 */
1457
1458 /* DSA save area used only by the NCR chip */
1459 volatile unsigned long saved2_dsa
1460 __attribute__ ((aligned (4)));
1461
1462 volatile unsigned long emulated_intfly
1463 __attribute__ ((aligned (4)));
1464
1465 volatile int event_size, event_index;
1466 volatile struct NCR53c7x0_event *events;
1467
1468 /* If we need to generate code to kill off the currently connected
1469 command, this is where we do it. Should have a BMI instruction
1470 to source or sink the current data, followed by a JUMP
1471 to abort_connected */
1472
1473 u32 *abort_script;
1474
1475 int script_count; /* Size of script in words */
1476 u32 script[0]; /* Relocated SCSI script */
1477
1478 };
1479
1480 #define IRQ_NONE 255
1481 #define DMA_NONE 255
1482 #define IRQ_AUTO 254
1483 #define DMA_AUTO 254
1484
1485 #define BOARD_GENERIC 0
1486
1487 #define NCR53c7x0_insn_size(insn) \
1488 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1489
1490
1491 #define NCR53c7x0_local_declare() \
1492 volatile unsigned char *NCR53c7x0_address_memory; \
1493 unsigned int NCR53c7x0_address_io; \
1494 int NCR53c7x0_memory_mapped
1495
1496 #define NCR53c7x0_local_setup(host) \
1497 NCR53c7x0_address_memory = (void *) (host)->base; \
1498 NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
1499 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1500 host->hostdata[0])-> options & OPTION_MEMORY_MAPPED
1501
1502 #ifdef BIG_ENDIAN
1503 /* These could be more efficient, given that we are always memory mapped,
1504 * but they don't give the same problems as the write macros, so leave
1505 * them. */
1506 #define NCR53c7x0_read8(address) \
1507 (NCR53c7x0_memory_mapped ? \
1508 (unsigned int)readb((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) : \
1509 inb(NCR53c7x0_address_io + (address)))
1510
1511 #define NCR53c7x0_read16(address) \
1512 (NCR53c7x0_memory_mapped ? \
1513 (unsigned int)readw((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) : \
1514 inw(NCR53c7x0_address_io + (address)))
1515 #else
1516 #define NCR53c7x0_read8(address) \
1517 (NCR53c7x0_memory_mapped ? \
1518 (unsigned int)readb((u32)NCR53c7x0_address_memory + (u32)(address)) : \
1519 inb(NCR53c7x0_address_io + (address)))
1520
1521 #define NCR53c7x0_read16(address) \
1522 (NCR53c7x0_memory_mapped ? \
1523 (unsigned int)readw((u32)NCR53c7x0_address_memory + (u32)(address)) : \
1524 inw(NCR53c7x0_address_io + (address)))
1525 #endif
1526 #define NCR53c7x0_read32(address) \
1527 (NCR53c7x0_memory_mapped ? \
1528 (unsigned int) readl((u32)NCR53c7x0_address_memory + (u32)(address)) : \
1529 inl(NCR53c7x0_address_io + (address)))
1530
1531 #ifdef BIG_ENDIAN
1532 /* If we are big-endian, then we are not Intel, so probably don't have
1533 * an i/o map as well as a memory map. So, let's assume memory mapped.
1534 * Also, I am having terrible problems trying to persuade the compiler
1535 * not to lay down code which does a read after write for these macros.
1536 * If you remove 'volatile' from writeb() and friends it is ok....
1537 */
1538
1539 #define NCR53c7x0_write8(address,value) \
1540 *(volatile unsigned char *) \
1541 ((u32)NCR53c7x0_address_memory + ((u32)(address)^3)) = (value)
1542
1543 #define NCR53c7x0_write16(address,value) \
1544 *(volatile unsigned short *) \
1545 ((u32)NCR53c7x0_address_memory + ((u32)(address)^2)) = (value)
1546
1547 #define NCR53c7x0_write32(address,value) \
1548 *(volatile unsigned long *) \
1549 ((u32)NCR53c7x0_address_memory + ((u32)(address))) = (value)
1550
1551 #else
1552
1553 #define NCR53c7x0_write8(address,value) \
1554 (NCR53c7x0_memory_mapped ? \
1555 ({writeb((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \
1556 outb((value), NCR53c7x0_address_io + (address)))
1557
1558 #define NCR53c7x0_write16(address,value) \
1559 (NCR53c7x0_memory_mapped ? \
1560 ({writew((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \
1561 outw((value), NCR53c7x0_address_io + (address)))
1562
1563 #define NCR53c7x0_write32(address,value) \
1564 (NCR53c7x0_memory_mapped ? \
1565 ({writel((value), (u32)NCR53c7x0_address_memory + (u32)(address)); mb();}) : \
1566 outl((value), NCR53c7x0_address_io + (address)))
1567
1568 #endif
1569
1570 /* Patch arbitrary 32 bit words in the script */
1571 #define patch_abs_32(script, offset, symbol, value) \
1572 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1573 (u32)); ++i) { \
1574 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1575 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1576 printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1577 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1578 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1579 (offset)]); \
1580 }
1581
1582 /* Patch read/write instruction immediate field */
1583 #define patch_abs_rwri_data(script, offset, symbol, value) \
1584 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1585 (u32)); ++i) \
1586 (script)[A_##symbol##_used[i] - (offset)] = \
1587 ((script)[A_##symbol##_used[i] - (offset)] & \
1588 ~DBC_RWRI_IMMEDIATE_MASK) | \
1589 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1590 DBC_RWRI_IMMEDIATE_MASK)
1591
1592 /* Patch transfer control instruction data field */
1593 #define patch_abs_tci_data(script, offset, symbol, value) \
1594 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1595 (u32)); ++i) \
1596 (script)[A_##symbol##_used[i] - (offset)] = \
1597 ((script)[A_##symbol##_used[i] - (offset)] & \
1598 ~DBC_TCI_DATA_MASK) | \
1599 (((value) << DBC_TCI_DATA_SHIFT) & \
1600 DBC_TCI_DATA_MASK)
1601
1602 /* Patch field in dsa structure (assignment should be +=?) */
1603 #define patch_dsa_32(dsa, symbol, word, value) \
1604 { \
1605 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32) \
1606 + (word)] = (value); \
1607 if (hostdata->options & OPTION_DEBUG_DSA) \
1608 printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
1609 #dsa, #symbol, hostdata->##symbol, \
1610 (word), (u32) (value)); \
1611 }
1612
1613 /* Paranoid people could use panic() here. */
1614 #define FATAL(host) shutdown((host));
1615
1616 #endif /* NCR53c710_C */
1617 #endif /* NCR53c710_H */
1618
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