1 /**************************************************************************
2 * Initio 9100 device driver for Linux.
3 *
4 * Copyright (c) 1994-1998 Initio Corporation
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * --------------------------------------------------------------------------
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions, and the following disclaimer,
28 * without modification, immediately at the beginning of the file.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
34 *
35 * Where this Software is combined with software released under the terms of
36 * the GNU Public License ("GPL") and the terms of the GPL would require the
37 * combined work to also be released under the terms of the GPL, the terms
38 * and conditions of this License will apply in addition to those of the
39 * GPL with the exception of any terms or conditions of this License that
40 * conflict with, or are expressly prohibited by, the GPL.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
46 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * SUCH DAMAGE.
53 *
54 **************************************************************************/
55
56 #include <linux/config.h>
57
58 #define ULONG unsigned long
59 #define USHORT unsigned short
60 #define UCHAR unsigned char
61 #define BYTE unsigned char
62 #define WORD unsigned short
63 #define DWORD unsigned long
64 #define UBYTE unsigned char
65 #define UWORD unsigned short
66 #define UDWORD unsigned long
67 #ifdef ALPHA
68 #define U32 unsigned int
69 #else
70 #define U32 unsigned long
71 #endif
72
73 #ifndef NULL
74 #define NULL 0 /* zero */
75 #endif
76 #ifndef TRUE
77 #define TRUE (1) /* boolean true */
78 #endif
79 #ifndef FALSE
80 #define FALSE (0) /* boolean false */
81 #endif
82 #ifndef FAILURE
83 #define FAILURE (-1)
84 #endif
85
86 #define TOTAL_SG_ENTRY 32
87 #define MAX_SUPPORTED_ADAPTERS 8
88 #define MAX_OFFSET 15
89 #define MAX_TARGETS 16
90
91 #define INI_VENDOR_ID 0x1101 /* Initio's PCI vendor ID */
92 #define I950_DEVICE_ID 0x9500 /* Initio's inic-950 product ID */
93 #define I940_DEVICE_ID 0x9400 /* Initio's inic-940 product ID */
94 #define I935_DEVICE_ID 0x9401 /* Initio's inic-935 product ID */
95
96 #define _I91USCSI_H
97
98 typedef struct {
99 unsigned short base;
100 unsigned short vec;
101 } i91u_config;
102
103 /***************************************/
104 /* Tulip Configuration Register Set */
105 /***************************************/
106 #define TUL_PVID 0x00 /* Vendor ID */
107 #define TUL_PDID 0x02 /* Device ID */
108 #define TUL_PCMD 0x04 /* Command */
109 #define TUL_PSTUS 0x06 /* Status */
110 #define TUL_PRID 0x08 /* Revision number */
111 #define TUL_PPI 0x09 /* Programming interface */
112 #define TUL_PSC 0x0A /* Sub Class */
113 #define TUL_PBC 0x0B /* Base Class */
114 #define TUL_PCLS 0x0C /* Cache line size */
115 #define TUL_PLTR 0x0D /* Latency timer */
116 #define TUL_PHDT 0x0E /* Header type */
117 #define TUL_PBIST 0x0F /* BIST */
118 #define TUL_PBAD 0x10 /* Base address */
119 #define TUL_PBAD1 0x14 /* Base address */
120 #define TUL_PBAD2 0x18 /* Base address */
121 #define TUL_PBAD3 0x1C /* Base address */
122 #define TUL_PBAD4 0x20 /* Base address */
123 #define TUL_PBAD5 0x24 /* Base address */
124 #define TUL_PRSVD 0x28 /* Reserved */
125 #define TUL_PRSVD1 0x2C /* Reserved */
126 #define TUL_PRAD 0x30 /* Expansion ROM base address */
127 #define TUL_PRSVD2 0x34 /* Reserved */
128 #define TUL_PRSVD3 0x38 /* Reserved */
129 #define TUL_PINTL 0x3C /* Interrupt line */
130 #define TUL_PINTP 0x3D /* Interrupt pin */
131 #define TUL_PIGNT 0x3E /* MIN_GNT */
132 #define TUL_PMGNT 0x3F /* MAX_GNT */
133
134 /************************/
135 /* Jasmin Register Set */
136 /************************/
137 #define TUL_HACFG0 0x40 /* H/A Configuration Register 0 */
138 #define TUL_HACFG1 0x41 /* H/A Configuration Register 1 */
139 #define TUL_HACFG2 0x42 /* H/A Configuration Register 2 */
140
141 #define TUL_SDCFG0 0x44 /* SCSI Device Configuration 0 */
142 #define TUL_SDCFG1 0x45 /* SCSI Device Configuration 1 */
143 #define TUL_SDCFG2 0x46 /* SCSI Device Configuration 2 */
144 #define TUL_SDCFG3 0x47 /* SCSI Device Configuration 3 */
145
146 #define TUL_GINTS 0x50 /* Global Interrupt Status Register */
147 #define TUL_GIMSK 0x52 /* Global Interrupt MASK Register */
148 #define TUL_GCTRL 0x54 /* Global Control Register */
149 #define TUL_GCTRL_EEPROM_BIT 0x04
150 #define TUL_GCTRL1 0x55 /* Global Control Register */
151 #define TUL_DMACFG 0x5B /* DMA configuration */
152 #define TUL_NVRAM 0x5D /* Non-volatile RAM port */
153
154 #define TUL_SCnt0 0x80 /* 00 R/W Transfer Counter Low */
155 #define TUL_SCnt1 0x81 /* 01 R/W Transfer Counter Mid */
156 #define TUL_SCnt2 0x82 /* 02 R/W Transfer Count High */
157 #define TUL_SFifoCnt 0x83 /* 03 R FIFO counter */
158 #define TUL_SIntEnable 0x84 /* 03 W Interrupt enble */
159 #define TUL_SInt 0x84 /* 04 R Interrupt Register */
160 #define TUL_SCtrl0 0x85 /* 05 W Control 0 */
161 #define TUL_SStatus0 0x85 /* 05 R Status 0 */
162 #define TUL_SCtrl1 0x86 /* 06 W Control 1 */
163 #define TUL_SStatus1 0x86 /* 06 R Status 1 */
164 #define TUL_SConfig 0x87 /* 07 W Configuration */
165 #define TUL_SStatus2 0x87 /* 07 R Status 2 */
166 #define TUL_SPeriod 0x88 /* 08 W Sync. Transfer Period & Offset */
167 #define TUL_SOffset 0x88 /* 08 R Offset */
168 #define TUL_SScsiId 0x89 /* 09 W SCSI ID */
169 #define TUL_SBusId 0x89 /* 09 R SCSI BUS ID */
170 #define TUL_STimeOut 0x8A /* 0A W Sel/Resel Time Out Register */
171 #define TUL_SIdent 0x8A /* 0A R Identify Message Register */
172 #define TUL_SAvail 0x8A /* 0A R Availiable Counter Register */
173 #define TUL_SData 0x8B /* 0B R/W SCSI data in/out */
174 #define TUL_SFifo 0x8C /* 0C R/W FIFO */
175 #define TUL_SSignal 0x90 /* 10 R/W SCSI signal in/out */
176 #define TUL_SCmd 0x91 /* 11 R/W Command */
177 #define TUL_STest0 0x92 /* 12 R/W Test0 */
178 #define TUL_STest1 0x93 /* 13 R/W Test1 */
179 #define TUL_SCFG1 0x94 /* 14 R/W Configuration */
180
181 #define TUL_XAddH 0xC0 /*DMA Transfer Physical Address */
182 #define TUL_XAddW 0xC8 /*DMA Current Transfer Physical Address */
183 #define TUL_XCntH 0xD0 /*DMA Transfer Counter */
184 #define TUL_XCntW 0xD4 /*DMA Current Transfer Counter */
185 #define TUL_XCmd 0xD8 /*DMA Command Register */
186 #define TUL_Int 0xDC /*Interrupt Register */
187 #define TUL_XStatus 0xDD /*DMA status Register */
188 #define TUL_Mask 0xE0 /*Interrupt Mask Register */
189 #define TUL_XCtrl 0xE4 /*DMA Control Register */
190 #define TUL_XCtrl1 0xE5 /*DMA Control Register 1 */
191 #define TUL_XFifo 0xE8 /*DMA FIFO */
192
193 #define TUL_WCtrl 0xF7 /*Bus master wait state control */
194 #define TUL_DCtrl 0xFB /*DMA delay control */
195
196 /*----------------------------------------------------------------------*/
197 /* bit definition for Command register of Configuration Space Header */
198 /*----------------------------------------------------------------------*/
199 #define BUSMS 0x04 /* BUS MASTER Enable */
200 #define IOSPA 0x01 /* IO Space Enable */
201
202 /*----------------------------------------------------------------------*/
203 /* Command Codes of Tulip SCSI Command register */
204 /*----------------------------------------------------------------------*/
205 #define TSC_EN_RESEL 0x80 /* Enable Reselection */
206 #define TSC_CMD_COMP 0x84 /* Command Complete Sequence */
207 #define TSC_SEL 0x01 /* Select Without ATN Sequence */
208 #define TSC_SEL_ATN 0x11 /* Select With ATN Sequence */
209 #define TSC_SEL_ATN_DMA 0x51 /* Select With ATN Sequence with DMA */
210 #define TSC_SEL_ATN3 0x31 /* Select With ATN3 Sequence */
211 #define TSC_SEL_ATNSTOP 0x12 /* Select With ATN and Stop Sequence */
212 #define TSC_SELATNSTOP 0x1E /* Select With ATN and Stop Sequence */
213
214 #define TSC_SEL_ATN_DIRECT_IN 0x95 /* Select With ATN Sequence */
215 #define TSC_SEL_ATN_DIRECT_OUT 0x15 /* Select With ATN Sequence */
216 #define TSC_SEL_ATN3_DIRECT_IN 0xB5 /* Select With ATN3 Sequence */
217 #define TSC_SEL_ATN3_DIRECT_OUT 0x35 /* Select With ATN3 Sequence */
218 #define TSC_XF_DMA_OUT_DIRECT 0x06 /* DMA Xfer Infomation out */
219 #define TSC_XF_DMA_IN_DIRECT 0x86 /* DMA Xfer Infomation in */
220
221 #define TSC_XF_DMA_OUT 0x43 /* DMA Xfer Infomation out */
222 #define TSC_XF_DMA_IN 0xC3 /* DMA Xfer Infomation in */
223 #define TSC_XF_FIFO_OUT 0x03 /* FIFO Xfer Infomation out */
224 #define TSC_XF_FIFO_IN 0x83 /* FIFO Xfer Infomation in */
225
226 #define TSC_MSG_ACCEPT 0x0F /* Message Accept */
227
228 /*----------------------------------------------------------------------*/
229 /* bit definition for Tulip SCSI Control 0 Register */
230 /*----------------------------------------------------------------------*/
231 #define TSC_RST_SEQ 0x20 /* Reset sequence counter */
232 #define TSC_FLUSH_FIFO 0x10 /* Flush FIFO */
233 #define TSC_ABT_CMD 0x04 /* Abort command (sequence) */
234 #define TSC_RST_CHIP 0x02 /* Reset SCSI Chip */
235 #define TSC_RST_BUS 0x01 /* Reset SCSI Bus */
236
237 /*----------------------------------------------------------------------*/
238 /* bit definition for Tulip SCSI Control 1 Register */
239 /*----------------------------------------------------------------------*/
240 #define TSC_EN_SCAM 0x80 /* Enable SCAM */
241 #define TSC_TIMER 0x40 /* Select timeout unit */
242 #define TSC_EN_SCSI2 0x20 /* SCSI-2 mode */
243 #define TSC_PWDN 0x10 /* Power down mode */
244 #define TSC_WIDE_CPU 0x08 /* Wide CPU */
245 #define TSC_HW_RESELECT 0x04 /* Enable HW reselect */
246 #define TSC_EN_BUS_OUT 0x02 /* Enable SCSI data bus out latch */
247 #define TSC_EN_BUS_IN 0x01 /* Enable SCSI data bus in latch */
248
249 /*----------------------------------------------------------------------*/
250 /* bit definition for Tulip SCSI Configuration Register */
251 /*----------------------------------------------------------------------*/
252 #define TSC_EN_LATCH 0x80 /* Enable phase latch */
253 #define TSC_INITIATOR 0x40 /* Initiator mode */
254 #define TSC_EN_SCSI_PAR 0x20 /* Enable SCSI parity */
255 #define TSC_DMA_8BIT 0x10 /* Alternate dma 8-bits mode */
256 #define TSC_DMA_16BIT 0x08 /* Alternate dma 16-bits mode */
257 #define TSC_EN_WDACK 0x04 /* Enable DACK while wide SCSI xfer */
258 #define TSC_ALT_PERIOD 0x02 /* Alternate sync period mode */
259 #define TSC_DIS_SCSIRST 0x01 /* Disable SCSI bus reset us */
260
261 #define TSC_INITDEFAULT (TSC_INITIATOR | TSC_EN_LATCH | TSC_ALT_PERIOD | TSC_DIS_SCSIRST)
262
263 #define TSC_WIDE_SCSI 0x80 /* Enable Wide SCSI */
264
265 /*----------------------------------------------------------------------*/
266 /* bit definition for Tulip SCSI signal Register */
267 /*----------------------------------------------------------------------*/
268 #define TSC_RST_ACK 0x00 /* Release ACK signal */
269 #define TSC_RST_ATN 0x00 /* Release ATN signal */
270 #define TSC_RST_BSY 0x00 /* Release BSY signal */
271
272 #define TSC_SET_ACK 0x40 /* ACK signal */
273 #define TSC_SET_ATN 0x08 /* ATN signal */
274
275 #define TSC_REQI 0x80 /* REQ signal */
276 #define TSC_ACKI 0x40 /* ACK signal */
277 #define TSC_BSYI 0x20 /* BSY signal */
278 #define TSC_SELI 0x10 /* SEL signal */
279 #define TSC_ATNI 0x08 /* ATN signal */
280 #define TSC_MSGI 0x04 /* MSG signal */
281 #define TSC_CDI 0x02 /* C/D signal */
282 #define TSC_IOI 0x01 /* I/O signal */
283
284
285 /*----------------------------------------------------------------------*/
286 /* bit definition for Tulip SCSI Status 0 Register */
287 /*----------------------------------------------------------------------*/
288 #define TSS_INT_PENDING 0x80 /* Interrupt pending */
289 #define TSS_SEQ_ACTIVE 0x40 /* Sequencer active */
290 #define TSS_XFER_CNT 0x20 /* Transfer counter zero */
291 #define TSS_FIFO_EMPTY 0x10 /* FIFO empty */
292 #define TSS_PAR_ERROR 0x08 /* SCSI parity error */
293 #define TSS_PH_MASK 0x07 /* SCSI phase mask */
294
295 /*----------------------------------------------------------------------*/
296 /* bit definition for Tulip SCSI Status 1 Register */
297 /*----------------------------------------------------------------------*/
298 #define TSS_STATUS_RCV 0x08 /* Status received */
299 #define TSS_MSG_SEND 0x40 /* Message sent */
300 #define TSS_CMD_PH_CMP 0x20 /* command phase done */
301 #define TSS_DATA_PH_CMP 0x10 /* Data phase done */
302 #define TSS_STATUS_SEND 0x08 /* Status sent */
303 #define TSS_XFER_CMP 0x04 /* Transfer completed */
304 #define TSS_SEL_CMP 0x02 /* Selection completed */
305 #define TSS_ARB_CMP 0x01 /* Arbitration completed */
306
307 /*----------------------------------------------------------------------*/
308 /* bit definition for Tulip SCSI Status 2 Register */
309 /*----------------------------------------------------------------------*/
310 #define TSS_CMD_ABTED 0x80 /* Command aborted */
311 #define TSS_OFFSET_0 0x40 /* Offset counter zero */
312 #define TSS_FIFO_FULL 0x20 /* FIFO full */
313 #define TSS_TIMEOUT_0 0x10 /* Timeout counter zero */
314 #define TSS_BUSY_RLS 0x08 /* Busy release */
315 #define TSS_PH_MISMATCH 0x04 /* Phase mismatch */
316 #define TSS_SCSI_BUS_EN 0x02 /* SCSI data bus enable */
317 #define TSS_SCSIRST 0x01 /* SCSI bus reset in progress */
318
319 /*----------------------------------------------------------------------*/
320 /* bit definition for Tulip SCSI Interrupt Register */
321 /*----------------------------------------------------------------------*/
322 #define TSS_RESEL_INT 0x80 /* Reselected interrupt */
323 #define TSS_SEL_TIMEOUT 0x40 /* Selected/reselected timeout */
324 #define TSS_BUS_SERV 0x20
325 #define TSS_SCSIRST_INT 0x10 /* SCSI bus reset detected */
326 #define TSS_DISC_INT 0x08 /* Disconnected interrupt */
327 #define TSS_SEL_INT 0x04 /* Select interrupt */
328 #define TSS_SCAM_SEL 0x02 /* SCAM selected */
329 #define TSS_FUNC_COMP 0x01
330
331 /*----------------------------------------------------------------------*/
332 /* SCSI Phase Codes. */
333 /*----------------------------------------------------------------------*/
334 #define DATA_OUT 0
335 #define DATA_IN 1 /* 4 */
336 #define CMD_OUT 2
337 #define STATUS_IN 3 /* 6 */
338 #define MSG_OUT 6 /* 3 */
339 #define MSG_IN 7
340
341
342
343 /*----------------------------------------------------------------------*/
344 /* Command Codes of Tulip xfer Command register */
345 /*----------------------------------------------------------------------*/
346 #define TAX_X_FORC 0x02
347 #define TAX_X_ABT 0x04
348 #define TAX_X_CLR_FIFO 0x08
349
350 #define TAX_X_IN 0x21
351 #define TAX_X_OUT 0x01
352 #define TAX_SG_IN 0xA1
353 #define TAX_SG_OUT 0x81
354
355 /*----------------------------------------------------------------------*/
356 /* Tulip Interrupt Register */
357 /*----------------------------------------------------------------------*/
358 #define XCMP 0x01
359 #define FCMP 0x02
360 #define XABT 0x04
361 #define XERR 0x08
362 #define SCMP 0x10
363 #define IPEND 0x80
364
365 /*----------------------------------------------------------------------*/
366 /* Tulip DMA Status Register */
367 /*----------------------------------------------------------------------*/
368 #define XPEND 0x01 /* Transfer pending */
369 #define FEMPTY 0x02 /* FIFO empty */
370
371
372
373 /*----------------------------------------------------------------------*/
374 /* bit definition for TUL_GCTRL */
375 /*----------------------------------------------------------------------*/
376 #define EXTSG 0x80
377 #define EXTAD 0x60
378 #define SEG4K 0x08
379 #define EEPRG 0x04
380 #define MRMUL 0x02
381
382 /*----------------------------------------------------------------------*/
383 /* bit definition for TUL_NVRAM */
384 /*----------------------------------------------------------------------*/
385 #define SE2CS 0x08
386 #define SE2CLK 0x04
387 #define SE2DO 0x02
388 #define SE2DI 0x01
389
390
391 /************************************************************************/
392 /* Scatter-Gather Element Structure */
393 /************************************************************************/
394 typedef struct SG_Struc {
395 U32 SG_Ptr; /* Data Pointer */
396 U32 SG_Len; /* Data Length */
397 } SG;
398
399 /***********************************************************************
400 SCSI Control Block
401 ************************************************************************/
402 typedef struct Scsi_Ctrl_Blk {
403 struct Scsi_Ctrl_Blk *SCB_NxtScb;
404 UBYTE SCB_Status; /*4 */
405 UBYTE SCB_NxtStat; /*5 */
406 UBYTE SCB_Mode; /*6 */
407 UBYTE SCB_Msgin; /*7 SCB_Res0 */
408 UWORD SCB_SGIdx; /*8 */
409 UWORD SCB_SGMax; /*A */
410 #ifdef ALPHA
411 U32 SCB_Reserved[2]; /*C */
412 #else
413 U32 SCB_Reserved[3]; /*C */
414 #endif
415
416 U32 SCB_XferLen; /*18 Current xfer len */
417 U32 SCB_TotXLen; /*1C Total xfer len */
418 U32 SCB_PAddr; /*20 SCB phy. Addr. */
419
420 UBYTE SCB_Opcode; /*24 SCB command code */
421 UBYTE SCB_Flags; /*25 SCB Flags */
422 UBYTE SCB_Target; /*26 Target Id */
423 UBYTE SCB_Lun; /*27 Lun */
424 U32 SCB_BufPtr; /*28 Data Buffer Pointer */
425 U32 SCB_BufLen; /*2C Data Allocation Length */
426 UBYTE SCB_SGLen; /*30 SG list # */
427 UBYTE SCB_SenseLen; /*31 Sense Allocation Length */
428 UBYTE SCB_HaStat; /*32 */
429 UBYTE SCB_TaStat; /*33 */
430 UBYTE SCB_CDBLen; /*34 CDB Length */
431 UBYTE SCB_Ident; /*35 Identify */
432 UBYTE SCB_TagMsg; /*36 Tag Message */
433 UBYTE SCB_TagId; /*37 Queue Tag */
434 UBYTE SCB_CDB[12]; /*38 */
435 U32 SCB_SGPAddr; /*44 SG List/Sense Buf phy. Addr. */
436 U32 SCB_SensePtr; /*48 Sense data pointer */
437 void (*SCB_Post) (BYTE *, BYTE *); /*4C POST routine */
438 unsigned char *SCB_Srb; /*50 SRB Pointer */
439 SG SCB_SGList[TOTAL_SG_ENTRY]; /*54 Start of SG list */
440 } SCB;
441
442 /* Bit Definition for SCB_Status */
443 #define SCB_RENT 0x01
444 #define SCB_PEND 0x02
445 #define SCB_CONTIG 0x04 /* Contigent Allegiance */
446 #define SCB_SELECT 0x08
447 #define SCB_BUSY 0x10
448 #define SCB_DONE 0x20
449
450
451 /* Opcodes of SCB_Opcode */
452 #define ExecSCSI 0x1
453 #define BusDevRst 0x2
454 #define AbortCmd 0x3
455
456
457 /* Bit Definition for SCB_Mode */
458 #define SCM_RSENS 0x01 /* request sense mode */
459
460
461 /* Bit Definition for SCB_Flags */
462 #define SCF_DONE 0x01
463 #define SCF_POST 0x02
464 #define SCF_SENSE 0x04
465 #define SCF_DIR 0x18
466 #define SCF_NO_DCHK 0x00
467 #define SCF_DIN 0x08
468 #define SCF_DOUT 0x10
469 #define SCF_NO_XF 0x18
470 #define SCF_WR_VF 0x20 /* Write verify turn on */
471 #define SCF_POLL 0x40
472 #define SCF_SG 0x80
473
474 /* Error Codes for SCB_HaStat */
475 #define HOST_SEL_TOUT 0x11
476 #define HOST_DO_DU 0x12
477 #define HOST_BUS_FREE 0x13
478 #define HOST_BAD_PHAS 0x14
479 #define HOST_INV_CMD 0x16
480 #define HOST_ABORTED 0x1A /* 07/21/98 */
481 #define HOST_SCSI_RST 0x1B
482 #define HOST_DEV_RST 0x1C
483
484 /* Error Codes for SCB_TaStat */
485 #define TARGET_CHKCOND 0x02
486 #define TARGET_BUSY 0x08
487 #define QUEUE_FULL 0x28
488
489 /* SCSI MESSAGE */
490 #define MSG_COMP 0x00
491 #define MSG_EXTEND 0x01
492 #define MSG_SDP 0x02
493 #define MSG_RESTORE 0x03
494 #define MSG_DISC 0x04
495 #define MSG_IDE 0x05
496 #define MSG_ABORT 0x06
497 #define MSG_REJ 0x07
498 #define MSG_NOP 0x08
499 #define MSG_PARITY 0x09
500 #define MSG_LINK_COMP 0x0A
501 #define MSG_LINK_FLAG 0x0B
502 #define MSG_DEVRST 0x0C
503 #define MSG_ABORT_TAG 0x0D
504
505 /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
506 #define MSG_STAG 0x20
507 #define MSG_HTAG 0x21
508 #define MSG_OTAG 0x22
509
510 #define MSG_IGNOREWIDE 0x23
511
512 #define MSG_IDENT 0x80
513
514 /***********************************************************************
515 Target Device Control Structure
516 **********************************************************************/
517
518 typedef struct Tar_Ctrl_Struc {
519 UWORD TCS_Flags; /* 0 */
520 UBYTE TCS_JS_Period; /* 2 */
521 UBYTE TCS_SConfig0; /* 3 */
522
523 UWORD TCS_DrvFlags; /* 4 */
524 UBYTE TCS_DrvHead; /* 6 */
525 UBYTE TCS_DrvSector; /* 7 */
526 } TCS;
527
528 /***********************************************************************
529 Target Device Control Structure
530 **********************************************************************/
531
532 /* Bit Definition for TCF_Flags */
533 #define TCF_SCSI_RATE 0x0007
534 #define TCF_EN_DISC 0x0008
535 #define TCF_NO_SYNC_NEGO 0x0010
536 #define TCF_NO_WDTR 0x0020
537 #define TCF_EN_255 0x0040
538 #define TCF_EN_START 0x0080
539 #define TCF_WDTR_DONE 0x0100
540 #define TCF_SYNC_DONE 0x0200
541 #define TCF_BUSY 0x0400
542
543
544 /* Bit Definition for TCF_DrvFlags */
545 #define TCF_DRV_BUSY 0x01 /* Indicate target busy(driver) */
546 #define TCF_DRV_EN_TAG 0x0800
547 #define TCF_DRV_255_63 0x0400
548
549 typedef struct I91u_Adpt_Struc {
550 UWORD ADPT_BIOS; /* 0 */
551 UWORD ADPT_BASE; /* 1 */
552 UBYTE ADPT_Bus; /* 2 */
553 UBYTE ADPT_Device; /* 3 */
554 UBYTE ADPT_INTR; /* 4 */
555 } INI_ADPT_STRUCT;
556
557
558 /***********************************************************************
559 Host Adapter Control Structure
560 ************************************************************************/
561 typedef struct Ha_Ctrl_Struc {
562 UWORD HCS_Base; /* 00 */
563 UWORD HCS_BIOS; /* 02 */
564 UBYTE HCS_Intr; /* 04 */
565 UBYTE HCS_SCSI_ID; /* 05 */
566 UBYTE HCS_MaxTar; /* 06 */
567 UBYTE HCS_NumScbs; /* 07 */
568
569 UBYTE HCS_Flags; /* 08 */
570 UBYTE HCS_Index; /* 09 */
571 UBYTE HCS_HaId; /* 0A */
572 UBYTE HCS_Config; /* 0B */
573 UWORD HCS_IdMask; /* 0C */
574 UBYTE HCS_Semaph; /* 0E */
575 UBYTE HCS_Phase; /* 0F */
576 UBYTE HCS_JSStatus0; /* 10 */
577 UBYTE HCS_JSInt; /* 11 */
578 UBYTE HCS_JSStatus1; /* 12 */
579 UBYTE HCS_SConf1; /* 13 */
580
581 UBYTE HCS_Msg[8]; /* 14 */
582 SCB *HCS_NxtAvail; /* 1C */
583 SCB *HCS_Scb; /* 20 */
584 SCB *HCS_ScbEnd; /* 24 */
585 SCB *HCS_NxtPend; /* 28 */
586 SCB *HCS_NxtContig; /* 2C */
587 SCB *HCS_ActScb; /* 30 */
588 TCS *HCS_ActTcs; /* 34 */
589
590 SCB *HCS_FirstAvail; /* 38 */
591 SCB *HCS_LastAvail; /* 3C */
592 SCB *HCS_FirstPend; /* 40 */
593 SCB *HCS_LastPend; /* 44 */
594 SCB *HCS_FirstBusy; /* 48 */
595 SCB *HCS_LastBusy; /* 4C */
596 SCB *HCS_FirstDone; /* 50 */
597 SCB *HCS_LastDone; /* 54 */
598 UBYTE HCS_MaxTags[16]; /* 58 */
599 UBYTE HCS_ActTags[16]; /* 68 */
600 TCS HCS_Tcs[MAX_TARGETS]; /* 78 */
601 ULONG pSRB_head; /* SRB save queue header */
602 ULONG pSRB_tail; /* SRB save queue tail */
603 #if LINUX_VERSION_CODE >= CVT_LINUX_VERSION(2,1,95)
604 spinlock_t HCS_AvailLock;
605 spinlock_t HCS_SemaphLock;
606 spinlock_t pSRB_lock; /* SRB queue lock */
607 #endif
608 } HCS;
609
610 /* Bit Definition for HCB_Config */
611 #define HCC_SCSI_RESET 0x01
612 #define HCC_EN_PAR 0x02
613 #define HCC_ACT_TERM1 0x04
614 #define HCC_ACT_TERM2 0x08
615 #define HCC_AUTO_TERM 0x10
616 #define HCC_EN_PWR 0x80
617
618 /* Bit Definition for HCB_Flags */
619 #define HCF_EXPECT_DISC 0x01
620 #define HCF_EXPECT_SELECT 0x02
621 #define HCF_EXPECT_RESET 0x10
622 #define HCF_EXPECT_DONE_DISC 0x20
623
624 /******************************************************************
625 Serial EEProm
626 *******************************************************************/
627
628 typedef struct _NVRAM_SCSI { /* SCSI channel configuration */
629 UCHAR NVM_ChSCSIID; /* 0Ch -> Channel SCSI ID */
630 UCHAR NVM_ChConfig1; /* 0Dh -> Channel config 1 */
631 UCHAR NVM_ChConfig2; /* 0Eh -> Channel config 2 */
632 UCHAR NVM_NumOfTarg; /* 0Fh -> Number of SCSI target */
633 /* SCSI target configuration */
634 UCHAR NVM_Targ0Config; /* 10h -> Target 0 configuration */
635 UCHAR NVM_Targ1Config; /* 11h -> Target 1 configuration */
636 UCHAR NVM_Targ2Config; /* 12h -> Target 2 configuration */
637 UCHAR NVM_Targ3Config; /* 13h -> Target 3 configuration */
638 UCHAR NVM_Targ4Config; /* 14h -> Target 4 configuration */
639 UCHAR NVM_Targ5Config; /* 15h -> Target 5 configuration */
640 UCHAR NVM_Targ6Config; /* 16h -> Target 6 configuration */
641 UCHAR NVM_Targ7Config; /* 17h -> Target 7 configuration */
642 UCHAR NVM_Targ8Config; /* 18h -> Target 8 configuration */
643 UCHAR NVM_Targ9Config; /* 19h -> Target 9 configuration */
644 UCHAR NVM_TargAConfig; /* 1Ah -> Target A configuration */
645 UCHAR NVM_TargBConfig; /* 1Bh -> Target B configuration */
646 UCHAR NVM_TargCConfig; /* 1Ch -> Target C configuration */
647 UCHAR NVM_TargDConfig; /* 1Dh -> Target D configuration */
648 UCHAR NVM_TargEConfig; /* 1Eh -> Target E configuration */
649 UCHAR NVM_TargFConfig; /* 1Fh -> Target F configuration */
650 } NVRAM_SCSI;
651
652 typedef struct _NVRAM {
653 /*----------header ---------------*/
654 USHORT NVM_Signature; /* 0,1: Signature */
655 UCHAR NVM_Size; /* 2: Size of data structure */
656 UCHAR NVM_Revision; /* 3: Revision of data structure */
657 /* ----Host Adapter Structure ---- */
658 UCHAR NVM_ModelByte0; /* 4: Model number (byte 0) */
659 UCHAR NVM_ModelByte1; /* 5: Model number (byte 1) */
660 UCHAR NVM_ModelInfo; /* 6: Model information */
661 UCHAR NVM_NumOfCh; /* 7: Number of SCSI channel */
662 UCHAR NVM_BIOSConfig1; /* 8: BIOS configuration 1 */
663 UCHAR NVM_BIOSConfig2; /* 9: BIOS configuration 2 */
664 UCHAR NVM_HAConfig1; /* A: Hoat adapter configuration 1 */
665 UCHAR NVM_HAConfig2; /* B: Hoat adapter configuration 2 */
666 NVRAM_SCSI NVM_SCSIInfo[2];
667 UCHAR NVM_reserved[10];
668 /* ---------- CheckSum ---------- */
669 USHORT NVM_CheckSum; /* 0x3E, 0x3F: Checksum of NVRam */
670 } NVRAM, *PNVRAM;
671
672 /* Bios Configuration for nvram->BIOSConfig1 */
673 #define NBC1_ENABLE 0x01 /* BIOS enable */
674 #define NBC1_8DRIVE 0x02 /* Support more than 2 drives */
675 #define NBC1_REMOVABLE 0x04 /* Support removable drive */
676 #define NBC1_INT19 0x08 /* Intercept int 19h */
677 #define NBC1_BIOSSCAN 0x10 /* Dynamic BIOS scan */
678 #define NBC1_LUNSUPPORT 0x40 /* Support LUN */
679
680 /* HA Configuration Byte 1 */
681 #define NHC1_BOOTIDMASK 0x0F /* Boot ID number */
682 #define NHC1_LUNMASK 0x70 /* Boot LUN number */
683 #define NHC1_CHANMASK 0x80 /* Boot Channel number */
684
685 /* Bit definition for nvram->SCSIconfig1 */
686 #define NCC1_BUSRESET 0x01 /* Reset SCSI bus at power up */
687 #define NCC1_PARITYCHK 0x02 /* SCSI parity enable */
688 #define NCC1_ACTTERM1 0x04 /* Enable active terminator 1 */
689 #define NCC1_ACTTERM2 0x08 /* Enable active terminator 2 */
690 #define NCC1_AUTOTERM 0x10 /* Enable auto terminator */
691 #define NCC1_PWRMGR 0x80 /* Enable power management */
692
693 /* Bit definition for SCSI Target configuration byte */
694 #define NTC_DISCONNECT 0x08 /* Enable SCSI disconnect */
695 #define NTC_SYNC 0x10 /* SYNC_NEGO */
696 #define NTC_NO_WDTR 0x20 /* SYNC_NEGO */
697 #define NTC_1GIGA 0x40 /* 255 head / 63 sectors (64/32) */
698 #define NTC_SPINUP 0x80 /* Start disk drive */
699
700 /* Default NVRam values */
701 #define INI_SIGNATURE 0xC925
702 #define NBC1_DEFAULT (NBC1_ENABLE)
703 #define NCC1_DEFAULT (NCC1_BUSRESET | NCC1_AUTOTERM | NCC1_PARITYCHK)
704 #define NTC_DEFAULT (NTC_NO_WDTR | NTC_1GIGA | NTC_DISCONNECT)
705
706 /* SCSI related definition */
707 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
708 #define DISC_ALLOW 0xC0 /* Disconnect is allowed */
709 #define SCSICMD_RequestSense 0x03
710
711
712 /*----------------------------------------------------------------------*/
713 /* PCI */
714 /*----------------------------------------------------------------------*/
715 #define PCI_FUNCTION_ID 0xB1
716 #define PCI_BIOS_PRESENT 0x01
717 #define FIND_PCI_DEVICE 0x02
718 #define FIND_PCI_CLASS_CODE 0x03
719 #define GENERATE_SPECIAL_CYCLE 0x06
720 #define READ_CONFIG_BYTE 0x08
721 #define READ_CONFIG_WORD 0x09
722 #define READ_CONFIG_DWORD 0x0A
723 #define WRITE_CONFIG_BYTE 0x0B
724 #define WRITE_CONFIG_WORD 0x0C
725 #define WRITE_CONFIG_DWORD 0x0D
726
727 #define SUCCESSFUL 0x00
728 #define FUNC_NOT_SUPPORTED 0x81
729 #define BAD_VENDOR_ID 0x83 /* Bad vendor ID */
730 #define DEVICE_NOT_FOUND 0x86 /* PCI device not found */
731 #define BAD_REGISTER_NUMBER 0x87
732
733 #define MAX_PCI_DEVICES 21 /* Maximum devices supportted */
734
735 #define MAX_PCI_CHANL 4
736
737 typedef struct _BIOS32_ENTRY_STRUCTURE {
738 DWORD Signatures; /* Should be "_32_" */
739 DWORD BIOS32Entry; /* 32-bit physical address */
740 BYTE Revision; /* Revision level, should be 0 */
741 BYTE Length; /* Multiply of 16, should be 1 */
742 BYTE CheckSum; /* Checksum of whole structure */
743 BYTE Reserved[5]; /* Reserved */
744 } BIOS32_ENTRY_STRUCTURE, *PBIOS32_ENTRY_STRUCTURE;
745
746 typedef struct {
747 union {
748 unsigned int eax;
749 struct {
750 unsigned short ax;
751 } word;
752 struct {
753 unsigned char al;
754 unsigned char ah;
755 } byte;
756 } eax;
757 union {
758 unsigned int ebx;
759 struct {
760 unsigned short bx;
761 } word;
762 struct {
763 unsigned char bl;
764 unsigned char bh;
765 } byte;
766 } ebx;
767 union {
768 unsigned int ecx;
769 struct {
770 unsigned short cx;
771 } word;
772 struct {
773 unsigned char cl;
774 unsigned char ch;
775 } byte;
776 } ecx;
777 union {
778 unsigned int edx;
779 struct {
780 unsigned short dx;
781 } word;
782 struct {
783 unsigned char dl;
784 unsigned char dh;
785 } byte;
786 } edx;
787 union {
788 unsigned int edi;
789 struct {
790 unsigned short di;
791 } word;
792 } edi;
793 union {
794 unsigned int esi;
795 struct {
796 unsigned short si;
797 } word;
798 } esi;
799 } REGS;
800
801 typedef union { /* Union define for mechanism 1 */
802 struct {
803 unsigned char RegNum;
804 unsigned char FcnNum:3;
805 unsigned char DeviceNum:5;
806 unsigned char BusNum;
807 unsigned char Reserved:7;
808 unsigned char Enable:1;
809 } sConfigAdr;
810 unsigned long lConfigAdr;
811 } CONFIG_ADR;
812
813 typedef union { /* Union define for mechanism 2 */
814 struct {
815 unsigned char RegNum;
816 unsigned char DeviceNum;
817 unsigned short Reserved;
818 } sHostAdr;
819 unsigned long lHostAdr;
820 } HOST_ADR;
821
822 typedef struct _HCSinfo {
823 ULONG base;
824 UCHAR vec;
825 UCHAR bios; /* High byte of BIOS address */
826 USHORT BaseAndBios; /* high byte: pHcsInfo->bios,low byte:pHcsInfo->base */
827 } HCSINFO;
828
829 #define TUL_RD(x,y) (UCHAR)(inb( (int)((ULONG)(x+y)) ))
830 #define TUL_RDLONG(x,y) (ULONG)(inl((int)((ULONG)(x+y)) ))
831 #define TUL_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
832 #define TUL_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
833 #define TUL_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
834
835 #define SCSI_ABORT_SNOOZE 0
836 #define SCSI_ABORT_SUCCESS 1
837 #define SCSI_ABORT_PENDING 2
838 #define SCSI_ABORT_BUSY 3
839 #define SCSI_ABORT_NOT_RUNNING 4
840 #define SCSI_ABORT_ERROR 5
841
842 #define SCSI_RESET_SNOOZE 0
843 #define SCSI_RESET_PUNT 1
844 #define SCSI_RESET_SUCCESS 2
845 #define SCSI_RESET_PENDING 3
846 #define SCSI_RESET_WAKEUP 4
847 #define SCSI_RESET_NOT_RUNNING 5
848 #define SCSI_RESET_ERROR 6
849
850 #define SCSI_RESET_SYNCHRONOUS 0x01
851 #define SCSI_RESET_ASYNCHRONOUS 0x02
852 #define SCSI_RESET_SUGGEST_BUS_RESET 0x04
853 #define SCSI_RESET_SUGGEST_HOST_RESET 0x08
854
855 #define SCSI_RESET_BUS_RESET 0x100
856 #define SCSI_RESET_HOST_RESET 0x200
857 #define SCSI_RESET_ACTION 0xff
858
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