1 /**************************************************************************
2 * Initio A100 device driver for Linux.
3 *
4 * Copyright (c) 1994-1998 Initio Corporation
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 * --------------------------------------------------------------------------
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions, and the following disclaimer,
28 * without modification, immediately at the beginning of the file.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
34 *
35 * Where this Software is combined with software released under the terms of
36 * the GNU Public License ("GPL") and the terms of the GPL would require the
37 * combined work to also be released under the terms of the GPL, the terms
38 * and conditions of this License will apply in addition to those of the
39 * GPL with the exception of any terms or conditions of this License that
40 * conflict with, or are expressly prohibited by, the GPL.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
46 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
52 * SUCH DAMAGE.
53 *
54 **************************************************************************
55 *
56 * Module: inia100.h
57 * Description: INI-A100U2W LINUX device driver header
58 * Revision History:
59 * 06/18/98 HL, Initial production Version 1.02
60 * 12/19/98 bv, Use spinlocks for 2.1.95 and up
61 ****************************************************************************/
62
63 #ifndef CVT_LINUX_VERSION
64 #define CVT_LINUX_VERSION(V,P,S) (((V) * 65536) + ((P) * 256) + (S))
65 #endif
66
67 #ifndef LINUX_VERSION_CODE
68 #include <linux/version.h>
69 #endif
70
71 #include "sd.h"
72
73 extern int inia100_detect(Scsi_Host_Template *);
74 extern int inia100_release(struct Scsi_Host *);
75 extern int inia100_command(Scsi_Cmnd *);
76 extern int inia100_queue(Scsi_Cmnd *, void (*done) (Scsi_Cmnd *));
77 extern int inia100_abort(Scsi_Cmnd *);
78 extern int inia100_reset(Scsi_Cmnd *, unsigned int);
79
80 extern int inia100_biosparam(Scsi_Disk *, kdev_t, int *); /*for linux v2.0 */
81
82 #define inia100_REVID "Initio INI-A100U2W SCSI device driver; Revision: 1.02c"
83
84 #define INIA100 { \
85 next: NULL, \
86 module: NULL, \
87 proc_name: "INIA100", \
88 proc_info: NULL, \
89 name: inia100_REVID, \
90 detect: inia100_detect, \
91 release: inia100_release, \
92 info: NULL, \
93 command: inia100_command, \
94 queuecommand: inia100_queue, \
95 eh_strategy_handler: NULL, \
96 eh_abort_handler: NULL, \
97 eh_device_reset_handler: NULL, \
98 eh_bus_reset_handler: NULL, \
99 eh_host_reset_handler: NULL, \
100 abort: inia100_abort, \
101 reset: inia100_reset, \
102 slave_attach: NULL, \
103 bios_param: inia100_biosparam, \
104 can_queue: 1, \
105 this_id: 1, \
106 sg_tablesize: SG_ALL, \
107 cmd_per_lun: 1, \
108 present: 0, \
109 unchecked_isa_dma: 0, \
110 use_clustering: ENABLE_CLUSTERING, \
111 use_new_eh_code: 0 \
112 }
113
114 #define VIRT_TO_BUS(i) (unsigned int) virt_to_bus((void *)(i))
115 #define ULONG unsigned long
116 #define PVOID void *
117 #define USHORT unsigned short
118 #define UCHAR unsigned char
119 #define BYTE unsigned char
120 #define WORD unsigned short
121 #define DWORD unsigned long
122 #define UBYTE unsigned char
123 #define UWORD unsigned short
124 #define UDWORD unsigned long
125 #ifdef ALPHA
126 #define U32 unsigned int
127 #else
128 #define U32 unsigned long
129 #endif
130
131 #ifndef NULL
132 #define NULL 0 /* zero */
133 #endif
134 #ifndef TRUE
135 #define TRUE (1) /* boolean true */
136 #endif
137 #ifndef FALSE
138 #define FALSE (0) /* boolean false */
139 #endif
140 #ifndef FAILURE
141 #define FAILURE (-1)
142 #endif
143 #if 1
144 #define ORC_MAXQUEUE 245
145 #else
146 #define ORC_MAXQUEUE 25
147 #endif
148
149 #define TOTAL_SG_ENTRY 32
150 #define MAX_TARGETS 16
151 #define IMAX_CDB 15
152 #define SENSE_SIZE 14
153 #define MAX_SUPPORTED_ADAPTERS 4
154 #define SUCCESSFUL 0x00
155
156 #define I920_DEVICE_ID 0x0002 /* Initio's inic-950 product ID */
157
158 /************************************************************************/
159 /* Scatter-Gather Element Structure */
160 /************************************************************************/
161 typedef struct ORC_SG_Struc {
162 U32 SG_Ptr; /* Data Pointer */
163 U32 SG_Len; /* Data Length */
164 } ORC_SG;
165
166
167 /* SCSI related definition */
168 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
169 #define DISC_ALLOW 0xC0 /* Disconnect is allowed */
170
171
172 #define ORC_OFFSET_SCB 16
173 #define ORC_MAX_SCBS 250
174 #define MAX_CHANNELS 2
175 #define MAX_ESCB_ELE 64
176 #define TCF_DRV_255_63 0x0400
177
178 /********************************************************/
179 /* Orchid Configuration Register Set */
180 /********************************************************/
181 #define ORC_PVID 0x00 /* Vendor ID */
182 #define ORC_VENDOR_ID 0x1101 /* Orchid vendor ID */
183 #define ORC_PDID 0x02 /* Device ID */
184 #define ORC_DEVICE_ID 0x1060 /* Orchid device ID */
185 #define ORC_COMMAND 0x04 /* Command */
186 #define BUSMS 0x04 /* BUS MASTER Enable */
187 #define IOSPA 0x01 /* IO Space Enable */
188 #define ORC_STATUS 0x06 /* Status register */
189 #define ORC_REVISION 0x08 /* Revision number */
190 #define ORC_BASE 0x10 /* Base address */
191 #define ORC_BIOS 0x50 /* Expansion ROM base address */
192 #define ORC_INT_NUM 0x3C /* Interrupt line */
193 #define ORC_INT_PIN 0x3D /* Interrupt pin */
194
195 /********************************************************/
196 /* Orchid Host Command Set */
197 /********************************************************/
198 #define ORC_CMD_NOP 0x00 /* Host command - NOP */
199 #define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */
200 #define ORC_CMD_ECHO 0x02 /* Host command - ECHO */
201 #define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */
202 #define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */
203 #define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */
204 #define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */
205 #define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */
206
207 /********************************************************/
208 /* Orchid Register Set */
209 /********************************************************/
210 #define ORC_GINTS 0xA0 /* Global Interrupt Status */
211 #define QINT 0x04 /* Reply Queue Interrupt */
212 #define ORC_GIMSK 0xA1 /* Global Interrupt MASK */
213 #define MQINT 0x04 /* Mask Reply Queue Interrupt */
214 #define ORC_GCFG 0xA2 /* Global Configure */
215 #define EEPRG 0x01 /* Enable EEPROM programming */
216 #define ORC_GSTAT 0xA3 /* Global status */
217 #define WIDEBUS 0x10 /* Wide SCSI Devices connected */
218 #define ORC_HDATA 0xA4 /* Host Data */
219 #define ORC_HCTRL 0xA5 /* Host Control */
220 #define SCSIRST 0x80 /* SCSI bus reset */
221 #define HDO 0x40 /* Host data out */
222 #define HOSTSTOP 0x02 /* Host stop RISC engine */
223 #define DEVRST 0x01 /* Device reset */
224 #define ORC_HSTUS 0xA6 /* Host Status */
225 #define HDI 0x02 /* Host data in */
226 #define RREADY 0x01 /* RISC engine is ready to receive */
227 #define ORC_NVRAM 0xA7 /* Nvram port address */
228 #define SE2CS 0x008
229 #define SE2CLK 0x004
230 #define SE2DO 0x002
231 #define SE2DI 0x001
232 #define ORC_PQUEUE 0xA8 /* Posting queue FIFO */
233 #define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */
234 #define ORC_RQUEUE 0xAA /* Reply queue FIFO */
235 #define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */
236 #define ORC_FWBASEADR 0xAC /* Firmware base address */
237
238 #define ORC_EBIOSADR0 0xB0 /* External Bios address */
239 #define ORC_EBIOSADR1 0xB1 /* External Bios address */
240 #define ORC_EBIOSADR2 0xB2 /* External Bios address */
241 #define ORC_EBIOSDATA 0xB3 /* External Bios address */
242
243 #define ORC_SCBSIZE 0xB7 /* SCB size register */
244 #define ORC_SCBBASE0 0xB8 /* SCB base address 0 */
245 #define ORC_SCBBASE1 0xBC /* SCB base address 1 */
246
247 #define ORC_RISCCTL 0xE0 /* RISC Control */
248 #define PRGMRST 0x002
249 #define DOWNLOAD 0x001
250 #define ORC_PRGMCTR0 0xE2 /* RISC program counter */
251 #define ORC_PRGMCTR1 0xE3 /* RISC program counter */
252 #define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */
253
254 typedef struct orc_extended_scb { /* Extended SCB */
255 ORC_SG ESCB_SGList[TOTAL_SG_ENTRY]; /*0 Start of SG list */
256 Scsi_Cmnd *SCB_Srb; /*50 SRB Pointer */
257 } ESCB;
258
259 /***********************************************************************
260 SCSI Control Block
261 ************************************************************************/
262 typedef struct orc_scb { /* Scsi_Ctrl_Blk */
263 UBYTE SCB_Opcode; /*00 SCB command code&residual */
264 UBYTE SCB_Flags; /*01 SCB Flags */
265 UBYTE SCB_Target; /*02 Target Id */
266 UBYTE SCB_Lun; /*03 Lun */
267 U32 SCB_Reserved0; /*04 Reserved for ORCHID must 0 */
268 U32 SCB_XferLen; /*08 Data Transfer Length */
269 U32 SCB_Reserved1; /*0C Reserved for ORCHID must 0 */
270 U32 SCB_SGLen; /*10 SG list # * 8 */
271 U32 SCB_SGPAddr; /*14 SG List Buf physical Addr */
272 U32 SCB_SGPAddrHigh; /*18 SG Buffer high physical Addr */
273 UBYTE SCB_HaStat; /*1C Host Status */
274 UBYTE SCB_TaStat; /*1D Target Status */
275 UBYTE SCB_Status; /*1E SCB status */
276 UBYTE SCB_Link; /*1F Link pointer, default 0xFF */
277 UBYTE SCB_SenseLen; /*20 Sense Allocation Length */
278 UBYTE SCB_CDBLen; /*21 CDB Length */
279 UBYTE SCB_Ident; /*22 Identify */
280 UBYTE SCB_TagMsg; /*23 Tag Message */
281 UBYTE SCB_CDB[IMAX_CDB]; /*24 SCSI CDBs */
282 UBYTE SCB_ScbIdx; /*3C Index for this ORCSCB */
283 U32 SCB_SensePAddr; /*34 Sense Buffer physical Addr */
284
285 ESCB *SCB_EScb; /*38 Extended SCB Pointer */
286 #ifndef ALPHA
287 UBYTE SCB_Reserved2[4]; /*3E Reserved for Driver use */
288 #endif
289 } ORC_SCB;
290
291 /* Opcodes of ORCSCB_Opcode */
292 #define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */
293 #define ORC_BUSDEVRST 0x01 /* SCSI Bus Device Reset */
294
295 /* Status of ORCSCB_Status */
296 #define ORCSCB_COMPLETE 0x00 /* SCB request completed */
297 #define ORCSCB_POST 0x01 /* SCB is posted by the HOST */
298
299 /* Bit Definition for ORCSCB_Flags */
300 #define SCF_DISINT 0x01 /* Disable HOST interrupt */
301 #define SCF_DIR 0x18 /* Direction bits */
302 #define SCF_NO_DCHK 0x00 /* Direction determined by SCSI */
303 #define SCF_DIN 0x08 /* From Target to Initiator */
304 #define SCF_DOUT 0x10 /* From Initiator to Target */
305 #define SCF_NO_XF 0x18 /* No data transfer */
306 #define SCF_POLL 0x40
307
308 /* Error Codes for ORCSCB_HaStat */
309 #define HOST_SEL_TOUT 0x11
310 #define HOST_DO_DU 0x12
311 #define HOST_BUS_FREE 0x13
312 #define HOST_BAD_PHAS 0x14
313 #define HOST_INV_CMD 0x16
314 #define HOST_SCSI_RST 0x1B
315 #define HOST_DEV_RST 0x1C
316
317
318 /* Error Codes for ORCSCB_TaStat */
319 #define TARGET_CHK_COND 0x02
320 #define TARGET_BUSY 0x08
321 #define TARGET_TAG_FULL 0x28
322
323
324 /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
325 #define MSG_STAG 0x20
326 #define MSG_HTAG 0x21
327 #define MSG_OTAG 0x22
328
329 #define MSG_IGNOREWIDE 0x23
330
331 #define MSG_IDENT 0x80
332 #define MSG_DISC 0x40 /* Disconnect allowed */
333
334
335 /* SCSI MESSAGE */
336 #define MSG_EXTEND 0x01
337 #define MSG_SDP 0x02
338 #define MSG_ABORT 0x06
339 #define MSG_REJ 0x07
340 #define MSG_NOP 0x08
341 #define MSG_PARITY 0x09
342 #define MSG_DEVRST 0x0C
343 #define MSG_STAG 0x20
344
345 /***********************************************************************
346 Target Device Control Structure
347 **********************************************************************/
348
349 typedef struct ORC_Tar_Ctrl_Struc {
350 UBYTE TCS_DrvDASD; /* 6 */
351 UBYTE TCS_DrvSCSI; /* 7 */
352 UBYTE TCS_DrvHead; /* 8 */
353 UWORD TCS_DrvFlags; /* 4 */
354 UBYTE TCS_DrvSector; /* 7 */
355 } ORC_TCS, *PORC_TCS;
356
357 /* Bit Definition for TCF_DrvFlags */
358 #define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */
359 #define TCS_DF_NOSCSI_SUPT 0x40 /* Suppress OS/2 SCSI Mgr support */
360
361
362 /***********************************************************************
363 Host Adapter Control Structure
364 ************************************************************************/
365 typedef struct ORC_Ha_Ctrl_Struc {
366 USHORT HCS_Base; /* 00 */
367 UBYTE HCS_Index; /* 02 */
368 UBYTE HCS_Intr; /* 04 */
369 UBYTE HCS_SCSI_ID; /* 06 H/A SCSI ID */
370 UBYTE HCS_BIOS; /* 07 BIOS configuration */
371
372 UBYTE HCS_Flags; /* 0B */
373 UBYTE HCS_HAConfig1; /* 1B SCSI0MAXTags */
374 UBYTE HCS_MaxTar; /* 1B SCSI0MAXTags */
375
376 USHORT HCS_Units; /* Number of units this adapter */
377 USHORT HCS_AFlags; /* Adapter info. defined flags */
378 ULONG HCS_Timeout; /* Adapter timeout value */
379 PVOID HCS_virScbArray; /* 28 Virtual Pointer to SCB array */
380 U32 HCS_physScbArray; /* Scb Physical address */
381 PVOID HCS_virEscbArray; /* Virtual pointer to ESCB Scatter list */
382 U32 HCS_physEscbArray; /* scatter list Physical address */
383 UBYTE TargetFlag[16]; /* 30 target configuration, TCF_EN_TAG */
384 UBYTE MaximumTags[16]; /* 40 ORC_MAX_SCBS */
385 UBYTE ActiveTags[16][16]; /* 50 */
386 ORC_TCS HCS_Tcs[16]; /* 28 */
387 U32 BitAllocFlag[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */
388 spinlock_t BitAllocFlagLock;
389 Scsi_Cmnd *pSRB_head;
390 Scsi_Cmnd *pSRB_tail;
391 spinlock_t pSRB_lock;
392 } ORC_HCS;
393
394 /* Bit Definition for HCS_Flags */
395
396 #define HCF_SCSI_RESET 0x01 /* SCSI BUS RESET */
397 #define HCF_PARITY 0x02 /* parity card */
398 #define HCF_LVDS 0x10 /* parity card */
399
400 /* Bit Definition for TargetFlag */
401
402 #define TCF_EN_255 0x08
403 #define TCF_EN_TAG 0x10
404 #define TCF_BUSY 0x20
405 #define TCF_DISCONNECT 0x40
406 #define TCF_SPIN_UP 0x80
407
408 /* Bit Definition for HCS_AFlags */
409 #define HCS_AF_IGNORE 0x01 /* Adapter ignore */
410 #define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */
411 #define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */
412
413
414 /*---------------------------------------*/
415 /* TimeOut for RESET to complete (30s) */
416 /* */
417 /* After a RESET the drive is checked */
418 /* every 200ms. */
419 /*---------------------------------------*/
420 #define DELAYED_RESET_MAX (30*1000L)
421 #define DELAYED_RESET_INTERVAL 200L
422
423 /*----------------------------------------------*/
424 /* TimeOut for IRQ from last interrupt (5s) */
425 /*----------------------------------------------*/
426 #define IRQ_TIMEOUT_INTERVAL (5*1000L)
427
428 /*----------------------------------------------*/
429 /* Retry Delay interval (200ms) */
430 /*----------------------------------------------*/
431 #define DELAYED_RETRY_INTERVAL 200L
432
433 #define INQUIRY_SIZE 36
434 #define CAPACITY_SIZE 8
435 #define DEFAULT_SENSE_LEN 14
436
437 #define DEVICE_NOT_FOUND 0x86
438
439 /*----------------------------------------------*/
440 /* Definition for PCI device */
441 /*----------------------------------------------*/
442 #define MAX_PCI_DEVICES 21
443 #define MAX_PCI_BUSES 8
444
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