1 /*****************************************************************************/
2 /* ips.h -- driver for the IBM ServeRAID controller */
3 /* */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* */
6 /* Copyright (C) 1999 IBM Corporation */
7 /* */
8 /* This program is free software; you can redistribute it and/or modify */
9 /* it under the terms of the GNU General Public License as published by */
10 /* the Free Software Foundation; either version 2 of the License, or */
11 /* (at your option) any later version. */
12 /* */
13 /* This program is distributed in the hope that it will be useful, */
14 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
15 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
16 /* GNU General Public License for more details. */
17 /* */
18 /* NO WARRANTY */
19 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
20 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
21 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
22 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
23 /* solely responsible for determining the appropriateness of using and */
24 /* distributing the Program and assumes all risks associated with its */
25 /* exercise of rights under this Agreement, including but not limited to */
26 /* the risks and costs of program errors, damage to or loss of data, */
27 /* programs or equipment, and unavailability or interruption of operations. */
28 /* */
29 /* DISCLAIMER OF LIABILITY */
30 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
31 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
32 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
33 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
34 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
35 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
36 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
37 /* */
38 /* You should have received a copy of the GNU General Public License */
39 /* along with this program; if not, write to the Free Software */
40 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
41 /* */
42 /* Bugs/Comments/Suggestions should be mailed to: */
43 /* ipslinux@us.ibm.com */
44 /* */
45 /*****************************************************************************/
46
47 #ifndef _IPS_H_
48 #define _IPS_H_
49
50 #include <asm/uaccess.h>
51 #include <asm/io.h>
52
53 /* Prototypes */
54 extern int ips_detect(Scsi_Host_Template *);
55 extern int ips_release(struct Scsi_Host *);
56 extern int ips_eh_abort(Scsi_Cmnd *);
57 extern int ips_eh_reset(Scsi_Cmnd *);
58 extern int ips_queue(Scsi_Cmnd *, void (*) (Scsi_Cmnd *));
59 extern int ips_biosparam(Disk *, kdev_t, int *);
60 extern const char * ips_info(struct Scsi_Host *);
61 extern void do_ipsintr(int, void *, struct pt_regs *);
62
63 /*
64 * Some handy macros
65 */
66 #ifndef LinuxVersionCode
67 #define LinuxVersionCode(x,y,z) (((x)<<16)+((y)<<8)+(z))
68 #endif
69
70 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
71 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
72 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_COPPERHEAD_DEVICEID) && \
73 (ha->revision_id >= IPS_REVID_TROMBONE32) && \
74 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
75 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_COPPERHEAD_DEVICEID) && \
76 (ha->revision_id >= IPS_REVID_CLARINETP1) && \
77 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
78 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_MORPHEUS_DEVICEID)
79 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
80 (IPS_IS_TROMBONE(ha) && \
81 (ips_force_i2o))) ? 1 : 0)
82 #define IPS_USE_I2O_STATUS(ha) (IPS_IS_MORPHEUS(ha))
83 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
84 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
85 (ips_force_memio))) ? 1 : 0)
86
87 #ifndef VIRT_TO_BUS
88 #define VIRT_TO_BUS(x) (unsigned int)virt_to_bus((void *) x)
89 #endif
90
91 #ifndef UDELAY
92 #define UDELAY udelay
93 #endif
94
95 #ifndef MDELAY
96 #define MDELAY mdelay
97 #endif
98
99 #ifndef verify_area_20
100 #define verify_area_20(t,a,sz) (0) /* success */
101 #endif
102
103 #ifndef PUT_USER
104 #define PUT_USER put_user
105 #endif
106
107 #ifndef __PUT_USER
108 #define __PUT_USER __put_user
109 #endif
110
111 #ifndef GET_USER
112 #define GET_USER get_user
113 #endif
114
115 #ifndef __GET_USER
116 #define __GET_USER __get_user
117 #endif
118
119 /*
120 * Lock macros
121 */
122 #define IPS_SCB_LOCK(cpu_flags) spin_lock_irqsave(&ha->scb_lock, cpu_flags)
123 #define IPS_SCB_UNLOCK(cpu_flags) spin_unlock_irqrestore(&ha->scb_lock, cpu_flags)
124 #define IPS_QUEUE_LOCK(queue) spin_lock_irqsave(&(queue)->lock, (queue)->cpu_flags)
125 #define IPS_QUEUE_UNLOCK(queue) spin_unlock_irqrestore(&(queue)->lock, (queue)->cpu_flags)
126 #define IPS_HA_LOCK(cpu_flags) spin_lock_irqsave(&ha->ips_lock, cpu_flags)
127 #define IPS_HA_UNLOCK(cpu_flags) spin_unlock_irqrestore(&ha->ips_lock, cpu_flags)
128
129 /*
130 * Adapter address map equates
131 */
132 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
133 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
134 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
135 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
136 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
137 #define IPS_REG_SQER 0x28 /* Status Q End Reg */
138 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
139 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
140 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
141 #define IPS_REG_CBSP 0x07 /* CBSP register */
142 #define IPS_REG_FLAP 0x18 /* Flash address port */
143 #define IPS_REG_FLDP 0x1C /* Flash data port */
144 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
145 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
146 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
147 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
148 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
149 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
150 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
151 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
152
153 /*
154 * Adapter register bit equates
155 */
156 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
157 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
158 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
159 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
160 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
161 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
162 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
163 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
164 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
165 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
166 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
167 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
168 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
169 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
170
171 /*
172 * Adapter Command ID Equates
173 */
174 #define IPS_CMD_GET_LD_INFO 0x19
175 #define IPS_CMD_GET_SUBSYS 0x40
176 #define IPS_CMD_READ_CONF 0x38
177 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
178 #define IPS_CMD_READ 0x02
179 #define IPS_CMD_WRITE 0x03
180 #define IPS_CMD_FFDC 0xD7
181 #define IPS_CMD_ENQUIRY 0x05
182 #define IPS_CMD_FLUSH 0x0A
183 #define IPS_CMD_READ_SG 0x82
184 #define IPS_CMD_WRITE_SG 0x83
185 #define IPS_CMD_DCDB 0x04
186 #define IPS_CMD_DCDB_SG 0x84
187 #define IPS_CMD_CONFIG_SYNC 0x58
188 #define IPS_CMD_ERROR_TABLE 0x17
189
190 /*
191 * Adapter Equates
192 */
193 #define IPS_CSL 0xFF
194 #define IPS_POCL 0x30
195 #define IPS_NORM_STATE 0x00
196 #define IPS_MAX_ADAPTERS 16
197 #define IPS_MAX_IOCTL 1
198 #define IPS_MAX_IOCTL_QUEUE 8
199 #define IPS_MAX_QUEUE 128
200 #define IPS_BLKSIZE 512
201 #define IPS_MAX_SG 17
202 #define IPS_MAX_LD 8
203 #define IPS_MAX_CHANNELS 4
204 #define IPS_MAX_TARGETS 15
205 #define IPS_MAX_CHUNKS 16
206 #define IPS_MAX_CMDS 128
207 #define IPS_MAX_XFER 0x10000
208 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
209 #define IPS_MAX_POST_BYTES 0x02
210 #define IPS_MAX_CONFIG_BYTES 0x02
211 #define IPS_GOOD_POST_STATUS 0x80
212 #define IPS_SEM_TIMEOUT 2000
213 #define IPS_IOCTL_COMMAND 0x0D
214 #define IPS_IOCTL_NEW_COMMAND 0x81
215 #define IPS_INTR_ON 0
216 #define IPS_INTR_IORL 1
217 #define IPS_INTR_HAL 2
218 #define IPS_ADAPTER_ID 0xF
219 #define IPS_VENDORID 0x1014
220 #define IPS_COPPERHEAD_DEVICEID 0x002E
221 #define IPS_MORPHEUS_DEVICEID 0x01BD
222 #define IPS_IOCTL_SIZE 8192
223 #define IPS_STATUS_SIZE 4
224 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
225 #define IPS_MEMMAP_SIZE 128
226 #define IPS_ONE_MSEC 1
227 #define IPS_ONE_SEC 1000
228
229 /*
230 * Geometry Settings
231 */
232 #define IPS_COMP_HEADS 128
233 #define IPS_COMP_SECTORS 32
234 #define IPS_NORM_HEADS 254
235 #define IPS_NORM_SECTORS 63
236
237 /*
238 * Adapter Basic Status Codes
239 */
240 #define IPS_BASIC_STATUS_MASK 0xFF
241 #define IPS_GSC_STATUS_MASK 0x0F
242 #define IPS_CMD_SUCCESS 0x00
243 #define IPS_CMD_RECOVERED_ERROR 0x01
244 #define IPS_INVAL_OPCO 0x03
245 #define IPS_INVAL_CMD_BLK 0x04
246 #define IPS_INVAL_PARM_BLK 0x05
247 #define IPS_BUSY 0x08
248 #define IPS_CMD_CMPLT_WERROR 0x0C
249 #define IPS_LD_ERROR 0x0D
250 #define IPS_CMD_TIMEOUT 0x0E
251 #define IPS_PHYS_DRV_ERROR 0x0F
252
253 /*
254 * Adapter Extended Status Equates
255 */
256 #define IPS_ERR_SEL_TO 0xF0
257 #define IPS_ERR_OU_RUN 0xF2
258 #define IPS_ERR_HOST_RESET 0xF7
259 #define IPS_ERR_DEV_RESET 0xF8
260 #define IPS_ERR_RECOVERY 0xFC
261 #define IPS_ERR_CKCOND 0xFF
262
263 /*
264 * Operating System Defines
265 */
266 #define IPS_OS_WINDOWS_NT 0x01
267 #define IPS_OS_NETWARE 0x02
268 #define IPS_OS_OPENSERVER 0x03
269 #define IPS_OS_UNIXWARE 0x04
270 #define IPS_OS_SOLARIS 0x05
271 #define IPS_OS_OS2 0x06
272 #define IPS_OS_LINUX 0x07
273 #define IPS_OS_FREEBSD 0x08
274
275 /*
276 * Adapter Revision ID's
277 */
278 #define IPS_REVID_SERVERAID 0x02
279 #define IPS_REVID_NAVAJO 0x03
280 #define IPS_REVID_SERVERAID2 0x04
281 #define IPS_REVID_CLARINETP1 0x05
282 #define IPS_REVID_CLARINETP2 0x07
283 #define IPS_REVID_CLARINETP3 0x0D
284 #define IPS_REVID_TROMBONE32 0x0F
285 #define IPS_REVID_TROMBONE64 0x10
286
287 /*
288 * Adapter Command/Status Packet Definitions
289 */
290 #define IPS_SUCCESS 0x01 /* Successfully completed */
291 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
292 #define IPS_FAILURE 0x04 /* Completed with Error */
293
294 /*
295 * Logical Drive Equates
296 */
297 #define IPS_LD_OFFLINE 0x02
298 #define IPS_LD_OKAY 0x03
299 #define IPS_LD_FREE 0x00
300 #define IPS_LD_SYS 0x06
301 #define IPS_LD_CRS 0x24
302
303 /*
304 * DCDB Table Equates
305 */
306 #define IPS_NO_DISCONNECT 0x00
307 #define IPS_DISCONNECT_ALLOWED 0x80
308 #define IPS_NO_AUTO_REQSEN 0x40
309 #define IPS_DATA_NONE 0x00
310 #define IPS_DATA_UNK 0x00
311 #define IPS_DATA_IN 0x01
312 #define IPS_DATA_OUT 0x02
313 #define IPS_TRANSFER64K 0x08
314 #define IPS_NOTIMEOUT 0x00
315 #define IPS_TIMEOUT10 0x10
316 #define IPS_TIMEOUT60 0x20
317 #define IPS_TIMEOUT20M 0x30
318
319 /*
320 * Host adapter Flags (bit numbers)
321 */
322 #define IPS_IN_INTR 0
323 #define IPS_IN_ABORT 1
324 #define IPS_IN_RESET 2
325
326 /*
327 * SCB Flags
328 */
329 #define IPS_SCB_ACTIVE 0x00001
330 #define IPS_SCB_WAITING 0x00002
331
332 /*
333 * Passthru stuff
334 */
335 #define IPS_COPPUSRCMD (('C'<<8) | 65)
336 #define IPS_COPPIOCCMD (('C'<<8) | 66)
337 #define IPS_NUMCTRLS (('C'<<8) | 68)
338 #define IPS_CTRLINFO (('C'<<8) | 69)
339 #define IPS_FLASHBIOS (('C'<<8) | 70)
340
341 /* time oriented stuff */
342 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
343 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
344
345 #define IPS_SECS_MIN 60
346 #define IPS_SECS_HOUR 3600
347 #define IPS_SECS_8HOURS 28800
348 #define IPS_SECS_DAY 86400
349 #define IPS_DAYS_NORMAL_YEAR 365
350 #define IPS_DAYS_LEAP_YEAR 366
351 #define IPS_EPOCH_YEAR 1970
352
353 /*
354 * Scsi_Host Template
355 */
356 #if LINUX_VERSION_CODE < LinuxVersionCode(2,3,27)
357 #define IPS { \
358 next : NULL, \
359 module : NULL, \
360 proc_info : NULL, \
361 proc_dir : NULL, \
362 name : NULL, \
363 detect : ips_detect, \
364 release : ips_release, \
365 info : ips_info, \
366 command : NULL, \
367 queuecommand : ips_queue, \
368 eh_strategy_handler : NULL, \
369 eh_abort_handler : ips_eh_abort, \
370 eh_device_reset_handler : NULL, \
371 eh_bus_reset_handler : NULL, \
372 eh_host_reset_handler : ips_eh_reset, \
373 abort : NULL, \
374 reset : NULL, \
375 slave_attach : NULL, \
376 bios_param : ips_biosparam, \
377 can_queue : 0, \
378 this_id: -1, \
379 sg_tablesize : IPS_MAX_SG, \
380 cmd_per_lun: 16, \
381 present : 0, \
382 unchecked_isa_dma : 0, \
383 use_clustering : ENABLE_CLUSTERING, \
384 use_new_eh_code : 1 \
385 }
386 #else
387 #define IPS { \
388 next : NULL, \
389 module : NULL, \
390 proc_info : NULL, \
391 name : NULL, \
392 detect : ips_detect, \
393 release : ips_release, \
394 info : ips_info, \
395 command : NULL, \
396 queuecommand : ips_queue, \
397 eh_strategy_handler : NULL, \
398 eh_abort_handler : ips_eh_abort, \
399 eh_device_reset_handler : NULL, \
400 eh_bus_reset_handler : NULL, \
401 eh_host_reset_handler : ips_eh_reset, \
402 abort : NULL, \
403 reset : NULL, \
404 slave_attach : NULL, \
405 bios_param : ips_biosparam, \
406 can_queue : 0, \
407 this_id: -1, \
408 sg_tablesize : IPS_MAX_SG, \
409 cmd_per_lun: 16, \
410 present : 0, \
411 unchecked_isa_dma : 0, \
412 use_clustering : ENABLE_CLUSTERING, \
413 use_new_eh_code : 1 \
414 }
415 #endif
416
417 /*
418 * IBM PCI Raid Command Formats
419 */
420 typedef struct {
421 u8 op_code;
422 u8 command_id;
423 u8 log_drv;
424 u8 sg_count;
425 u32 lba;
426 u32 sg_addr;
427 u16 sector_count;
428 u16 reserved;
429 u32 ccsar;
430 u32 cccr;
431 } IPS_IO_CMD, *PIPS_IO_CMD;
432
433 typedef struct {
434 u8 op_code;
435 u8 command_id;
436 u16 reserved;
437 u32 reserved2;
438 u32 buffer_addr;
439 u32 reserved3;
440 u32 ccsar;
441 u32 cccr;
442 } IPS_LD_CMD, *PIPS_LD_CMD;
443
444 typedef struct {
445 u8 op_code;
446 u8 command_id;
447 u8 reserved;
448 u8 reserved2;
449 u32 reserved3;
450 u32 buffer_addr;
451 u32 reserved4;
452 } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
453
454 typedef struct {
455 u8 op_code;
456 u8 command_id;
457 u16 reserved;
458 u32 reserved2;
459 u32 dcdb_address;
460 u32 reserved3;
461 u32 ccsar;
462 u32 cccr;
463 } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
464
465 typedef struct {
466 u8 op_code;
467 u8 command_id;
468 u8 channel;
469 u8 source_target;
470 u32 reserved;
471 u32 reserved2;
472 u32 reserved3;
473 u32 ccsar;
474 u32 cccr;
475 } IPS_CS_CMD, *PIPS_CS_CMD;
476
477 typedef struct {
478 u8 op_code;
479 u8 command_id;
480 u8 log_drv;
481 u8 control;
482 u32 reserved;
483 u32 reserved2;
484 u32 reserved3;
485 u32 ccsar;
486 u32 cccr;
487 } IPS_US_CMD, *PIPS_US_CMD;
488
489 typedef struct {
490 u8 op_code;
491 u8 command_id;
492 u8 reserved;
493 u8 state;
494 u32 reserved2;
495 u32 reserved3;
496 u32 reserved4;
497 u32 ccsar;
498 u32 cccr;
499 } IPS_FC_CMD, *PIPS_FC_CMD;
500
501 typedef struct {
502 u8 op_code;
503 u8 command_id;
504 u8 reserved;
505 u8 desc;
506 u32 reserved2;
507 u32 buffer_addr;
508 u32 reserved3;
509 u32 ccsar;
510 u32 cccr;
511 } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
512
513 typedef struct {
514 u8 op_code;
515 u8 command_id;
516 u8 page;
517 u8 write;
518 u32 reserved;
519 u32 buffer_addr;
520 u32 reserved2;
521 u32 ccsar;
522 u32 cccr;
523 } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
524
525 typedef struct {
526 u8 op_code;
527 u8 command_id;
528 u8 reset_count;
529 u8 reset_type;
530 u8 second;
531 u8 minute;
532 u8 hour;
533 u8 day;
534 u8 reserved1[4];
535 u8 month;
536 u8 yearH;
537 u8 yearL;
538 u8 reserved2;
539 } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
540
541 typedef union {
542 IPS_IO_CMD basic_io;
543 IPS_LD_CMD logical_info;
544 IPS_IOCTL_CMD ioctl_info;
545 IPS_DCDB_CMD dcdb;
546 IPS_CS_CMD config_sync;
547 IPS_US_CMD unlock_stripe;
548 IPS_FC_CMD flush_cache;
549 IPS_STATUS_CMD status;
550 IPS_NVRAM_CMD nvram;
551 IPS_FFDC_CMD ffdc;
552 } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
553
554 typedef struct {
555 u8 logical_id;
556 u8 reserved;
557 u8 raid_level;
558 u8 state;
559 u32 sector_count;
560 } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
561
562 typedef struct {
563 u8 no_of_log_drive;
564 u8 reserved[3];
565 IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
566 } IPS_LD_INFO, *PIPS_LD_INFO;
567
568 typedef struct {
569 u8 device_address;
570 u8 cmd_attribute;
571 u16 transfer_length;
572 u32 buffer_pointer;
573 u8 cdb_length;
574 u8 sense_length;
575 u8 sg_count;
576 u8 reserved;
577 u8 scsi_cdb[12];
578 u8 sense_info[64];
579 u8 scsi_status;
580 u8 reserved2[3];
581 } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
582
583 typedef union {
584 struct {
585 volatile u8 reserved;
586 volatile u8 command_id;
587 volatile u8 basic_status;
588 volatile u8 extended_status;
589 } fields;
590
591 volatile u32 value;
592 } IPS_STATUS, *PIPS_STATUS;
593
594 typedef struct {
595 IPS_STATUS status[IPS_MAX_CMDS + 1];
596 volatile PIPS_STATUS p_status_start;
597 volatile PIPS_STATUS p_status_end;
598 volatile PIPS_STATUS p_status_tail;
599 volatile u32 hw_status_start;
600 volatile u32 hw_status_tail;
601 IPS_LD_INFO logical_drive_info;
602 } IPS_ADAPTER, *PIPS_ADAPTER;
603
604 typedef struct {
605 u8 ucLogDriveCount;
606 u8 ucMiscFlag;
607 u8 ucSLTFlag;
608 u8 ucBSTFlag;
609 u8 ucPwrChgCnt;
610 u8 ucWrongAdrCnt;
611 u8 ucUnidentCnt;
612 u8 ucNVramDevChgCnt;
613 u8 CodeBlkVersion[8];
614 u8 BootBlkVersion[8];
615 u32 ulDriveSize[IPS_MAX_LD];
616 u8 ucConcurrentCmdCount;
617 u8 ucMaxPhysicalDevices;
618 u16 usFlashRepgmCount;
619 u8 ucDefunctDiskCount;
620 u8 ucRebuildFlag;
621 u8 ucOfflineLogDrvCount;
622 u8 ucCriticalDrvCount;
623 u16 usConfigUpdateCount;
624 u8 ucBlkFlag;
625 u8 reserved;
626 u16 usAddrDeadDisk[IPS_MAX_CHANNELS * IPS_MAX_TARGETS];
627 } IPS_ENQ, *PIPS_ENQ;
628
629 typedef struct {
630 u8 ucInitiator;
631 u8 ucParameters;
632 u8 ucMiscFlag;
633 u8 ucState;
634 u32 ulBlockCount;
635 u8 ucDeviceId[28];
636 } IPS_DEVSTATE, *PIPS_DEVSTATE;
637
638 typedef struct {
639 u8 ucChn;
640 u8 ucTgt;
641 u16 ucReserved;
642 u32 ulStartSect;
643 u32 ulNoOfSects;
644 } IPS_CHUNK, *PIPS_CHUNK;
645
646 typedef struct {
647 u16 ucUserField;
648 u8 ucState;
649 u8 ucRaidCacheParam;
650 u8 ucNoOfChunkUnits;
651 u8 ucStripeSize;
652 u8 ucParams;
653 u8 ucReserved;
654 u32 ulLogDrvSize;
655 IPS_CHUNK chunk[IPS_MAX_CHUNKS];
656 } IPS_LD, *PIPS_LD;
657
658 typedef struct {
659 u8 board_disc[8];
660 u8 processor[8];
661 u8 ucNoChanType;
662 u8 ucNoHostIntType;
663 u8 ucCompression;
664 u8 ucNvramType;
665 u32 ulNvramSize;
666 } IPS_HARDWARE, *PIPS_HARDWARE;
667
668 typedef struct {
669 u8 ucLogDriveCount;
670 u8 ucDateD;
671 u8 ucDateM;
672 u8 ucDateY;
673 u8 init_id[4];
674 u8 host_id[12];
675 u8 time_sign[8];
676
677 struct {
678 u32 usCfgDrvUpdateCnt:16;
679 u32 ConcurDrvStartCnt:4;
680 u32 StartupDelay:4;
681 u32 auto_rearrange:1;
682 u32 cd_boot:1;
683 u32 cluster:1;
684 u32 reserved:5;
685 } UserOpt;
686
687 u16 user_field;
688 u8 ucRebuildRate;
689 u8 ucReserve;
690 IPS_HARDWARE hardware_disc;
691 IPS_LD logical_drive[IPS_MAX_LD];
692 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
693 u8 reserved[512];
694
695 } IPS_CONF, *PIPS_CONF;
696
697 typedef struct {
698 u32 signature;
699 u8 reserved;
700 u8 adapter_slot;
701 u16 adapter_type;
702 u8 bios_high[4];
703 u8 bios_low[4];
704 u16 reserved2;
705 u8 reserved3;
706 u8 operating_system;
707 u8 driver_high[4];
708 u8 driver_low[4];
709 u8 reserved4[100];
710 } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
711
712 typedef struct _IPS_SUBSYS {
713 u32 param[128];
714 } IPS_SUBSYS, *PIPS_SUBSYS;
715
716 /*
717 * Inquiry Data Format
718 */
719 typedef struct {
720 u8 DeviceType:5;
721 u8 DeviceTypeQualifier:3;
722 u8 DeviceTypeModifier:7;
723 u8 RemoveableMedia:1;
724 u8 Versions;
725 u8 ResponseDataFormat;
726 u8 AdditionalLength;
727 u16 Reserved;
728 u8 SoftReset:1;
729 u8 CommandQueue:1;
730 u8 Reserved2:1;
731 u8 LinkedCommands:1;
732 u8 Synchronous:1;
733 u8 Wide16Bit:1;
734 u8 Wide32Bit:1;
735 u8 RelativeAddressing:1;
736 u8 VendorId[8];
737 u8 ProductId[16];
738 u8 ProductRevisionLevel[4];
739 u8 VendorSpecific[20];
740 u8 Reserved3[40];
741 } IPS_INQ_DATA, *PIPS_INQ_DATA;
742
743 /*
744 * Read Capacity Data Format
745 */
746 typedef struct {
747 u32 lba;
748 u32 len;
749 } IPS_CAPACITY;
750
751 /*
752 * Sense Data Format
753 */
754 typedef struct {
755 u8 pg_pc:6; /* Page Code */
756 u8 pg_res1:2; /* Reserved */
757 u8 pg_len; /* Page Length */
758 u16 pg_trk_z; /* Tracks per zone */
759 u16 pg_asec_z; /* Alternate sectors per zone */
760 u16 pg_atrk_z; /* Alternate tracks per zone */
761 u16 pg_atrk_v; /* Alternate tracks per volume */
762 u16 pg_sec_t; /* Sectors per track */
763 u16 pg_bytes_s; /* Bytes per physical sectors */
764 u16 pg_intl; /* Interleave */
765 u16 pg_trkskew; /* Track skew factor */
766 u16 pg_cylskew; /* Cylinder Skew Factor */
767 u32 pg_res2:27; /* Reserved */
768 u32 pg_ins:1; /* Inhibit Slave */
769 u32 pg_surf:1; /* Allocate Surface Sectors */
770 u32 pg_rmb:1; /* Removeable */
771 u32 pg_hsec:1; /* Hard sector formatting */
772 u32 pg_ssec:1; /* Soft sector formatting */
773 } IPS_DADF;
774
775 typedef struct {
776 u8 pg_pc:6; /* Page Code */
777 u8 pg_res1:2; /* Reserved */
778 u8 pg_len; /* Page Length */
779 u16 pg_cylu; /* Number of cylinders (upper) */
780 u8 pg_cyll; /* Number of cylinders (lower) */
781 u8 pg_head; /* Number of heads */
782 u16 pg_wrpcompu; /* Write precomp (upper) */
783 u32 pg_wrpcompl:8; /* Write precomp (lower) */
784 u32 pg_redwrcur:24; /* Reduced write current */
785 u32 pg_drstep:16; /* Drive step rate */
786 u32 pg_landu:16; /* Landing zone cylinder (upper) */
787 u32 pg_landl:8; /* Landing zone cylinder (lower) */
788 u32 pg_res2:24; /* Reserved */
789 } IPS_RDDG;
790
791 struct ips_blk_desc {
792 u8 bd_dencode;
793 u8 bd_nblks1;
794 u8 bd_nblks2;
795 u8 bd_nblks3;
796 u8 bd_res;
797 u8 bd_blen1;
798 u8 bd_blen2;
799 u8 bd_blen3;
800 };
801
802 typedef struct {
803 u8 plh_len; /* Data length */
804 u8 plh_type; /* Medium type */
805 u8 plh_res:7; /* Reserved */
806 u8 plh_wp:1; /* Write protect */
807 u8 plh_bdl; /* Block descriptor length */
808 } ips_sense_plh_t;
809
810 typedef struct {
811 ips_sense_plh_t plh;
812 struct ips_blk_desc blk_desc;
813
814 union {
815 IPS_DADF pg3;
816 IPS_RDDG pg4;
817 } pdata;
818 } ips_mdata_t;
819
820 /*
821 * Scatter Gather list format
822 */
823 typedef struct ips_sglist {
824 u32 address;
825 u32 length;
826 } IPS_SG_LIST, *PIPS_SG_LIST;
827
828 typedef struct _IPS_INFOSTR {
829 char *buffer;
830 int length;
831 int offset;
832 int pos;
833 int localpos;
834 } IPS_INFOSTR;
835
836 typedef struct {
837 char *option_name;
838 int *option_flag;
839 int option_value;
840 } IPS_OPTION;
841
842 /*
843 * Status Info
844 */
845 typedef struct ips_stat {
846 u32 residue_len;
847 u32 scb_addr;
848 } ips_stat_t;
849
850 /*
851 * SCB Queue Format
852 */
853 typedef struct ips_scb_queue {
854 struct ips_scb *head;
855 struct ips_scb *tail;
856 u32 count;
857 u32 cpu_flags;
858 spinlock_t lock;
859 } ips_scb_queue_t;
860
861 /*
862 * Wait queue_format
863 */
864 typedef struct ips_wait_queue {
865 Scsi_Cmnd *head;
866 Scsi_Cmnd *tail;
867 u32 count;
868 u32 cpu_flags;
869 spinlock_t lock;
870 } ips_wait_queue_t;
871
872 typedef struct ips_copp_wait_item {
873 Scsi_Cmnd *scsi_cmd;
874 struct semaphore *sem;
875 struct ips_copp_wait_item *next;
876 } ips_copp_wait_item_t;
877
878 typedef struct ips_copp_queue {
879 struct ips_copp_wait_item *head;
880 struct ips_copp_wait_item *tail;
881 u32 count;
882 u32 cpu_flags;
883 spinlock_t lock;
884 } ips_copp_queue_t;
885
886 /* forward decl for host structure */
887 struct ips_ha;
888
889 typedef struct {
890 int (*reset)(struct ips_ha *);
891 int (*issue)(struct ips_ha *, struct ips_scb *);
892 int (*isinit)(struct ips_ha *);
893 int (*isintr)(struct ips_ha *);
894 int (*init)(struct ips_ha *);
895 int (*erasebios)(struct ips_ha *);
896 int (*programbios)(struct ips_ha *, char *, int);
897 int (*verifybios)(struct ips_ha *, char *, int);
898 u32 (*statupd)(struct ips_ha *);
899 void (*statinit)(struct ips_ha *);
900 void (*intr)(struct ips_ha *);
901 void (*enableint)(struct ips_ha *);
902 } ips_hw_func_t;
903
904 typedef struct ips_ha {
905 u8 ha_id[IPS_MAX_CHANNELS+1];
906 u32 dcdb_active[IPS_MAX_CHANNELS];
907 u32 io_addr; /* Base I/O address */
908 u8 irq; /* IRQ for adapter */
909 u8 ntargets; /* Number of targets */
910 u8 nbus; /* Number of buses */
911 u8 nlun; /* Number of Luns */
912 u16 ad_type; /* Adapter type */
913 u16 host_num; /* Adapter number */
914 u32 max_xfer; /* Maximum Xfer size */
915 u32 max_cmds; /* Max concurrent commands */
916 u32 num_ioctl; /* Number of Ioctls */
917 ips_stat_t sp; /* Status packer pointer */
918 struct ips_scb *scbs; /* Array of all CCBS */
919 struct ips_scb *scb_freelist; /* SCB free list */
920 ips_wait_queue_t scb_waitlist; /* Pending SCB list */
921 ips_copp_queue_t copp_waitlist; /* Pending PT list */
922 ips_scb_queue_t scb_activelist; /* Active SCB list */
923 IPS_IO_CMD *dummy; /* dummy command */
924 IPS_ADAPTER *adapt; /* Adapter status area */
925 IPS_ENQ *enq; /* Adapter Enquiry data */
926 IPS_CONF *conf; /* Adapter config data */
927 IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
928 IPS_SUBSYS *subsys; /* Subsystem parameters */
929 char *ioctl_data; /* IOCTL data area */
930 u32 ioctl_datasize; /* IOCTL data size */
931 u32 cmd_in_progress; /* Current command in progress*/
932 long flags; /* HA flags */
933 u8 waitflag; /* are we waiting for cmd */
934 u8 active;
935 u16 reset_count; /* number of resets */
936 u32 last_ffdc; /* last time we sent ffdc info*/
937 u8 revision_id; /* Revision level */
938 u16 device_id; /* PCI device ID */
939 u8 reserved;
940 u32 mem_addr; /* Memory mapped address */
941 u32 io_len; /* Size of IO Address */
942 u32 mem_len; /* Size of memory address */
943 char *mem_ptr; /* Memory mapped Ptr */
944 char *ioremap_ptr; /* ioremapped memory pointer */
945 ips_hw_func_t func; /* hw function pointers */
946 struct pci_dev *pcidev; /* PCI device handle */
947 spinlock_t scb_lock;
948 spinlock_t copp_lock;
949 spinlock_t ips_lock;
950 } ips_ha_t;
951
952 typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
953
954 /*
955 * SCB Format
956 */
957 typedef struct ips_scb {
958 IPS_HOST_COMMAND cmd;
959 IPS_DCDB_TABLE dcdb;
960 u8 target_id;
961 u8 bus;
962 u8 lun;
963 u8 cdb[12];
964 u32 scb_busaddr;
965 u32 data_busaddr;
966 u32 timeout;
967 u8 basic_status;
968 u8 extended_status;
969 u16 breakup;
970 u32 data_len;
971 u32 sg_len;
972 u32 flags;
973 u32 op_code;
974 IPS_SG_LIST *sg_list;
975 Scsi_Cmnd *scsi_cmd;
976 struct ips_scb *q_next;
977 ips_scb_callback callback;
978 struct semaphore *sem;
979 } ips_scb_t;
980
981 typedef struct ips_scb_pt {
982 IPS_HOST_COMMAND cmd;
983 IPS_DCDB_TABLE dcdb;
984 u8 target_id;
985 u8 bus;
986 u8 lun;
987 u8 cdb[12];
988 u32 scb_busaddr;
989 u32 data_busaddr;
990 u32 timeout;
991 u8 basic_status;
992 u8 extended_status;
993 u16 breakup;
994 u32 data_len;
995 u32 sg_len;
996 u32 flags;
997 u32 op_code;
998 IPS_SG_LIST *sg_list;
999 Scsi_Cmnd *scsi_cmd;
1000 struct ips_scb *q_next;
1001 ips_scb_callback callback;
1002 } ips_scb_pt_t;
1003
1004 /*
1005 * Passthru Command Format
1006 */
1007 typedef struct {
1008 u8 CoppID[4];
1009 u32 CoppCmd;
1010 u32 PtBuffer;
1011 u8 *CmdBuffer;
1012 u32 CmdBSize;
1013 ips_scb_pt_t CoppCP;
1014 u32 TimeOut;
1015 u8 BasicStatus;
1016 u8 ExtendedStatus;
1017 u16 reserved;
1018 } ips_passthru_t;
1019
1020 #endif
1021
1022 /*
1023 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1024 * Emacs will notice this stuff at the end of the file and automatically
1025 * adjust the settings for this buffer only. This must remain at the end
1026 * of the file.
1027 * ---------------------------------------------------------------------------
1028 * Local variables:
1029 * c-indent-level: 2
1030 * c-brace-imaginary-offset: 0
1031 * c-brace-offset: -2
1032 * c-argdecl-indent: 2
1033 * c-label-offset: -2
1034 * c-continued-statement-offset: 2
1035 * c-continued-brace-offset: 0
1036 * indent-tabs-mode: nil
1037 * tab-width: 8
1038 * End:
1039 */
1040
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