1 /*************************************************************************
2 * QLOGIC LINUX SOFTWARE
3 *
4 * QLogic ISP1x80/1x160 device driver for Linux 2.3.x (redhat 6.x).
5 *
6 * COPYRIGHT (C) 1996-2000 QLOGIC CORPORATION
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the Qlogic's Linux Software License.
10 *
11 * This program is WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 *
18 * 1. Redistribution's or source code must retain the above copyright
19 * notice, this list of conditions, and the following disclaimer,
20 * without modification, immediately at the beginning of the file.
21 * 2. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 *****************************************************************************/
25
26 /*************************************************************************************
27 QLOGIC CORPORATION SOFTWARE
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155 *************************************************************************************/
156
157
158 #ifndef _IO_HBA_QLA1280_H /* wrapper symbol for kernel use */
159 #define _IO_HBA_QLA1280_H /* subject to change without notice */
160
161 #if defined(__cplusplus)
162 extern "C" {
163 #endif
164
165 #include <linux/version.h>
166
167 /*
168 * Enable define statement to ignore Data Underrun Errors,
169 * remove define statement to enable detection.
170 */
171 /* #define DATA_UNDERRUN_ERROR_DISABLE */
172
173 /*
174 * Driver debug definitions.
175 */
176 /* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM2. */
177 /* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM2. */
178 /* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM2. */
179 /* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM2. */
180 /* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM2. */
181 /* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM2. */
182 /* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM2. */
183
184 #define QL_DEBUG_CONSOLE /* Output to console instead of COM2. */
185
186 #ifndef TRUE
187 # define TRUE 1
188 #endif
189 #ifndef FALSE
190 # define FALSE 0
191 #endif
192
193
194 #ifndef KERNEL_VERSION
195 # define KERNEL_VERSION(x,y,z) (((x)<<16)+((y)<<8)+(z))
196 #endif
197
198 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,1,92)
199 # if defined(__sparc_v9__) || defined(__powerpc__)
200 # error "PPC and Sparc platforms are only support under 2.1.92 and above"
201 # endif
202 #endif
203
204
205 /*
206 * Locking
207 */
208 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)
209 # include <linux/spinlock.h>
210 # include <linux/smp.h>
211 # define cpuid smp_processor_id()
212 # if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
213 # define DRIVER_LOCK_INIT \
214 spin_lock_init(&ha->spin_lock);
215 # define DRIVER_LOCK \
216 if(!ha->cpu_lock_count[cpuid]) { \
217 spin_lock_irqsave(&ha->spin_lock, cpu_flags); \
218 ha->cpu_lock_count[cpuid]++; \
219 } else { \
220 ha->cpu_lock_count[cpuid]++; \
221 }
222 # define DRIVER_UNLOCK \
223 if(--ha->cpu_lock_count[cpuid] == 0) \
224 spin_unlock_irqrestore(&ha->spin_lock, cpu_flags);
225 # else
226 # define DRIVER_LOCK_INIT
227 # define DRIVER_LOCK
228 # define DRIVER_UNLOCK
229 # endif
230 #else
231 # define cpuid 0
232 # define DRIVER_LOCK_INIT
233 # define DRIVER_LOCK \
234 save_flags(cpu_flags); \
235 cli();
236 # define DRIVER_UNLOCK \
237 restore_flags(cpu_flags);
238 # define le32_to_cpu(x) (x)
239 # define cpu_to_le32(x) (x)
240 #endif
241
242 /*
243 * Data bit definitions.
244 */
245 #define BIT_0 0x1
246 #define BIT_1 0x2
247 #define BIT_2 0x4
248 #define BIT_3 0x8
249 #define BIT_4 0x10
250 #define BIT_5 0x20
251 #define BIT_6 0x40
252 #define BIT_7 0x80
253 #define BIT_8 0x100
254 #define BIT_9 0x200
255 #define BIT_10 0x400
256 #define BIT_11 0x800
257 #define BIT_12 0x1000
258 #define BIT_13 0x2000
259 #define BIT_14 0x4000
260 #define BIT_15 0x8000
261 #define BIT_16 0x10000
262 #define BIT_17 0x20000
263 #define BIT_18 0x40000
264 #define BIT_19 0x80000
265 #define BIT_20 0x100000
266 #define BIT_21 0x200000
267 #define BIT_22 0x400000
268 #define BIT_23 0x800000
269 #define BIT_24 0x1000000
270 #define BIT_25 0x2000000
271 #define BIT_26 0x4000000
272 #define BIT_27 0x8000000
273 #define BIT_28 0x10000000
274 #define BIT_29 0x20000000
275 #define BIT_30 0x40000000
276 #define BIT_31 0x80000000
277
278 /*
279 * Common size type definitions
280 */
281 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,0)
282 typedef unsigned char uint8_t;
283 typedef unsigned short uint16_t;
284 typedef unsigned long uint32_t;
285 typedef char int8_t;
286 typedef short int16_t;
287 typedef long int32_t;
288 #endif
289
290 /*
291 * Local Macro Definitions.
292 */
293 #if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \
294 defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || \
295 defined(QL_DEBUG_LEVEL_5) || defined(QL_DEBUG_LEVEL_6) || \
296 defined(QL_DEBUG_LEVEL_7)
297 #define QL_DEBUG_ROUTINES
298 #endif
299
300 /*
301 * I/O port macros
302 */
303 #define LINUX_IOPORTS /* Linux in/out routines are define*/
304 /* differently from other OSs */
305 /* #define MEMORY_MAPPED_IO */ /* Enable memory mapped I/O */
306 #undef MEMORY_MAPPED_IO /* Disable memory mapped I/O */
307
308 #ifdef QL_DEBUG_LEVEL_1
309 #define RD_REG_BYTE(addr) qla1280_getbyte((uint8_t *)addr)
310 #define RD_REG_WORD(addr) qla1280_getword((uint16_t *)addr)
311 #define RD_REG_DWORD(addr) qla1280_getdword((uint32_t *)addr)
312 #define WRT_REG_BYTE(addr, data) qla1280_putbyte((uint8_t *)addr, data)
313 #define WRT_REG_WORD(addr, data) qla1280_putword((uint16_t *)addr, data)
314 #define WRT_REG_DWORD(addr, data) qla1280_putdword((uint32_t *)addr, data)
315 #else /* QL_DEBUG_LEVEL_1 */
316 #ifdef MEMORY_MAPPED_IO
317 #define RD_REG_BYTE(addr) readb((unsigned long) (addr)
318 #define RD_REG_WORD(addr) readw((unsigned long) (addr)
319 #define RD_REG_DWORD(addr) readl((unsigned long) (addr)
320 #define WRT_REG_BYTE(addr, data) writeb((data), (unsigned long) (addr))
321 #define WRT_REG_WORD(addr, data) writew((data), (unsigned long) (addr))
322 #define WRT_REG_DWORD(addr, data) writel((data), (unsigned long) (addr))
323 #else /* MEMORY_MAPPED_IO */
324 #define RD_REG_BYTE(addr) (inb((unsigned long)addr))
325 #define RD_REG_WORD(addr) (inw((unsigned long)addr))
326 #define RD_REG_DWORD(addr) (inl((unsigned long)addr))
327 #ifdef LINUX_IOPORTS
328 /* Parameters are reversed in Linux */
329 #define WRT_REG_BYTE(addr, data) (outb(data,(unsigned long)addr))
330 #define WRT_REG_WORD(addr, data) (outw(data,(unsigned long)addr))
331 #define WRT_REG_DWORD(addr, data) (outl(data,(unsigned long)addr))
332 #else
333 #define WRT_REG_BYTE(addr, data) (outb((unsigned long)addr, data))
334 #define WRT_REG_WORD(addr, data) (outw((unsigned long)addr, data))
335 #define WRT_REG_DWORD(addr, data) (outl((unsigned long)addr, data))
336 #endif
337 #endif /* MEMORY_MAPPED_IO */
338 #endif /* QL_DEBUG_LEVEL_1 */
339
340 /*
341 * Host adapter default definitions.
342 */
343 #define MAX_BUSES 2 /* 2 */
344 #define MAX_B_BITS 1
345
346 #define MAX_TARGETS 16 /* 16 */
347 #define MAX_T_BITS 4 /* 4 */
348
349 #define MAX_LUNS 8 /* 32 */
350 #define MAX_L_BITS 3 /* 5 */
351
352 /*
353 * Watchdog time quantum
354 */
355 #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */
356
357 /* Command retry count (0-65535) */
358 #define COMMAND_RETRY_COUNT 255
359
360 /* Maximum outstanding commands in ISP queues (1-65535) */
361 #define MAX_OUTSTANDING_COMMANDS 512
362
363 /* ISP request and response entry counts (37-65535) */
364 #define REQUEST_ENTRY_CNT 256 /* Number of request entries. */
365 #define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */
366
367 /* Maximum equipage per controller */
368 #define MAX_EQ (MAX_BUSES * MAX_TARGETS * MAX_LUNS)
369
370 /* Number of segments 1 - 65535 */
371 #define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */
372
373
374 typedef struct timer_list timer_t; /* timer */
375
376 /*
377 * SCSI Request Block structure
378 */
379 typedef struct srb
380 {
381 Scsi_Cmnd *cmd; /* (4) SCSI command block */
382 struct srb *s_next; /* (4) Next block on LU queue */
383 struct srb *s_prev; /* (4) Previous block on LU queue */
384 uint8_t flags; /* (1) Status flags. */
385 uint8_t dir; /* direction of transfer */
386 uint8_t unused[2];
387 u_long r_start; /* jiffies at start of request */
388 u_long u_start; /* jiffies when sent to F/W */
389 }srb_t;
390
391 /*
392 * SRB flag definitions
393 */
394 #define SRB_TIMEOUT BIT_0 /* Command timed out */
395 #define SRB_SENT BIT_1 /* Command sent to ISP */
396 #define SRB_ABORT_PENDING BIT_2 /* Command abort sent to device */
397 #define SRB_ABORTED BIT_3 /* Command aborted command already */
398
399
400 /*
401 * Logical Unit Queue structure
402 */
403 typedef struct scsi_lu
404 {
405 srb_t *q_first; /* First block on LU queue */
406 srb_t *q_last; /* Last block on LU queue */
407 uint8_t q_flag; /* LU queue state flags */
408 uint8_t q_sense[16]; /* sense data */
409 u_long io_cnt; /* total xfer count */
410 u_long resp_time; /* total response time (start - finish) */
411 u_long act_time; /* total actived time (minus queuing time) */
412 u_long w_cnt; /* total writes */
413 u_long r_cnt; /* total reads */
414 uint16_t q_outcnt; /* Pending jobs for this LU */
415 #if QL1280_TARGET_MODE_SUPPORT
416 void (*q_func)(); /* Target driver event handler */
417 int32_t q_param; /* Target driver event param */
418 uint8_t q_lock; /* Device Queue Lock */
419 #endif
420 }scsi_lu_t;
421
422 /*
423 * Logical Unit flags
424 */
425 #define QLA1280_QBUSY BIT_0
426 #define QLA1280_QWAIT BIT_1
427 #define QLA1280_QSUSP BIT_2
428 #define QLA1280_QSENSE BIT_3 /* Sense data cache valid */
429 #define QLA1280_QRESET BIT_4
430 #define QLA1280_QHBA BIT_5
431 #define QLA1280_BSUSP BIT_6 /* controller is suspended */
432 #define QLA1280_BREM BIT_7 /* controller is removed */
433
434 /*
435 * ISP PCI Configuration Register Set
436 */
437 typedef volatile struct
438 {
439 uint16_t vendor_id; /* 0x0 */
440 uint16_t device_id; /* 0x2 */
441 uint16_t command; /* 0x4 */
442 uint16_t status; /* 0x6 */
443 uint8_t revision_id; /* 0x8 */
444 uint8_t programming_interface; /* 0x9 */
445 uint8_t sub_class; /* 0xa */
446 uint8_t base_class; /* 0xb */
447 uint8_t cache_line; /* 0xc */
448 uint8_t latency_timer; /* 0xd */
449 uint8_t header_type; /* 0xe */
450 uint8_t bist; /* 0xf */
451 uint32_t base_port; /* 0x10 */
452 uint32_t mem_base_addr; /* 0x14 */
453 uint32_t base_addr[4]; /* 0x18-0x24 */
454 uint32_t reserved_1[2]; /* 0x28-0x2c */
455 uint16_t expansion_rom; /* 0x30 */
456 uint32_t reserved_2[2]; /* 0x34-0x38 */
457 uint8_t interrupt_line; /* 0x3c */
458 uint8_t interrupt_pin; /* 0x3d */
459 uint8_t min_grant; /* 0x3e */
460 uint8_t max_latency; /* 0x3f */
461 }config_reg_t;
462
463 /*
464 * ISP I/O Register Set structure definitions.
465 */
466 typedef volatile struct
467 {
468 uint16_t id_l; /* ID low */
469 uint16_t id_h; /* ID high */
470 uint16_t cfg_0; /* Configuration 0 */
471 uint16_t cfg_1; /* Configuration 1 */
472 uint16_t ictrl; /* Interface control */
473 #define ISP_RESET BIT_0 /* ISP soft reset */
474 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
475 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
476 uint16_t istatus; /* Interface status */
477 #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */
478 #define RISC_INT BIT_2 /* RISC interrupt */
479 #define PCI_INT BIT_1 /* PCI interrupt */
480 uint16_t semaphore; /* Semaphore */
481 uint16_t nvram; /* NVRAM register. */
482 #define NV_DESELECT 0
483 #define NV_CLOCK BIT_0
484 #define NV_SELECT BIT_1
485 #define NV_DATA_OUT BIT_2
486 #define NV_DATA_IN BIT_3
487 uint16_t flash_data; /* Flash BIOS data */
488 uint16_t flash_address; /* Flash BIOS address */
489
490 uint16_t unused_1[0x2e]; /* 0x14-0x6f Gap */
491
492 uint16_t mailbox0; /* Mailbox 0 */
493 uint16_t mailbox1; /* Mailbox 1 */
494 uint16_t mailbox2; /* Mailbox 2 */
495 uint16_t mailbox3; /* Mailbox 3 */
496 uint16_t mailbox4; /* Mailbox 4 */
497 uint16_t mailbox5; /* Mailbox 5 */
498 uint16_t mailbox6; /* Mailbox 6 */
499 uint16_t mailbox7; /* Mailbox 7 */
500
501 uint16_t unused_2[0x20]; /* 0x80-0xbf Gap */
502
503 uint16_t host_cmd; /* Host command and control */
504 #define HOST_INT BIT_7 /* host interrupt bit */
505 #define BIOS_ENABLE BIT_0
506
507 uint16_t unused_6[0x5]; /* 0xc2-0xcb Gap */
508
509 uint16_t gpio_data;
510 uint16_t gpio_enable;
511
512 uint16_t unused_7[0x11]; /* d0-f0 */
513 uint16_t scsiControlPins; /* f2 */
514
515 }device_reg_t;
516
517 #define MAILBOX_REGISTER_COUNT 8
518
519 /*
520 * ISP product identification definitions in mailboxes after reset.
521 */
522 #define PROD_ID_1 0x4953
523 #define PROD_ID_2 0x0000
524 #define PROD_ID_2a 0x5020
525 #define PROD_ID_3 0x2020
526 #define PROD_ID_4 0x1
527
528 /*
529 * ISP host command and control register command definitions
530 */
531 #define HC_RESET_RISC 0x1000 /* Reset RISC */
532 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
533 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
534 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
535 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
536 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
537 #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */
538
539 /*
540 * ISP mailbox Self-Test status codes
541 */
542 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
543 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
544 #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */
545 #define MBS_BUSY 4 /* Busy. */
546
547 /*
548 * ISP mailbox command complete status codes
549 */
550 #define MBS_CMD_CMP 0x4000 /* Command Complete. */
551 #define MBS_INV_CMD 0x4001 /* Invalid Command. */
552 #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */
553 #define MBS_TEST_FAILED 0x4003 /* Test Failed. */
554 #define MBS_CMD_ERR 0x4005 /* Command Error. */
555 #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */
556
557 /*
558 * ISP mailbox asynchronous event status codes
559 */
560 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
561 #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */
562 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
563 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
564 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
565 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
566 #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */
567 #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */
568 #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */
569 #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */
570
571 /*
572 * ISP mailbox commands
573 */
574 #define MBC_NOP 0 /* No Operation. */
575 #define MBC_LOAD_RAM 1 /* Load RAM. */
576 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
577 #define MBC_WRITE_RAM_WORD 4 /* Write ram word. */
578 #define MBC_READ_RAM_WORD 5 /* Read ram word. */
579 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
580 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
581 #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision. */
582 #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue. */
583 #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue. */
584 #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command. */
585 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
586 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
587 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
588 #define MBC_BUS_RESET 0x18 /* SCSI bus reset. */
589 #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay. */
590 #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters. */
591 #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID. */
592 #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout. */
593 #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay. */
594 #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit. */
595 #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate. */
596 #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state. */
597 #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time. */
598 #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters. */
599 #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters. */
600 #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */
601 #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word. */
602 #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word. */
603 #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */
604 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64. */
605 #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode. */
606
607 /*
608 * ISP Get/Set Target Parameters mailbox command control flags.
609 */
610 #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */
611 #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */
612 #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */
613 #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */
614 #define TP_SYNC BIT_12 /* Synchronous data transfers. */
615 #define TP_WIDE BIT_13 /* Wide data transfers. */
616 #define TP_PARITY BIT_14 /* Parity checking. */
617 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */
618
619 /*
620 * NVRAM Command values.
621 */
622 #define NV_START_BIT BIT_2
623 #define NV_WRITE_OP (BIT_26+BIT_24)
624 #define NV_READ_OP (BIT_26+BIT_25)
625 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
626 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
627 #define NV_DELAY_COUNT 10
628
629 /*
630 * QLogic ISP1280 NVRAM structure definition.
631 */
632 typedef struct
633 {
634 uint8_t id[4]; /* 0, 1, 2, 3 */
635 uint8_t version; /* 4 */
636
637 struct
638 {
639 uint8_t bios_configuration_mode :2;
640 uint8_t bios_disable :1;
641 uint8_t selectable_scsi_boot_enable :1;
642 uint8_t cd_rom_boot_enable :1;
643 uint8_t disable_loading_risc_code :1;
644 uint8_t enable_64bit_addressing :1;
645 uint8_t unused_7 :1;
646 }cntr_flags_1; /* 5 */
647
648 struct
649 {
650 uint8_t boot_lun_number :5;
651 uint8_t scsi_bus_number :1;
652 uint8_t unused_6 :1;
653 uint8_t unused_7 :1;
654 uint8_t boot_target_number :4;
655 uint8_t unused_12 :1;
656 uint8_t unused_13 :1;
657 uint8_t unused_14 :1;
658 uint8_t unused_15 :1;
659 }cntr_flags_2; /* 6, 7 */
660
661 uint16_t unused_8; /* 8, 9 */
662 uint16_t unused_10; /* 10, 11 */
663 uint16_t unused_12; /* 12, 13 */
664 uint16_t unused_14; /* 14, 15 */
665
666 union
667 {
668 uint8_t c;
669 struct
670 {
671 uint8_t reserved :2;
672 uint8_t burst_enable :1;
673 uint8_t reserved_1 :1;
674 uint8_t fifo_threshold :4;
675 }f;
676 }isp_config; /* 16 */
677
678 /* Termination
679 * 0 = Disable, 1 = high only, 3 = Auto term
680 */
681 union
682 {
683 uint8_t c;
684 struct
685 {
686 uint8_t scsi_bus_1_control :2;
687 uint8_t scsi_bus_0_control :2;
688 uint8_t unused_0 :1;
689 uint8_t unused_1 :1;
690 uint8_t unused_2 :1;
691 uint8_t auto_term_support :1;
692 }f;
693 }termination; /* 17 */
694
695 uint16_t isp_parameter; /* 18, 19 */
696
697 union
698 {
699 uint16_t w;
700 struct
701 {
702 uint8_t enable_fast_posting :1;
703 uint8_t report_lvd_bus_transition :1;
704 uint8_t unused_2 :1;
705 uint8_t unused_3 :1;
706 uint8_t unused_4 :1;
707 uint8_t unused_5 :1;
708 uint8_t unused_6 :1;
709 uint8_t unused_7 :1;
710 uint8_t unused_8 :1;
711 uint8_t unused_9 :1;
712 uint8_t unused_10 :1;
713 uint8_t unused_11 :1;
714 uint8_t unused_12 :1;
715 uint8_t unused_13 :1;
716 uint8_t unused_14 :1;
717 uint8_t unused_15 :1;
718 }f;
719 }firmware_feature; /* 20, 21 */
720
721 uint16_t unused_22; /* 22, 23 */
722
723 struct
724 {
725 struct
726 {
727 uint8_t initiator_id :4;
728 uint8_t scsi_reset_disable :1;
729 uint8_t scsi_bus_size :1;
730 uint8_t scsi_bus_type :1;
731 uint8_t unused_7 :1;
732 }config_1; /* 24 */
733
734 uint8_t bus_reset_delay; /* 25 */
735 uint8_t retry_count; /* 26 */
736 uint8_t retry_delay; /* 27 */
737
738 struct
739 {
740 uint8_t async_data_setup_time :4;
741 uint8_t req_ack_active_negation :1;
742 uint8_t data_line_active_negation :1;
743 uint8_t unused_6 :1;
744 uint8_t unused_7 :1;
745 }config_2; /* 28 */
746
747 uint8_t unused_29; /* 29 */
748
749 uint16_t selection_timeout; /* 30, 31 */
750 uint16_t max_queue_depth; /* 32, 33 */
751
752 uint16_t unused_34; /* 34, 35 */
753 uint16_t unused_36; /* 36, 37 */
754 uint16_t unused_38; /* 38, 39 */
755
756 struct
757 {
758 union
759 {
760 uint8_t c;
761 struct
762 {
763 uint8_t renegotiate_on_error :1;
764 uint8_t stop_queue_on_check :1;
765 uint8_t auto_request_sense :1;
766 uint8_t tag_queuing :1;
767 uint8_t sync_data_transfers :1;
768 uint8_t wide_data_transfers :1;
769 uint8_t parity_checking :1;
770 uint8_t disconnect_allowed :1;
771 }f;
772 }parameter; /* 40 */
773
774 uint8_t execution_throttle; /* 41 */
775 uint8_t sync_period; /* 42 */
776
777 struct
778 {
779 uint8_t sync_offset :4;
780 uint8_t device_enable :1;
781 uint8_t lun_disable :1;
782 uint8_t unused_6 :1;
783 uint8_t unused_7 :1;
784 }flags; /* 43 */
785
786 uint16_t unused_44; /* 44, 45 */
787 }target[MAX_TARGETS];
788 }bus[MAX_BUSES];
789
790 uint16_t unused_248; /* 248, 249 */
791
792 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
793
794 uint8_t unused_254; /* 254 */
795
796 uint8_t chksum; /* 255 */
797 }nvram_t;
798
799 /*
800 * QLogic ISP12160 NVRAM structure definition.
801 */
802 typedef struct
803 {
804 uint8_t id[4]; /* 0, 1, 2, 3 */
805 uint8_t version; /* 4 */
806 /* Host/Bios Flags */
807 struct
808 {
809 uint8_t bios_configuration_mode :2;
810 uint8_t bios_disable :1;
811 uint8_t selectable_scsi_boot_enable :1;
812 uint8_t cd_rom_boot_enable :1;
813 uint8_t disable_loading_risc_code :1;
814 uint8_t unused_6 :1;
815 uint8_t unused_7 :1;
816 }cntr_flags_1; /* 5 */
817 /* Selectable Boot Support */
818 struct
819 {
820 uint8_t boot_lun_number :5;
821 uint8_t scsi_bus_number :1;
822 uint8_t unused_6 :1;
823 uint8_t unused_7 :1;
824 uint8_t boot_target_number :4;
825 uint8_t unused_12 :1;
826 uint8_t unused_13 :1;
827 uint8_t unused_14 :1;
828 uint8_t unused_15 :1;
829 }cntr_flags_2; /* 6, 7 */
830
831 uint16_t unused_8; /* 8, 9 */
832 uint16_t unused_10; /* 10, 11 */
833 uint16_t unused_12; /* 12, 13 */
834 uint16_t unused_14; /* 14, 15 */
835
836 /* ISP Config Parameters */
837 union
838 {
839 uint8_t c;
840 struct
841 {
842 uint8_t reserved :2;
843 uint8_t burst_enable :1;
844 uint8_t reserved_1 :1;
845 uint8_t fifo_threshold :4;
846 }f;
847 }isp_config; /* 16 */
848
849 /* Termination
850 * 0 = Disable, 1 = high only, 3 = Auto term
851 */
852 union
853 {
854 uint8_t c;
855 struct
856 {
857 uint8_t scsi_bus_1_control :2;
858 uint8_t scsi_bus_0_control :2;
859 uint8_t unused_0 :1;
860 uint8_t unused_1 :1;
861 uint8_t unused_2 :1;
862 uint8_t auto_term_support :1;
863 }f;
864 }termination; /* 17 */
865 /* Auto Term - 3 */
866 /* High Only - 1 (GPIO2 = 1 & GPIO3 = 0) */
867 /* Disable - 0 (GPIO2 = 0 & GPIO3 = X) */
868
869 uint16_t isp_parameter; /* 18, 19 */
870
871 union
872 {
873 uint16_t w;
874 struct
875 {
876 uint8_t enable_fast_posting :1;
877 uint8_t report_lvd_bus_transition :1;
878 uint8_t unused_2 :1;
879 uint8_t unused_3 :1;
880 uint8_t unused_4 :1;
881 uint8_t unused_5 :1;
882 uint8_t unused_6 :1;
883 uint8_t unused_7 :1;
884 uint8_t unused_8 :1;
885 uint8_t unused_9 :1;
886 uint8_t unused_10 :1;
887 uint8_t unused_11 :1;
888 uint8_t unused_12 :1;
889 uint8_t unused_13 :1;
890 uint8_t unused_14 :1;
891 uint8_t unused_15 :1;
892 }f;
893 }firmware_feature; /* 20, 21 */
894
895 uint16_t unused_22; /* 22, 23 */
896
897 struct
898 {
899 struct
900 {
901 uint8_t initiator_id :4;
902 uint8_t scsi_reset_disable :1;
903 uint8_t scsi_bus_size :1;
904 uint8_t scsi_bus_type :1;
905 uint8_t unused_7 :1;
906 }config_1; /* 24 */
907
908 uint8_t bus_reset_delay; /* 25 */
909 uint8_t retry_count; /* 26 */
910 uint8_t retry_delay; /* 27 */
911 /* Adapter Capabilities bits */
912 struct
913 {
914 uint8_t async_data_setup_time :4;
915 uint8_t req_ack_active_negation :1;
916 uint8_t data_line_active_negation :1;
917 uint8_t unused_6 :1;
918 uint8_t unused_7 :1;
919 }config_2; /* 28 */
920
921 uint8_t unused_29; /* 29 */
922
923 uint16_t selection_timeout; /* 30, 31 */
924 uint16_t max_queue_depth; /* 32, 33 */
925
926 uint16_t unused_34; /* 34, 35 */
927 uint16_t unused_36; /* 36, 37 */
928 uint16_t unused_38; /* 38, 39 */
929
930 struct
931 {
932 union
933 {
934 uint8_t c;
935 struct
936 {
937 uint8_t renegotiate_on_error :1;
938 uint8_t stop_queue_on_check :1;
939 uint8_t auto_request_sense :1;
940 uint8_t tag_queuing :1;
941 uint8_t sync_data_transfers :1;
942 uint8_t wide_data_transfers :1;
943 uint8_t parity_checking :1;
944 uint8_t disconnect_allowed :1;
945 }f;
946 }parameter; /* 40 */
947
948 uint8_t execution_throttle; /* 41 */
949 uint8_t sync_period; /* 42 */
950
951 struct
952 {
953 uint8_t sync_offset :5;
954 uint8_t device_enable :1;
955 uint8_t unused_6 :1;
956 uint8_t unused_7 :1;
957 uint8_t ppr_options :4;
958 uint8_t ppr_bus_width :2;
959 uint8_t unused_8 :1;
960 uint8_t enable_ppr :1;
961 }flags; /* 43, 44 */
962
963 uint8_t unused_45; /* 45 */
964 }target[MAX_TARGETS];
965 }bus[MAX_BUSES];
966
967 uint16_t unused_248; /* 248, 249 */
968
969 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */
970
971 uint8_t System_Id_Pointer; /* 254 */
972
973 uint8_t chksum; /* 255 */
974 }nvram160_t;
975
976 /*
977 * ISP queue - command entry structure definition.
978 */
979 #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */
980 typedef struct
981 {
982 uint8_t entry_type; /* Entry type. */
983 #define COMMAND_TYPE 1 /* Command entry */
984 uint8_t entry_count; /* Entry count. */
985 uint8_t sys_define; /* System defined. */
986 uint8_t entry_status; /* Entry Status. */
987 uint32_t handle; /* System handle. */
988 uint8_t lun; /* SCSI LUN */
989 uint8_t target; /* SCSI ID */
990 uint16_t cdb_len; /* SCSI command length. */
991 uint16_t control_flags; /* Control flags. */
992 uint16_t reserved;
993 uint16_t timeout; /* Command timeout. */
994 uint16_t dseg_count; /* Data segment count. */
995 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
996 uint32_t dseg_0_address; /* Data segment 0 address. */
997 uint32_t dseg_0_length; /* Data segment 0 length. */
998 uint32_t dseg_1_address; /* Data segment 1 address. */
999 uint32_t dseg_1_length; /* Data segment 1 length. */
1000 uint32_t dseg_2_address; /* Data segment 2 address. */
1001 uint32_t dseg_2_length; /* Data segment 2 length. */
1002 uint32_t dseg_3_address; /* Data segment 3 address. */
1003 uint32_t dseg_3_length; /* Data segment 3 length. */
1004 }cmd_entry_t;
1005
1006 /*
1007 * ISP queue - continuation entry structure definition.
1008 */
1009 typedef struct
1010 {
1011 uint8_t entry_type; /* Entry type. */
1012 #define CONTINUE_TYPE 2 /* Continuation entry. */
1013 uint8_t entry_count; /* Entry count. */
1014 uint8_t sys_define; /* System defined. */
1015 uint8_t entry_status; /* Entry Status. */
1016 uint32_t reserved; /* Reserved */
1017 uint32_t dseg_0_address; /* Data segment 0 address. */
1018 uint32_t dseg_0_length; /* Data segment 0 length. */
1019 uint32_t dseg_1_address; /* Data segment 1 address. */
1020 uint32_t dseg_1_length; /* Data segment 1 length. */
1021 uint32_t dseg_2_address; /* Data segment 2 address. */
1022 uint32_t dseg_2_length; /* Data segment 2 length. */
1023 uint32_t dseg_3_address; /* Data segment 3 address. */
1024 uint32_t dseg_3_length; /* Data segment 3 length. */
1025 uint32_t dseg_4_address; /* Data segment 4 address. */
1026 uint32_t dseg_4_length; /* Data segment 4 length. */
1027 uint32_t dseg_5_address; /* Data segment 5 address. */
1028 uint32_t dseg_5_length; /* Data segment 5 length. */
1029 uint32_t dseg_6_address; /* Data segment 6 address. */
1030 uint32_t dseg_6_length; /* Data segment 6 length. */
1031 }cont_entry_t;
1032
1033 /*
1034 * ISP queue - status entry structure definition.
1035 */
1036 typedef struct
1037 {
1038 uint8_t entry_type; /* Entry type. */
1039 #define STATUS_TYPE 3 /* Status entry. */
1040 uint8_t entry_count; /* Entry count. */
1041 uint8_t sys_define; /* System defined. */
1042 uint8_t entry_status; /* Entry Status. */
1043 #define RF_CONT BIT_0 /* Continuation. */
1044 #define RF_FULL BIT_1 /* Full */
1045 #define RF_BAD_HEADER BIT_2 /* Bad header. */
1046 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */
1047 uint32_t handle; /* System handle. */
1048 uint16_t scsi_status; /* SCSI status. */
1049 uint16_t comp_status; /* Completion status. */
1050 uint16_t state_flags; /* State flags. */
1051 #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */
1052 #define SF_GOT_SENSE BIT_13 /* Got Sense */
1053 #define SF_GOT_STATUS BIT_12 /* Got Status */
1054 #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */
1055 #define SF_SENT_CDB BIT_10 /* Send CDB */
1056 #define SF_GOT_TARGET BIT_9 /* */
1057 #define SF_GOT_BUS BIT_8 /* */
1058 uint16_t status_flags; /* Status flags. */
1059 uint16_t time; /* Time. */
1060 uint16_t req_sense_length; /* Request sense data length. */
1061 uint32_t residual_length; /* Residual transfer length. */
1062 uint16_t reserved[4];
1063 uint8_t req_sense_data[32]; /* Request sense data. */
1064 }sts_entry_t, response_t;
1065
1066 /*
1067 * ISP queue - marker entry structure definition.
1068 */
1069 typedef struct
1070 {
1071 uint8_t entry_type; /* Entry type. */
1072 #define MARKER_TYPE 4 /* Marker entry. */
1073 uint8_t entry_count; /* Entry count. */
1074 uint8_t sys_define; /* System defined. */
1075 uint8_t entry_status; /* Entry Status. */
1076 uint32_t reserved;
1077 uint8_t lun; /* SCSI LUN */
1078 uint8_t target; /* SCSI ID */
1079 uint8_t modifier; /* Modifier (7-0). */
1080 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1081 #define MK_SYNC_ID 1 /* Synchronize ID */
1082 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1083 uint8_t reserved_1[53];
1084 }mrk_entry_t;
1085
1086 /*
1087 * ISP queue - extended command entry structure definition.
1088 */
1089 typedef struct
1090 {
1091 uint8_t entry_type; /* Entry type. */
1092 #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */
1093 uint8_t entry_count; /* Entry count. */
1094 uint8_t sys_define; /* System defined. */
1095 uint8_t entry_status; /* Entry Status. */
1096 uint32_t handle; /* System handle. */
1097 uint8_t lun; /* SCSI LUN */
1098 uint8_t target; /* SCSI ID */
1099 uint16_t cdb_len; /* SCSI command length. */
1100 uint16_t control_flags; /* Control flags. */
1101 uint16_t reserved;
1102 uint16_t timeout; /* Command timeout. */
1103 uint16_t dseg_count; /* Data segment count. */
1104 uint8_t scsi_cdb[88]; /* SCSI command words. */
1105 }ecmd_entry_t;
1106
1107 /*
1108 * ISP queue - 64-Bit addressing, command entry structure definition.
1109 */
1110 typedef struct
1111 {
1112 uint8_t entry_type; /* Entry type. */
1113 #define COMMAND_A64_TYPE 9 /* Command A64 entry */
1114 uint8_t entry_count; /* Entry count. */
1115 uint8_t sys_define; /* System defined. */
1116 uint8_t entry_status; /* Entry Status. */
1117 uint32_t handle; /* System handle. */
1118 uint8_t lun; /* SCSI LUN */
1119 uint8_t target; /* SCSI ID */
1120 uint16_t cdb_len; /* SCSI command length. */
1121 uint16_t control_flags; /* Control flags. */
1122 uint16_t reserved;
1123 uint16_t timeout; /* Command timeout. */
1124 uint16_t dseg_count; /* Data segment count. */
1125 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1126 uint32_t reserved_1[2]; /* unused */
1127 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1128 uint32_t dseg_0_length; /* Data segment 0 length. */
1129 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1130 uint32_t dseg_1_length; /* Data segment 1 length. */
1131 }cmd_a64_entry_t, request_t;
1132
1133 /*
1134 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1135 */
1136 typedef struct
1137 {
1138 uint8_t entry_type; /* Entry type. */
1139 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */
1140 uint8_t entry_count; /* Entry count. */
1141 uint8_t sys_define; /* System defined. */
1142 uint8_t entry_status; /* Entry Status. */
1143 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1144 uint32_t dseg_0_length; /* Data segment 0 length. */
1145 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1146 uint32_t dseg_1_length; /* Data segment 1 length. */
1147 uint32_t dseg_2_address[2]; /* Data segment 2 address. */
1148 uint32_t dseg_2_length; /* Data segment 2 length. */
1149 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1150 uint32_t dseg_3_length; /* Data segment 3 length. */
1151 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1152 uint32_t dseg_4_length; /* Data segment 4 length. */
1153 }cont_a64_entry_t;
1154
1155 /*
1156 * ISP queue - enable LUN entry structure definition.
1157 */
1158 typedef struct
1159 {
1160 uint8_t entry_type; /* Entry type. */
1161 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
1162 uint8_t entry_count; /* Entry count. */
1163 uint8_t reserved_1;
1164 uint8_t entry_status; /* Entry Status not used. */
1165 uint32_t reserved_2;
1166 uint16_t lun; /* Bit 15 is bus number. */
1167 uint16_t reserved_4;
1168 uint32_t option_flags;
1169 uint8_t status;
1170 uint8_t reserved_5;
1171 uint8_t command_count; /* Number of ATIOs allocated. */
1172 uint8_t immed_notify_count; /* Number of Immediate Notify */
1173 /* entries allocated. */
1174 uint8_t group_6_length; /* SCSI CDB length for group 6 */
1175 /* commands (2-26). */
1176 uint8_t group_7_length; /* SCSI CDB length for group 7 */
1177 /* commands (2-26). */
1178 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
1179 uint16_t reserved_6[20];
1180 }elun_entry_t;
1181
1182 /*
1183 * ISP queue - modify LUN entry structure definition.
1184 */
1185 typedef struct
1186 {
1187 uint8_t entry_type; /* Entry type. */
1188 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
1189 uint8_t entry_count; /* Entry count. */
1190 uint8_t reserved_1;
1191 uint8_t entry_status; /* Entry Status. */
1192 uint32_t reserved_2;
1193 uint8_t lun; /* SCSI LUN */
1194 uint8_t reserved_3;
1195 uint8_t operators;
1196 uint8_t reserved_4;
1197 uint32_t option_flags;
1198 uint8_t status;
1199 uint8_t reserved_5;
1200 uint8_t command_count; /* Number of ATIOs allocated. */
1201 uint8_t immed_notify_count; /* Number of Immediate Notify */
1202 /* entries allocated. */
1203 uint16_t reserved_6;
1204 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
1205 uint16_t reserved_7[20];
1206 }modify_lun_entry_t;
1207
1208 /*
1209 * ISP queue - immediate notify entry structure definition.
1210 */
1211 typedef struct
1212 {
1213 uint8_t entry_type; /* Entry type. */
1214 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */
1215 uint8_t entry_count; /* Entry count. */
1216 uint8_t reserved_1;
1217 uint8_t entry_status; /* Entry Status. */
1218 uint32_t reserved_2;
1219 uint8_t lun;
1220 uint8_t initiator_id;
1221 uint8_t reserved_3;
1222 uint8_t target_id;
1223 uint32_t option_flags;
1224 uint8_t status;
1225 uint8_t reserved_4;
1226 uint8_t tag_value; /* Received queue tag message value */
1227 uint8_t tag_type; /* Received queue tag message type */
1228 /* entries allocated. */
1229 uint16_t seq_id;
1230 uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */
1231 uint16_t reserved_5[8];
1232 uint8_t sense_data[18];
1233 }notify_entry_t;
1234
1235 /*
1236 * ISP queue - notify acknowledge entry structure definition.
1237 */
1238 typedef struct
1239 {
1240 uint8_t entry_type; /* Entry type. */
1241 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
1242 uint8_t entry_count; /* Entry count. */
1243 uint8_t reserved_1;
1244 uint8_t entry_status; /* Entry Status. */
1245 uint32_t reserved_2;
1246 uint8_t lun;
1247 uint8_t initiator_id;
1248 uint8_t reserved_3;
1249 uint8_t target_id;
1250 uint32_t option_flags;
1251 uint8_t status;
1252 uint8_t event;
1253 uint16_t seq_id;
1254 uint16_t reserved_4[22];
1255 }nack_entry_t;
1256
1257 /*
1258 * ISP queue - Accept Target I/O (ATIO) entry structure definition.
1259 */
1260 typedef struct
1261 {
1262 uint8_t entry_type; /* Entry type. */
1263 #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */
1264 uint8_t entry_count; /* Entry count. */
1265 uint8_t reserved_1;
1266 uint8_t entry_status; /* Entry Status. */
1267 uint32_t reserved_2;
1268 uint8_t lun;
1269 uint8_t initiator_id;
1270 uint8_t cdb_len;
1271 uint8_t target_id;
1272 uint32_t option_flags;
1273 uint8_t status;
1274 uint8_t scsi_status;
1275 uint8_t tag_value; /* Received queue tag message value */
1276 uint8_t tag_type; /* Received queue tag message type */
1277 uint8_t cdb[26];
1278 uint8_t sense_data[18];
1279 }atio_entry_t;
1280
1281 /*
1282 * ISP queue - Continue Target I/O (CTIO) entry structure definition.
1283 */
1284 typedef struct
1285 {
1286 uint8_t entry_type; /* Entry type. */
1287 #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */
1288 uint8_t entry_count; /* Entry count. */
1289 uint8_t reserved_1;
1290 uint8_t entry_status; /* Entry Status. */
1291 uint32_t reserved_2;
1292 uint8_t lun; /* SCSI LUN */
1293 uint8_t initiator_id;
1294 uint8_t reserved_3;
1295 uint8_t target_id;
1296 uint32_t option_flags;
1297 uint8_t status;
1298 uint8_t scsi_status;
1299 uint8_t tag_value; /* Received queue tag message value */
1300 uint8_t tag_type; /* Received queue tag message type */
1301 uint32_t transfer_length;
1302 uint32_t residual;
1303 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
1304 uint16_t dseg_count; /* Data segment count. */
1305 uint32_t dseg_0_address; /* Data segment 0 address. */
1306 uint32_t dseg_0_length; /* Data segment 0 length. */
1307 uint32_t dseg_1_address; /* Data segment 1 address. */
1308 uint32_t dseg_1_length; /* Data segment 1 length. */
1309 uint32_t dseg_2_address; /* Data segment 2 address. */
1310 uint32_t dseg_2_length; /* Data segment 2 length. */
1311 uint32_t dseg_3_address; /* Data segment 3 address. */
1312 uint32_t dseg_3_length; /* Data segment 3 length. */
1313 }ctio_entry_t;
1314
1315 /*
1316 * ISP queue - CTIO returned entry structure definition.
1317 */
1318 typedef struct
1319 {
1320 uint8_t entry_type; /* Entry type. */
1321 #define CTIO_RET_TYPE 7 /* CTIO return entry */
1322 uint8_t entry_count; /* Entry count. */
1323 uint8_t reserved_1;
1324 uint8_t entry_status; /* Entry Status. */
1325 uint32_t reserved_2;
1326 uint8_t lun; /* SCSI LUN */
1327 uint8_t initiator_id;
1328 uint8_t reserved_3;
1329 uint8_t target_id;
1330 uint32_t option_flags;
1331 uint8_t status;
1332 uint8_t scsi_status;
1333 uint8_t tag_value; /* Received queue tag message value */
1334 uint8_t tag_type; /* Received queue tag message type */
1335 uint32_t transfer_length;
1336 uint32_t residual;
1337 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
1338 uint16_t dseg_count; /* Data segment count. */
1339 uint32_t dseg_0_address; /* Data segment 0 address. */
1340 uint32_t dseg_0_length; /* Data segment 0 length. */
1341 uint32_t dseg_1_address; /* Data segment 1 address. */
1342 uint16_t dseg_1_length; /* Data segment 1 length. */
1343 uint8_t sense_data[18];
1344 }ctio_ret_entry_t;
1345
1346 /*
1347 * ISP queue - CTIO A64 entry structure definition.
1348 */
1349 typedef struct
1350 {
1351 uint8_t entry_type; /* Entry type. */
1352 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */
1353 uint8_t entry_count; /* Entry count. */
1354 uint8_t reserved_1;
1355 uint8_t entry_status; /* Entry Status. */
1356 uint32_t reserved_2;
1357 uint8_t lun; /* SCSI LUN */
1358 uint8_t initiator_id;
1359 uint8_t reserved_3;
1360 uint8_t target_id;
1361 uint32_t option_flags;
1362 uint8_t status;
1363 uint8_t scsi_status;
1364 uint8_t tag_value; /* Received queue tag message value */
1365 uint8_t tag_type; /* Received queue tag message type */
1366 uint32_t transfer_length;
1367 uint32_t residual;
1368 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
1369 uint16_t dseg_count; /* Data segment count. */
1370 uint32_t reserved_4[2];
1371 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1372 uint32_t dseg_0_length; /* Data segment 0 length. */
1373 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1374 uint32_t dseg_1_length; /* Data segment 1 length. */
1375 }ctio_a64_entry_t;
1376
1377 /*
1378 * ISP queue - CTIO returned entry structure definition.
1379 */
1380 typedef struct
1381 {
1382 uint8_t entry_type; /* Entry type. */
1383 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */
1384 uint8_t entry_count; /* Entry count. */
1385 uint8_t reserved_1;
1386 uint8_t entry_status; /* Entry Status. */
1387 uint32_t reserved_2;
1388 uint8_t lun; /* SCSI LUN */
1389 uint8_t initiator_id;
1390 uint8_t reserved_3;
1391 uint8_t target_id;
1392 uint32_t option_flags;
1393 uint8_t status;
1394 uint8_t scsi_status;
1395 uint8_t tag_value; /* Received queue tag message value */
1396 uint8_t tag_type; /* Received queue tag message type */
1397 uint32_t transfer_length;
1398 uint32_t residual;
1399 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */
1400 uint16_t dseg_count; /* Data segment count. */
1401 uint16_t reserved_4[7];
1402 uint8_t sense_data[18];
1403 }ctio_a64_ret_entry_t;
1404
1405 /*
1406 * ISP request and response queue entry sizes
1407 */
1408 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1409 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1410
1411 /*
1412 * ISP status entry - completion status definitions.
1413 */
1414 #define CS_COMPLETE 0x0 /* No errors */
1415 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1416 #define CS_DMA 0x2 /* A DMA direction error. */
1417 #define CS_TRANSPORT 0x3 /* Transport error. */
1418 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1419 #define CS_ABORTED 0x5 /* System aborted command. */
1420 #define CS_TIMEOUT 0x6 /* Timeout error. */
1421 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1422 #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */
1423 #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */
1424 #define CS_BAD_MSG 0xA /* Bad msg after status phase. */
1425 #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */
1426 #define CS_EXTENDED_ID 0xC /* Extended ID failed. */
1427 #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */
1428 #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */
1429 #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */
1430 #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */
1431 #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */
1432 #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */
1433 #define CS_ID_MSG 0x13 /* Target rejected ID msg. */
1434 #define CS_FREE 0x14 /* Unexpected bus free. */
1435 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1436 #define CS_TRANACTION_1 0x18 /* Transaction error 1 */
1437 #define CS_TRANACTION_2 0x19 /* Transaction error 2 */
1438 #define CS_TRANACTION_3 0x1a /* Transaction error 3 */
1439 #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */
1440 #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */
1441 #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */
1442 #define CS_ARS_FAILED 0x1e /* ARS failed */
1443 #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */
1444 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1445 #define CS_UNKNOWN 0x81 /* Driver defined */
1446 #define CS_RETRY 0x82 /* Driver defined */
1447
1448 /*
1449 * ISP status entry - SCSI status byte bit definitions.
1450 */
1451 #define SS_CHECK_CONDITION BIT_1
1452 #define SS_CONDITION_MET BIT_2
1453 #define SS_BUSY_CONDITION BIT_3
1454 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1455
1456 /*
1457 * ISP target entries - Option flags bit definitions.
1458 */
1459 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
1460 #define OF_DATA_IN BIT_6 /* Data in to initiator */
1461 /* (data from target to initiator) */
1462 #define OF_DATA_OUT BIT_7 /* Data out from initiator */
1463 /* (data from initiator to target) */
1464 #define OF_NO_DATA (BIT_7 | BIT_6)
1465 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */
1466 #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */
1467 #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */
1468 #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */
1469 #define OF_SSTS BIT_31 /* Send SCSI status */
1470
1471 #if QL1280_TARGET_MODE_SUPPORT
1472 /*
1473 * Target Read/Write buffer structure.
1474 */
1475 #define TARGET_DATA_OFFSET 4
1476 #define TARGET_DATA_SIZE 0x2000 /* 8K */
1477 #define TARGET_INQ_OFFSET (TARGET_DATA_OFFSET + TARGET_DATA_SIZE)
1478 #define TARGET_SENSE_SIZE 18
1479 #define TARGET_BUF_SIZE 36
1480
1481 typedef struct
1482 {
1483 uint8_t hdr[4];
1484 uint8_t data[TARGET_DATA_SIZE];
1485 struct ident inq;
1486 }tgt_t;
1487 #endif
1488
1489 /*
1490 * BUS parameters/settings structure
1491 */
1492 typedef struct
1493 {
1494 uint8_t id; /* Host adapter SCSI id */
1495 uint8_t bus_reset_delay; /* SCSI bus reset delay. */
1496 uint8_t failed_reset_count; /* number of time reset failed */
1497 uint8_t unused;
1498 uint16_t device_enables; /* Device enable bits. */
1499 uint16_t lun_disables; /* LUN disable bits. */
1500 uint16_t qtag_enables; /* Tag queue enables. */
1501 uint16_t hiwat; /* High water mark per device. */
1502 uint8_t reset_marker :1;
1503 uint8_t disable_scsi_reset :1;
1504 uint8_t scsi_bus_dead :1; /* SCSI Bus is Dead, when 5 back to back resets failed */
1505
1506 }bus_param_t;
1507
1508 /*
1509 * Linux Host Adapter structure
1510 */
1511 typedef struct scsi_qla_host
1512 {
1513 /* Linux adapter configuration data */
1514 struct Scsi_Host *host; /* pointer to host data */
1515 struct scsi_qla_host *next;
1516 device_reg_t *iobase; /* Base Memory-mapped I/O address */
1517 uint8_t pci_bus;
1518 uint8_t pci_device_fn;
1519 uint8_t devnum;
1520 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,95)
1521 struct pci_dev *pdev;
1522 #endif
1523 volatile unsigned char *mmpbase; /* memory mapped address */
1524 unsigned long host_no;
1525 unsigned long instance;
1526 uint8_t revision;
1527 uint8_t ports;
1528 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,1,0)
1529 spinlock_t spin_lock;
1530 #endif
1531 volatile unsigned char cpu_lock_count[NR_CPUS];
1532 unsigned long actthreads;
1533 unsigned long qthreads;
1534 unsigned long isr_count; /* Interrupt count */
1535 unsigned long spurious_int;
1536
1537 uint32_t device_id;
1538
1539 /* Outstandings ISP commands. */
1540 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
1541
1542 /* BUS configuration data */
1543 bus_param_t bus_settings[MAX_BUSES];
1544
1545 /* Device LUN queues. */
1546 scsi_lu_t *dev[MAX_EQ]; /* Logical unit queues */
1547
1548 #ifdef UNUSED
1549 /* Interrupt lock, and data */
1550 uint8_t intr_lock; /* Lock for interrupt locking */
1551 #endif
1552
1553 /* bottom half run queue */
1554 struct tq_struct run_qla_bh;
1555
1556 /* Received ISP mailbox data. */
1557 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1558
1559 #ifdef UNUSED
1560 /* ISP ring lock, rings, and indexes */
1561 uint8_t ring_lock; /* ISP ring lock */
1562 struct timer_list dev_timer[MAX_TARGETS];
1563 #endif
1564
1565 request_t req[REQUEST_ENTRY_CNT+1];
1566 response_t res[RESPONSE_ENTRY_CNT+1];
1567 unsigned long request_dma; /* Physical address. */
1568 request_t *request_ring; /* Base virtual address */
1569 request_t *request_ring_ptr; /* Current address. */
1570 uint16_t req_ring_index; /* Current index. */
1571 uint16_t req_q_cnt; /* Number of available entries. */
1572
1573 unsigned long response_dma; /* Physical address. */
1574 response_t *response_ring; /* Base virtual address */
1575 response_t *response_ring_ptr; /* Current address. */
1576 uint16_t rsp_ring_index; /* Current index. */
1577
1578 #if QL1280_TARGET_MODE_SUPPORT
1579 /* Target buffer and sense data. */
1580 uint32_t tbuf_dma; /* Physical address. */
1581 tgt_t *tbuf;
1582 uint32_t tsense_dma; /* Physical address. */
1583 uint8_t *tsense;
1584 #endif
1585
1586 #if WATCHDOGTIMER
1587 /* Watchdog queue, lock and total timer */
1588 uint8_t watchdog_q_lock; /* Lock for watchdog queue */
1589 srb_t *wdg_q_first; /* First job on watchdog queue */
1590 srb_t *wdg_q_last; /* Last job on watchdog queue */
1591 uint32_t total_timeout; /* Total timeout (quantum count) */
1592 uint32_t watchdogactive;
1593 #endif
1594
1595 srb_t *done_q_first; /* First job on done queue */
1596 srb_t *done_q_last; /* Last job on done queue */
1597
1598 volatile struct
1599 {
1600 uint32_t watchdog_enabled :1; /* 0 */
1601 uint32_t mbox_int :1; /* 1 */
1602 uint32_t mbox_busy :1; /* 2 */
1603 uint32_t online :1; /* 3 */
1604 uint32_t reset_marker :1; /* 4 */
1605 uint32_t isp_abort_needed :1; /* 5 */
1606 uint32_t pci_64bit_slot :1; /* 6 */
1607 uint32_t disable_host_adapter :1; /* 7 */
1608 uint32_t reset_active :1; /* 8 */
1609 uint32_t abort_isp_active :1; /* 9 */
1610 uint32_t disable_risc_code_load :1; /* 10 */
1611 uint32_t enable_64bit_addressing :1; /* 11 */
1612 #define QLA1280_IN_ISR_BIT 12
1613 uint32_t in_isr :1; /* 12 */
1614 uint32_t in_abort :1; /* 13 */
1615 uint32_t in_reset :1; /* 14 */
1616 uint32_t dpc :1; /* 15 */
1617 uint32_t dpc_sched :1; /* 16 */
1618 uint32_t interrupts_on :1; /* 17 */
1619 }flags;
1620
1621 }scsi_qla_host_t;
1622
1623 /*
1624 * Macros to help code, maintain, etc.
1625 */
1626 #define SUBDEV(b, t, l) ( (b << (MAX_T_BITS + MAX_L_BITS)) | (t << MAX_L_BITS) | l)
1627 #define LU_Q(ha, b, t, l) (ha->dev[SUBDEV(b, t, l)])
1628
1629 /*
1630 * Locking Macro Definitions
1631 *
1632 * LOCK/UNLOCK definitions are lock/unlock primitives for multi-processor
1633 * or spl/splx for uniprocessor.
1634 */
1635 #define QLA1280_HIER HBA_HIER_BASE /* Locking hierarchy base for hba */
1636
1637 #define QLA1280_WATCHDOG_Q_LOCK(ha, p)
1638 #define QLA1280_WATCHDOG_Q_UNLOCK(ha, p)
1639
1640 #define QLA1280_SCSILU_LOCK(q)
1641 #define QLA1280_SCSILU_UNLOCK(q)
1642
1643 #define QLA1280_INTR_LOCK(ha)
1644 #define QLA1280_INTR_UNLOCK(ha)
1645
1646 #define QLA1280_RING_LOCK(ha)
1647 #define QLA1280_RING_UNLOCK(ha)
1648
1649 #if defined(__cplusplus)
1650 }
1651 #endif
1652 /*
1653 * Linux - SCSI Driver Interface Function Prototypes.
1654 */
1655 int qla1280_proc_info ( char *, char **, off_t, int, int, int);
1656 const char * qla1280_info(struct Scsi_Host *host);
1657 int qla1280_detect(Scsi_Host_Template *);
1658 int qla1280_release(struct Scsi_Host *);
1659 const char * qla1280_info(struct Scsi_Host *);
1660 int qla1280_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *));
1661 int qla1280_abort(Scsi_Cmnd *);
1662 int qla1280_reset(Scsi_Cmnd *, unsigned int);
1663 int qla1280_biosparam(Disk *, kdev_t, int[]);
1664 void qla1280_intr_handler(int, void *, struct pt_regs *);
1665 void qla1280_setup(char *s, int *dummy);
1666 #if defined(__386__)
1667 # define QLA1280_BIOSPARAM qla1280_biosparam
1668 #else
1669 # define QLA1280_BIOSPARAM NULL
1670 #endif
1671
1672 /*
1673 * Scsi_Host_template (see hosts.h)
1674 * Device driver Interfaces to mid-level SCSI driver.
1675 */
1676 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,1,95)
1677 /* This interface is now obsolete !!! */
1678 #define QLA1280_LINUX_TEMPLATE { \
1679 next: NULL, \
1680 usage_count: NULL, \
1681 proc_dir: NULL, \
1682 proc_info: NULL, \
1683 name: "Qlogic ISP 1280", \
1684 detect: qla1280_detect, \
1685 release: qla1280_release, \
1686 info: qla1280_info, \
1687 command: NULL, \
1688 queuecommand: qla1280_queuecommand, \
1689 abort: qla1280_abort, \
1690 reset: qla1280_reset, \
1691 slave_attach: NULL, \
1692 bios_param: QLA1280_BIOSPARAM, \
1693 can_queue: 255, /* MAX_OUTSTANDING_COMMANDS */ \
1694 this_id: -1, /* scsi id of host adapter */ \
1695 sg_tablesize: SG_ALL, \
1696 cmd_per_lun: 3, /* max commands per lun */ \
1697 present: 0, /* number of 1280s present */ \
1698 unchecked_isa_dma: 0, /* no memeory DMA restrictions */ \
1699 use_clustering: ENABLE_CLUSTERING \
1700 }
1701 #else
1702
1703 #define QLA1280_LINUX_TEMPLATE { \
1704 next: NULL, \
1705 module: NULL, \
1706 proc_dir: NULL, \
1707 proc_info: qla1280_proc_info, \
1708 name: "Qlogic ISP 1280\1080", \
1709 detect: qla1280_detect, \
1710 release: qla1280_release, \
1711 info: qla1280_info, \
1712 ioctl: NULL, \
1713 command: NULL, \
1714 queuecommand: qla1280_queuecommand, \
1715 eh_strategy_handler: NULL, \
1716 eh_abort_handler: NULL, \
1717 eh_device_reset_handler: NULL, \
1718 eh_bus_reset_handler: NULL, \
1719 eh_host_reset_handler: NULL, \
1720 abort: qla1280_abort, \
1721 reset: qla1280_reset, \
1722 slave_attach: NULL, \
1723 bios_param: QLA1280_BIOSPARAM, \
1724 can_queue: 255, /* max simultaneous cmds */\
1725 this_id: -1, /* scsi id of host adapter */\
1726 sg_tablesize: SG_ALL, /* max scatter-gather cmds */\
1727 cmd_per_lun: 3, /* cmds per lun (linked cmds) */\
1728 present: 0, /* number of 7xxx's present */\
1729 unchecked_isa_dma: 0, /* no memory DMA restrictions */\
1730 use_clustering: ENABLE_CLUSTERING, \
1731 use_new_eh_code: 0, \
1732 emulated: 0 \
1733 }
1734 #endif
1735
1736
1737 #endif /* _IO_HBA_QLA1280_H */
1738
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