1 /* qlogicpti.h: Performance Technologies QlogicISP sbus card defines.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
4 */
5
6 #ifndef _QLOGICPTI_H
7 #define _QLOGICPTI_H
8
9 /* Qlogic/SBUS controller registers. */
10 #define SBUS_CFG1 0x006UL
11 #define SBUS_CTRL 0x008UL
12 #define SBUS_STAT 0x00aUL
13 #define SBUS_SEMAPHORE 0x00cUL
14 #define CMD_DMA_CTRL 0x022UL
15 #define DATA_DMA_CTRL 0x042UL
16 #define MBOX0 0x080UL
17 #define MBOX1 0x082UL
18 #define MBOX2 0x084UL
19 #define MBOX3 0x086UL
20 #define MBOX4 0x088UL
21 #define MBOX5 0x08aUL
22 #define CPU_CMD 0x214UL
23 #define CPU_ORIDE 0x224UL
24 #define CPU_PCTRL 0x272UL
25 #define CPU_PDIFF 0x276UL
26 #define RISC_PSR 0x420UL
27 #define RISC_MTREG 0x42EUL
28 #define HCCTRL 0x440UL
29
30 /* SCSI parameters for this driver. */
31 #define MAX_TARGETS 16
32 #define MAX_LUNS 8
33
34 /* With the qlogic interface, every queue slot can hold a SCSI
35 * command with up to 4 scatter/gather entries. If we need more
36 * than 4 entries, continuation entries can be used that hold
37 * another 7 entries each. Unlike for other drivers, this means
38 * that the maximum number of scatter/gather entries we can
39 * support at any given time is a function of the number of queue
40 * slots available. That is, host->can_queue and host->sg_tablesize
41 * are dynamic and _not_ independent. This all works fine because
42 * requests are queued serially and the scatter/gather limit is
43 * determined for each queue request anew.
44 */
45 #define QLOGICPTI_REQ_QUEUE_LEN 255 /* must be power of two - 1 */
46 #define QLOGICPTI_MAX_SG(ql) (4 + ((ql) > 0) ? 7*((ql) - 1) : 0)
47
48 #ifndef NULL
49 #define NULL (0)
50 #endif
51
52 int qlogicpti_detect(Scsi_Host_Template *);
53 int qlogicpti_release(struct Scsi_Host *);
54 const char * qlogicpti_info(struct Scsi_Host *);
55 int qlogicpti_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *));
56 int qlogicpti_queuecommand_slow(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *));
57 int qlogicpti_abort(Scsi_Cmnd *);
58 int qlogicpti_reset(Scsi_Cmnd *, unsigned int);
59
60 /* mailbox command complete status codes */
61 #define MBOX_COMMAND_COMPLETE 0x4000
62 #define INVALID_COMMAND 0x4001
63 #define HOST_INTERFACE_ERROR 0x4002
64 #define TEST_FAILED 0x4003
65 #define COMMAND_ERROR 0x4005
66 #define COMMAND_PARAM_ERROR 0x4006
67
68 /* async event status codes */
69 #define ASYNC_SCSI_BUS_RESET 0x8001
70 #define SYSTEM_ERROR 0x8002
71 #define REQUEST_TRANSFER_ERROR 0x8003
72 #define RESPONSE_TRANSFER_ERROR 0x8004
73 #define REQUEST_QUEUE_WAKEUP 0x8005
74 #define EXECUTION_TIMEOUT_RESET 0x8006
75
76 /* Am I fucking pedantic or what? */
77 struct Entry_header {
78 #ifdef __BIG_ENDIAN
79 u8 entry_cnt;
80 u8 entry_type;
81 u8 flags;
82 u8 sys_def_1;
83 #else /* __LITTLE_ENDIAN */
84 u8 entry_type;
85 u8 entry_cnt;
86 u8 sys_def_1;
87 u8 flags;
88 #endif
89 };
90
91 /* entry header type commands */
92 #define ENTRY_COMMAND 1
93 #define ENTRY_CONTINUATION 2
94 #define ENTRY_STATUS 3
95 #define ENTRY_MARKER 4
96 #define ENTRY_EXTENDED_COMMAND 5
97
98 /* entry header flag definitions */
99 #define EFLAG_CONTINUATION 1
100 #define EFLAG_BUSY 2
101 #define EFLAG_BAD_HEADER 4
102 #define EFLAG_BAD_PAYLOAD 8
103
104 struct dataseg {
105 u32 d_base;
106 u32 d_count;
107 };
108
109 struct Command_Entry {
110 struct Entry_header hdr;
111 u32 handle;
112 #ifdef __BIG_ENDIAN
113 u8 target_id;
114 u8 target_lun;
115 #else /* __LITTLE_ENDIAN */
116 u8 target_lun;
117 u8 target_id;
118 #endif
119 u16 cdb_length;
120 u16 control_flags;
121 u16 rsvd;
122 u16 time_out;
123 u16 segment_cnt;
124 u8 cdb[12];
125 struct dataseg dataseg[4];
126 };
127
128 /* command entry control flag definitions */
129 #define CFLAG_NODISC 0x01
130 #define CFLAG_HEAD_TAG 0x02
131 #define CFLAG_ORDERED_TAG 0x04
132 #define CFLAG_SIMPLE_TAG 0x08
133 #define CFLAG_TAR_RTN 0x10
134 #define CFLAG_READ 0x20
135 #define CFLAG_WRITE 0x40
136
137 struct Ext_Command_Entry {
138 struct Entry_header hdr;
139 u32 handle;
140 #ifdef __BIG_ENDIAN
141 u8 target_id;
142 u8 target_lun;
143 #else /* __LITTLE_ENDIAN */
144 u8 target_lun;
145 u8 target_id;
146 #endif
147 u16 cdb_length;
148 u16 control_flags;
149 u16 rsvd;
150 u16 time_out;
151 u16 segment_cnt;
152 u8 cdb[44];
153 };
154
155 struct Continuation_Entry {
156 struct Entry_header hdr;
157 u32 reserved;
158 struct dataseg dataseg[7];
159 };
160
161 struct Marker_Entry {
162 struct Entry_header hdr;
163 u32 reserved;
164 #ifdef __BIG_ENDIAN
165 u8 target_id;
166 u8 target_lun;
167 #else /* __LITTLE_ENDIAN */
168 u8 target_lun;
169 u8 target_id;
170 #endif
171 #ifdef __BIG_ENDIAN
172 u8 rsvd;
173 u8 modifier;
174 #else /* __LITTLE_ENDIAN */
175 u8 modifier;
176 u8 rsvd;
177 #endif
178 u8 rsvds[52];
179 };
180
181 /* marker entry modifier definitions */
182 #define SYNC_DEVICE 0
183 #define SYNC_TARGET 1
184 #define SYNC_ALL 2
185
186 struct Status_Entry {
187 struct Entry_header hdr;
188 u32 handle;
189 u16 scsi_status;
190 u16 completion_status;
191 u16 state_flags;
192 u16 status_flags;
193 u16 time;
194 u16 req_sense_len;
195 u32 residual;
196 u8 rsvd[8];
197 u8 req_sense_data[32];
198 };
199
200 /* status entry completion status definitions */
201 #define CS_COMPLETE 0x0000
202 #define CS_INCOMPLETE 0x0001
203 #define CS_DMA_ERROR 0x0002
204 #define CS_TRANSPORT_ERROR 0x0003
205 #define CS_RESET_OCCURRED 0x0004
206 #define CS_ABORTED 0x0005
207 #define CS_TIMEOUT 0x0006
208 #define CS_DATA_OVERRUN 0x0007
209 #define CS_COMMAND_OVERRUN 0x0008
210 #define CS_STATUS_OVERRUN 0x0009
211 #define CS_BAD_MESSAGE 0x000a
212 #define CS_NO_MESSAGE_OUT 0x000b
213 #define CS_EXT_ID_FAILED 0x000c
214 #define CS_IDE_MSG_FAILED 0x000d
215 #define CS_ABORT_MSG_FAILED 0x000e
216 #define CS_REJECT_MSG_FAILED 0x000f
217 #define CS_NOP_MSG_FAILED 0x0010
218 #define CS_PARITY_ERROR_MSG_FAILED 0x0011
219 #define CS_DEVICE_RESET_MSG_FAILED 0x0012
220 #define CS_ID_MSG_FAILED 0x0013
221 #define CS_UNEXP_BUS_FREE 0x0014
222 #define CS_DATA_UNDERRUN 0x0015
223 #define CS_BUS_RESET 0x001c
224
225 /* status entry state flag definitions */
226 #define SF_GOT_BUS 0x0100
227 #define SF_GOT_TARGET 0x0200
228 #define SF_SENT_CDB 0x0400
229 #define SF_TRANSFERRED_DATA 0x0800
230 #define SF_GOT_STATUS 0x1000
231 #define SF_GOT_SENSE 0x2000
232
233 /* status entry status flag definitions */
234 #define STF_DISCONNECT 0x0001
235 #define STF_SYNCHRONOUS 0x0002
236 #define STF_PARITY_ERROR 0x0004
237 #define STF_BUS_RESET 0x0008
238 #define STF_DEVICE_RESET 0x0010
239 #define STF_ABORTED 0x0020
240 #define STF_TIMEOUT 0x0040
241 #define STF_NEGOTIATION 0x0080
242
243 /* mailbox commands */
244 #define MBOX_NO_OP 0x0000
245 #define MBOX_LOAD_RAM 0x0001
246 #define MBOX_EXEC_FIRMWARE 0x0002
247 #define MBOX_DUMP_RAM 0x0003
248 #define MBOX_WRITE_RAM_WORD 0x0004
249 #define MBOX_READ_RAM_WORD 0x0005
250 #define MBOX_MAILBOX_REG_TEST 0x0006
251 #define MBOX_VERIFY_CHECKSUM 0x0007
252 #define MBOX_ABOUT_FIRMWARE 0x0008
253 #define MBOX_CHECK_FIRMWARE 0x000e
254 #define MBOX_INIT_REQ_QUEUE 0x0010
255 #define MBOX_INIT_RES_QUEUE 0x0011
256 #define MBOX_EXECUTE_IOCB 0x0012
257 #define MBOX_WAKE_UP 0x0013
258 #define MBOX_STOP_FIRMWARE 0x0014
259 #define MBOX_ABORT 0x0015
260 #define MBOX_ABORT_DEVICE 0x0016
261 #define MBOX_ABORT_TARGET 0x0017
262 #define MBOX_BUS_RESET 0x0018
263 #define MBOX_STOP_QUEUE 0x0019
264 #define MBOX_START_QUEUE 0x001a
265 #define MBOX_SINGLE_STEP_QUEUE 0x001b
266 #define MBOX_ABORT_QUEUE 0x001c
267 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
268 #define MBOX_GET_FIRMWARE_STATUS 0x001f
269 #define MBOX_GET_INIT_SCSI_ID 0x0020
270 #define MBOX_GET_SELECT_TIMEOUT 0x0021
271 #define MBOX_GET_RETRY_COUNT 0x0022
272 #define MBOX_GET_TAG_AGE_LIMIT 0x0023
273 #define MBOX_GET_CLOCK_RATE 0x0024
274 #define MBOX_GET_ACT_NEG_STATE 0x0025
275 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
276 #define MBOX_GET_SBUS_PARAMS 0x0027
277 #define MBOX_GET_TARGET_PARAMS 0x0028
278 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
279 #define MBOX_SET_INIT_SCSI_ID 0x0030
280 #define MBOX_SET_SELECT_TIMEOUT 0x0031
281 #define MBOX_SET_RETRY_COUNT 0x0032
282 #define MBOX_SET_TAG_AGE_LIMIT 0x0033
283 #define MBOX_SET_CLOCK_RATE 0x0034
284 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
285 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
286 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
287 #define MBOX_SET_TARGET_PARAMS 0x0038
288 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
289
290 struct host_param {
291 u_short initiator_scsi_id;
292 u_short bus_reset_delay;
293 u_short retry_count;
294 u_short retry_delay;
295 u_short async_data_setup_time;
296 u_short req_ack_active_negation;
297 u_short data_line_active_negation;
298 u_short data_dma_burst_enable;
299 u_short command_dma_burst_enable;
300 u_short tag_aging;
301 u_short selection_timeout;
302 u_short max_queue_depth;
303 };
304
305 /*
306 * Device Flags:
307 *
308 * Bit Name
309 * ---------
310 * 7 Disconnect Privilege
311 * 6 Parity Checking
312 * 5 Wide Data Transfers
313 * 4 Synchronous Data Transfers
314 * 3 Tagged Queuing
315 * 2 Automatic Request Sense
316 * 1 Stop Queue on Check Condition
317 * 0 Renegotiate on Error
318 */
319
320 struct dev_param {
321 u_short device_flags;
322 u_short execution_throttle;
323 u_short synchronous_period;
324 u_short synchronous_offset;
325 u_short device_enable;
326 u_short reserved; /* pad */
327 };
328
329 /*
330 * The result queue can be quite a bit smaller since continuation entries
331 * do not show up there:
332 */
333 #define RES_QUEUE_LEN 255 /* Must be power of two - 1 */
334 #define QUEUE_ENTRY_LEN 64
335
336 #define NEXT_REQ_PTR(wheee) (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN)
337 #define NEXT_RES_PTR(wheee) (((wheee) + 1) & RES_QUEUE_LEN)
338 #define PREV_REQ_PTR(wheee) (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN)
339 #define PREV_RES_PTR(wheee) (((wheee) - 1) & RES_QUEUE_LEN)
340
341 struct pti_queue_entry {
342 char __opaque[QUEUE_ENTRY_LEN];
343 };
344
345 /* Software state for the driver. */
346 struct qlogicpti {
347 /* These are the hot elements in the cache, so they come first. */
348 spinlock_t lock; /* Driver mutex */
349 unsigned long qregs; /* Adapter registers */
350 struct pti_queue_entry *res_cpu; /* Ptr to RESPONSE bufs (CPU) */
351 struct pti_queue_entry *req_cpu; /* Ptr to REQUEST bufs (CPU) */
352
353 u_int req_in_ptr; /* index of next request slot */
354 u_int res_out_ptr; /* index of next result slot */
355 long send_marker; /* must we send a marker? */
356 struct sbus_dev *sdev;
357 unsigned long __pad;
358
359 int cmd_count[MAX_TARGETS];
360 unsigned long tag_ages[MAX_TARGETS];
361
362 /* The cmd->handler is only 32-bits, so that things work even on monster
363 * Ex000 sparc64 machines with >4GB of ram we just keep track of the
364 * scsi command pointers here. This is essentially what Matt Jacob does. -DaveM
365 */
366 Scsi_Cmnd *cmd_slots[QLOGICPTI_REQ_QUEUE_LEN + 1];
367
368 /* The rest of the elements are unimportant for performance. */
369 struct qlogicpti *next;
370 __u32 res_dvma; /* Ptr to RESPONSE bufs (DVMA)*/
371 __u32 req_dvma; /* Ptr to REQUEST bufs (DVMA) */
372 u_char fware_majrev, fware_minrev, fware_micrev;
373 struct Scsi_Host *qhost;
374 int qpti_id;
375 int scsi_id;
376 int prom_node;
377 char prom_name[64];
378 int irq;
379 char differential, ultra, clock;
380 unsigned char bursts;
381 struct host_param host_param;
382 struct dev_param dev_param[MAX_TARGETS];
383
384 unsigned long sreg;
385 #define SREG_TPOWER 0x80 /* State of termpwr */
386 #define SREG_FUSE 0x40 /* State of on board fuse */
387 #define SREG_PDISAB 0x20 /* Disable state for power on */
388 #define SREG_DSENSE 0x10 /* Sense for differential */
389 #define SREG_IMASK 0x0c /* Interrupt level */
390 #define SREG_SPMASK 0x03 /* Mask for switch pack */
391 unsigned char swsreg;
392 unsigned int
393 gotirq : 1, /* this instance got an irq */
394 is_pti : 1, /* Non-zero if this is a PTI board. */
395 sbits : 16; /* syncmode known bits */
396 };
397
398 /* How to twiddle them bits... */
399
400 /* SBUS config register one. */
401 #define SBUS_CFG1_EPAR 0x0100 /* Enable parity checking */
402 #define SBUS_CFG1_FMASK 0x00f0 /* Forth code cycle mask */
403 #define SBUS_CFG1_BENAB 0x0004 /* Burst dvma enable */
404 #define SBUS_CFG1_B64 0x0003 /* Enable 64byte bursts */
405 #define SBUS_CFG1_B32 0x0002 /* Enable 32byte bursts */
406 #define SBUS_CFG1_B16 0x0001 /* Enable 16byte bursts */
407 #define SBUS_CFG1_B8 0x0008 /* Enable 8byte bursts */
408
409 /* SBUS control register */
410 #define SBUS_CTRL_EDIRQ 0x0020 /* Enable Data DVMA Interrupts */
411 #define SBUS_CTRL_ECIRQ 0x0010 /* Enable Command DVMA Interrupts */
412 #define SBUS_CTRL_ESIRQ 0x0008 /* Enable SCSI Processor Interrupts */
413 #define SBUS_CTRL_ERIRQ 0x0004 /* Enable RISC Processor Interrupts */
414 #define SBUS_CTRL_GENAB 0x0002 /* Global Interrupt Enable */
415 #define SBUS_CTRL_RESET 0x0001 /* Soft Reset */
416
417 /* SBUS status register */
418 #define SBUS_STAT_DINT 0x0020 /* Data DVMA IRQ pending */
419 #define SBUS_STAT_CINT 0x0010 /* Command DVMA IRQ pending */
420 #define SBUS_STAT_SINT 0x0008 /* SCSI Processor IRQ pending */
421 #define SBUS_STAT_RINT 0x0004 /* RISC Processor IRQ pending */
422 #define SBUS_STAT_GINT 0x0002 /* Global IRQ pending */
423
424 /* SBUS semaphore register */
425 #define SBUS_SEMAPHORE_STAT 0x0002 /* Semaphore status bit */
426 #define SBUS_SEMAPHORE_LCK 0x0001 /* Semaphore lock bit */
427
428 /* DVMA control register */
429 #define DMA_CTRL_CSUSPEND 0x0010 /* DMA channel suspend */
430 #define DMA_CTRL_CCLEAR 0x0008 /* DMA channel clear and reset */
431 #define DMA_CTRL_FCLEAR 0x0004 /* DMA fifo clear */
432 #define DMA_CTRL_CIRQ 0x0002 /* DMA irq clear */
433 #define DMA_CTRL_DMASTART 0x0001 /* DMA transfer start */
434
435 /* SCSI processor override register */
436 #define CPU_ORIDE_ETRIG 0x8000 /* External trigger enable */
437 #define CPU_ORIDE_STEP 0x4000 /* Single step mode enable */
438 #define CPU_ORIDE_BKPT 0x2000 /* Breakpoint reg enable */
439 #define CPU_ORIDE_PWRITE 0x1000 /* SCSI pin write enable */
440 #define CPU_ORIDE_OFORCE 0x0800 /* Force outputs on */
441 #define CPU_ORIDE_LBACK 0x0400 /* SCSI loopback enable */
442 #define CPU_ORIDE_PTEST 0x0200 /* Parity test enable */
443 #define CPU_ORIDE_TENAB 0x0100 /* SCSI pins tristate enable */
444 #define CPU_ORIDE_TPINS 0x0080 /* SCSI pins enable */
445 #define CPU_ORIDE_FRESET 0x0008 /* FIFO reset */
446 #define CPU_ORIDE_CTERM 0x0004 /* Command terminate */
447 #define CPU_ORIDE_RREG 0x0002 /* Reset SCSI processor regs */
448 #define CPU_ORIDE_RMOD 0x0001 /* Reset SCSI processor module */
449
450 /* SCSI processor commands */
451 #define CPU_CMD_BRESET 0x300b /* Reset SCSI bus */
452
453 /* SCSI processor pin control register */
454 #define CPU_PCTRL_PVALID 0x8000 /* Phase bits are valid */
455 #define CPU_PCTRL_PHI 0x0400 /* Parity bit high */
456 #define CPU_PCTRL_PLO 0x0200 /* Parity bit low */
457 #define CPU_PCTRL_REQ 0x0100 /* REQ bus signal */
458 #define CPU_PCTRL_ACK 0x0080 /* ACK bus signal */
459 #define CPU_PCTRL_RST 0x0040 /* RST bus signal */
460 #define CPU_PCTRL_BSY 0x0020 /* BSY bus signal */
461 #define CPU_PCTRL_SEL 0x0010 /* SEL bus signal */
462 #define CPU_PCTRL_ATN 0x0008 /* ATN bus signal */
463 #define CPU_PCTRL_MSG 0x0004 /* MSG bus signal */
464 #define CPU_PCTRL_CD 0x0002 /* CD bus signal */
465 #define CPU_PCTRL_IO 0x0001 /* IO bus signal */
466
467 /* SCSI processor differential pins register */
468 #define CPU_PDIFF_SENSE 0x0200 /* Differential sense */
469 #define CPU_PDIFF_MODE 0x0100 /* Differential mode */
470 #define CPU_PDIFF_OENAB 0x0080 /* Outputs enable */
471 #define CPU_PDIFF_PMASK 0x007c /* Differential control pins */
472 #define CPU_PDIFF_TGT 0x0002 /* Target mode enable */
473 #define CPU_PDIFF_INIT 0x0001 /* Initiator mode enable */
474
475 /* RISC processor status register */
476 #define RISC_PSR_FTRUE 0x8000 /* Force true */
477 #define RISC_PSR_LCD 0x4000 /* Loop counter shows done status */
478 #define RISC_PSR_RIRQ 0x2000 /* RISC irq status */
479 #define RISC_PSR_TOFLOW 0x1000 /* Timer overflow (rollover) */
480 #define RISC_PSR_AOFLOW 0x0800 /* Arithmetic overflow */
481 #define RISC_PSR_AMSB 0x0400 /* Arithmetic big endian */
482 #define RISC_PSR_ACARRY 0x0200 /* Arithmetic carry */
483 #define RISC_PSR_AZERO 0x0100 /* Arithmetic zero */
484 #define RISC_PSR_ULTRA 0x0020 /* Ultra mode */
485 #define RISC_PSR_DIRQ 0x0010 /* DVMA interrupt */
486 #define RISC_PSR_SIRQ 0x0008 /* SCSI processor interrupt */
487 #define RISC_PSR_HIRQ 0x0004 /* Host interrupt */
488 #define RISC_PSR_IPEND 0x0002 /* Interrupt pending */
489 #define RISC_PSR_FFALSE 0x0001 /* Force false */
490
491 /* RISC processor memory timing register */
492 #define RISC_MTREG_P1DFLT 0x1200 /* Default read/write timing, pg1 */
493 #define RISC_MTREG_P0DFLT 0x0012 /* Default read/write timing, pg0 */
494 #define RISC_MTREG_P1ULTRA 0x2300 /* Ultra-mode rw timing, pg1 */
495 #define RISC_MTREG_P0ULTRA 0x0023 /* Ultra-mode rw timing, pg0 */
496
497 /* Host command/ctrl register */
498 #define HCCTRL_NOP 0x0000 /* CMD: No operation */
499 #define HCCTRL_RESET 0x1000 /* CMD: Reset RISC cpu */
500 #define HCCTRL_PAUSE 0x2000 /* CMD: Pause RISC cpu */
501 #define HCCTRL_REL 0x3000 /* CMD: Release paused RISC cpu */
502 #define HCCTRL_STEP 0x4000 /* CMD: Single step RISC cpu */
503 #define HCCTRL_SHIRQ 0x5000 /* CMD: Set host irq */
504 #define HCCTRL_CHIRQ 0x6000 /* CMD: Clear host irq */
505 #define HCCTRL_CRIRQ 0x7000 /* CMD: Clear RISC cpu irq */
506 #define HCCTRL_BKPT 0x8000 /* CMD: Breakpoint enables change */
507 #define HCCTRL_TMODE 0xf000 /* CMD: Enable test mode */
508 #define HCCTRL_HIRQ 0x0080 /* Host IRQ pending */
509 #define HCCTRL_RRIP 0x0040 /* RISC cpu reset in happening now */
510 #define HCCTRL_RPAUSED 0x0020 /* RISC cpu is paused now */
511 #define HCCTRL_EBENAB 0x0010 /* External breakpoint enable */
512 #define HCCTRL_B1ENAB 0x0008 /* Breakpoint 1 enable */
513 #define HCCTRL_B0ENAB 0x0004 /* Breakpoint 0 enable */
514
515 #define QLOGICPTI { \
516 detect: qlogicpti_detect, \
517 release: qlogicpti_release, \
518 info: qlogicpti_info, \
519 queuecommand: qlogicpti_queuecommand_slow, \
520 abort: qlogicpti_abort, \
521 reset: qlogicpti_reset, \
522 can_queue: QLOGICPTI_REQ_QUEUE_LEN, \
523 this_id: 7, \
524 sg_tablesize: QLOGICPTI_MAX_SG(QLOGICPTI_REQ_QUEUE_LEN), \
525 cmd_per_lun: 1, \
526 use_clustering: ENABLE_CLUSTERING, \
527 use_new_eh_code: 0 \
528 }
529
530 /* For our interrupt engine. */
531 #define for_each_qlogicpti(qp) \
532 for((qp) = qptichain; (qp); (qp) = (qp)->next)
533
534 #endif /* !(_QLOGICPTI_H) */
535
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