1 #ifndef _SIM710_H
2 #define _SIM710_H
3
4 /*
5 * sim710.h - Copyright (C) 1999 Richard Hirst
6 */
7
8 #include <linux/types.h>
9
10 int sim710_detect(Scsi_Host_Template *);
11 int sim710_command(Scsi_Cmnd *);
12 int sim710_queuecommand(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
13 int sim710_abort(Scsi_Cmnd * SCpnt);
14 int sim710_bus_reset(Scsi_Cmnd * SCpnt);
15 int sim710_dev_reset(Scsi_Cmnd * SCpnt);
16 int sim710_host_reset(Scsi_Cmnd * SCpnt);
17 int sim710_biosparam(Disk *, kdev_t, int*);
18 #ifdef MODULE
19 int sim710_release(struct Scsi_Host *);
20 #else
21 #define sim710_release NULL
22 #endif
23
24 #include <scsi/scsicam.h>
25
26 #define SIM710_SCSI { proc_name: "sim710", \
27 name: "Simple 53c710", \
28 detect: sim710_detect, \
29 release: sim710_release, \
30 queuecommand: sim710_queuecommand, \
31 eh_abort_handler: sim710_abort, \
32 eh_device_reset_handler: sim710_dev_reset, \
33 eh_bus_reset_handler: sim710_bus_reset, \
34 eh_host_reset_handler: sim710_host_reset, \
35 bios_param: scsicam_bios_param, \
36 can_queue: 8, \
37 this_id: 7, \
38 sg_tablesize: 128, \
39 cmd_per_lun: 1, \
40 use_clustering: DISABLE_CLUSTERING, \
41 use_new_eh_code: 1}
42
43 #ifndef HOSTS_C
44
45 #ifdef __BIG_ENDIAN
46 #define bE 3 /* 0 for little endian, 3 for big endian */
47 #else
48 #define bE 0
49 #endif
50
51 /* SCSI control 0 rw, default = 0xc0 */
52 #define SCNTL0_REG (0x00^bE)
53 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
54 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
55 #define SCNTL0_STRT 0x20 /* Start Sequence */
56 #define SCNTL0_WATN 0x10 /* Select with ATN */
57 #define SCNTL0_EPC 0x08 /* Enable parity checking */
58 /* Bit 2 is reserved on 800 series chips */
59 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
60 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
61 #define SCNTL0_TRG 0x01 /* Target mode */
62
63 /* SCSI control 1 rw, default = 0x00 */
64
65 #define SCNTL1_REG (0x01^bE)
66 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
67 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
68 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
69 and reselection */
70 #define SCNTL1_CON 0x10 /* Connected */
71 #define SCNTL1_RST 0x08 /* SCSI RST/ */
72 #define SCNTL1_AESP 0x04 /* Force bad parity */
73 #define SCNTL1_SND_700 0x02 /* Start SCSI send */
74 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
75 arbitration immediately after
76 busfree is detected */
77 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
78 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
79
80 /* SCSI control 2 rw, */
81
82 #define SCNTL2_REG_800 (0x02^bE)
83 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
84
85 /* SCSI control 3 rw */
86
87 #define SCNTL3_REG_800 (0x03^bE)
88 #define SCNTL3_800_SCF_SHIFT 4
89 #define SCNTL3_800_SCF_MASK 0x70
90 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
91 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
92 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
93 /* 0x20 = SCLK/1.5
94 0x30 = SCLK/2
95 0x40 = SCLK/3 */
96
97 #define SCNTL3_800_CCF_SHIFT 0
98 #define SCNTL3_800_CCF_MASK 0x07
99 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
100 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
101 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
102 0x03 37.51 - 50
103 0x04 50.01 - 66 */
104
105 /*
106 * SCSI destination ID rw - the appropriate bit is set for the selected
107 * target ID. This is written by the SCSI SCRIPTS processor.
108 * default = 0x00
109 */
110 #define SDID_REG_700 (0x02^bE)
111 #define SDID_REG_800 (0x06^bE)
112
113 #define GP_REG_800 (0x07^bE) /* General purpose IO */
114 #define GP_800_IO1 0x02
115 #define GP_800_IO2 0x01
116
117 /* SCSI interrupt enable rw, default = 0x00 */
118 #define SIEN_REG_700 (0x03^bE)
119 #define SIEN0_REG_800 (0x40^bE)
120 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
121 #define SIEN_FC 0x40 /* Function complete */
122 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
123 #define SIEN_800_SEL 0x20 /* Selected */
124 #define SIEN_700_SEL 0x10 /* Selected or reselected */
125 #define SIEN_800_RESEL 0x10 /* Reselected */
126 #define SIEN_SGE 0x08 /* SCSI gross error */
127 #define SIEN_UDC 0x04 /* Unexpected disconnect */
128 #define SIEN_RST 0x02 /* SCSI RST/ received */
129 #define SIEN_PAR 0x01 /* Parity error */
130
131 /*
132 * SCSI chip ID rw
133 * NCR53c700 :
134 * When arbitrating, the highest bit is used, when reselection or selection
135 * occurs, the chip responds to all IDs for which a bit is set.
136 * default = 0x00
137 */
138 #define SCID_REG (0x04^bE)
139 /* Bit 7 is reserved on 800 series chips */
140 #define SCID_800_RRE 0x40 /* Enable response to reselection */
141 #define SCID_800_SRE 0x20 /* Enable response to selection */
142 /* Bits four and three are reserved on 800 series chips */
143 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
144
145 /* SCSI transfer rw, default = 0x00 */
146 #define SXFER_REG (0x05^bE)
147 #define SXFER_DHP 0x80 /* Disable halt on parity */
148
149 #define SXFER_TP2 0x40 /* Transfer period msb */
150 #define SXFER_TP1 0x20
151 #define SXFER_TP0 0x10 /* lsb */
152 #define SXFER_TP_MASK 0x70
153 /* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
154 #define SXFER_TP_SHIFT 5
155 #define SXFER_TP_4 0x00 /* Divisors */
156 #define SXFER_TP_5 0x10<<1
157 #define SXFER_TP_6 0x20<<1
158 #define SXFER_TP_7 0x30<<1
159 #define SXFER_TP_8 0x40<<1
160 #define SXFER_TP_9 0x50<<1
161 #define SXFER_TP_10 0x60<<1
162 #define SXFER_TP_11 0x70<<1
163
164 #define SXFER_MO3 0x08 /* Max offset msb */
165 #define SXFER_MO2 0x04
166 #define SXFER_MO1 0x02
167 #define SXFER_MO0 0x01 /* lsb */
168 #define SXFER_MO_MASK 0x0f
169 #define SXFER_MO_SHIFT 0
170
171 /*
172 * SCSI output data latch rw
173 * The contents of this register are driven onto the SCSI bus when
174 * the Assert Data Bus bit of the SCNTL1 register is set and
175 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
176 */
177 #define SODL_REG_700 (0x06^bE)
178 #define SODL_REG_800 (0x54^bE)
179
180
181 /*
182 * SCSI output control latch rw, default = 0
183 * Note that when the chip is being manually programmed as an initiator,
184 * the MSG, CD, and IO bits must be set correctly for the phase the target
185 * is driving the bus in. Otherwise no data transfer will occur due to
186 * phase mismatch.
187 */
188
189 #define SOCL_REG (0x07^bE)
190 #define SOCL_REQ 0x80 /* REQ */
191 #define SOCL_ACK 0x40 /* ACK */
192 #define SOCL_BSY 0x20 /* BSY */
193 #define SOCL_SEL 0x10 /* SEL */
194 #define SOCL_ATN 0x08 /* ATN */
195 #define SOCL_MSG 0x04 /* MSG */
196 #define SOCL_CD 0x02 /* C/D */
197 #define SOCL_IO 0x01 /* I/O */
198
199 /*
200 * SCSI first byte received latch ro
201 * This register contains the first byte received during a block MOVE
202 * SCSI SCRIPTS instruction, including
203 *
204 * Initiator mode Target mode
205 * Message in Command
206 * Status Message out
207 * Data in Data out
208 *
209 * It also contains the selecting or reselecting device's ID and our
210 * ID.
211 *
212 * Note that this is the register the various IF conditionals can
213 * operate on.
214 */
215 #define SFBR_REG (0x08^bE)
216
217 /*
218 * SCSI input data latch ro
219 * In initiator mode, data is latched into this register on the rising
220 * edge of REQ/. In target mode, data is latched on the rising edge of
221 * ACK/
222 */
223 #define SIDL_REG_700 (0x09^bE)
224 #define SIDL_REG_800 (0x50^bE)
225
226 /*
227 * SCSI bus data lines ro
228 * This register reflects the instantaneous status of the SCSI data
229 * lines. Note that SCNTL0 must be set to disable parity checking,
230 * otherwise reading this register will latch new parity.
231 */
232 #define SBDL_REG_700 (0x0a^bE)
233 #define SBDL_REG_800 (0x58^bE)
234
235 #define SSID_REG_800 (0x0a^bE)
236 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
237 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
238
239
240
241 /*
242 * SCSI bus control lines rw,
243 * instantaneous readout of control lines
244 */
245 #define SBCL_REG (0x0b^bE)
246 #define SBCL_REQ 0x80 /* REQ ro */
247 #define SBCL_ACK 0x40 /* ACK ro */
248 #define SBCL_BSY 0x20 /* BSY ro */
249 #define SBCL_SEL 0x10 /* SEL ro */
250 #define SBCL_ATN 0x08 /* ATN ro */
251 #define SBCL_MSG 0x04 /* MSG ro */
252 #define SBCL_CD 0x02 /* C/D ro */
253 #define SBCL_IO 0x01 /* I/O ro */
254 #define SBCL_PHASE_CMDOUT SBCL_CD
255 #define SBCL_PHASE_DATAIN SBCL_IO
256 #define SBCL_PHASE_DATAOUT 0
257 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
258 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
259 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
260 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
261 /*
262 * Synchronous SCSI Clock Control bits
263 * 0 - set by DCNTL
264 * 1 - SCLK / 1.0
265 * 2 - SCLK / 1.5
266 * 3 - SCLK / 2.0
267 */
268 #define SBCL_SSCF1 0x02 /* wo, -66 only */
269 #define SBCL_SSCF0 0x01 /* wo, -66 only */
270 #define SBCL_SSCF_MASK 0x03
271
272 /*
273 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
274 * insure that 10 clocks elapse between the two
275 */
276 /* DMA status ro */
277 #define DSTAT_REG (0x0c^bE)
278 #define DSTAT_DFE 0x80 /* DMA FIFO empty */
279 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
280 #define DSTAT_BF 0x20 /* Bus Fault */
281 #define DSTAT_ABRT 0x10 /* Aborted - set on error */
282 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
283 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
284 set when INT instruction is
285 executed */
286 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
287 #define DSTAT_OPC 0x01 /* Illegal instruction */
288 #define DSTAT_IID 0x01 /* Same thing, different name */
289
290
291 #define SSTAT0_REG (0x0d^bE) /* SCSI status 0 ro */
292 #define SIST0_REG_800 (0x42^bE) /* SCSI status 0 ro */
293 #define SSTAT0_MA 0x80 /* ini : phase mismatch,
294 * tgt : ATN/ asserted
295 */
296 #define SSTAT0_CMP 0x40 /* function complete */
297 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
298 #define SSTAT0_800_SEL 0x20 /* Selected */
299 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
300 #define SIST0_800_RSL 0x10 /* Reselected */
301 #define SSTAT0_SGE 0x08 /* SCSI gross error */
302 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
303 #define SSTAT0_RST 0x02 /* SCSI RST/ received */
304 #define SSTAT0_PAR 0x01 /* Parity error */
305
306 #define SSTAT1_REG (0x0e^bE) /* SCSI status 1 ro */
307 #define SSTAT1_ILF 0x80 /* SIDL full */
308 #define SSTAT1_ORF 0x40 /* SODR full */
309 #define SSTAT1_OLF 0x20 /* SODL full */
310 #define SSTAT1_AIP 0x10 /* Arbitration in progress */
311 #define SSTAT1_LOA 0x08 /* Lost arbitration */
312 #define SSTAT1_WOA 0x04 /* Won arbitration */
313 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
314 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
315
316 #define SSTAT2_REG (0x0f^bE) /* SCSI status 2 ro */
317 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
318 #define SSTAT2_FF2 0x40 /* data FIFO */
319 #define SSTAT2_FF1 0x20
320 #define SSTAT2_FF0 0x10
321 #define SSTAT2_FF_MASK 0xf0
322 #define SSTAT2_FF_SHIFT 4
323
324 /*
325 * Latched signals, latched on the leading edge of REQ/ for initiators,
326 * ACK/ for targets.
327 */
328 #define SSTAT2_SDP 0x08 /* SDP */
329 #define SSTAT2_MSG 0x04 /* MSG */
330 #define SSTAT2_CD 0x02 /* C/D */
331 #define SSTAT2_IO 0x01 /* I/O */
332 #define SSTAT2_PHASE_CMDOUT SSTAT2_CD
333 #define SSTAT2_PHASE_DATAIN SSTAT2_IO
334 #define SSTAT2_PHASE_DATAOUT 0
335 #define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
336 #define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG)
337 #define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO)
338 #define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
339
340
341 #define DSA_REG 0x10 /* DATA structure address */
342
343 #define CTEST0_REG_700 (0x14^bE) /* Chip test 0 ro */
344 #define CTEST0_REG_800 (0x18^bE) /* Chip test 0 ro */
345 /* 0x80 - 0x04 are reserved */
346 #define CTEST0_700_RTRG 0x02 /* Real target mode */
347 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
348 * SCSI bus to host, 0 =
349 * host to SCSI.
350 */
351
352 #define CTEST1_REG_700 (0x15^bE) /* Chip test 1 ro */
353 #define CTEST1_REG_800 (0x19^bE) /* Chip test 1 ro */
354 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
355 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
356 #define CTEST1_FMT1 0x20
357 #define CTEST1_FMT0 0x10
358
359 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
360 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
361 #define CTEST1_FFL1 0x02
362 #define CTEST1_FFL0 0x01
363
364 #define CTEST2_REG_700 (0x16^bE) /* Chip test 2 ro */
365 #define CTEST2_REG_800 (0x1a^bE) /* Chip test 2 ro */
366
367 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
368 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
369 Reading this register clears */
370 #define CTEST2_800_CIO 0x20 /* Configured as IO */.
371 #define CTEST2_800_CM 0x10 /* Configured as memory */
372
373 /* 0x80 - 0x40 are reserved on 700 series chips */
374 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
375 * As an initiator, this bit is
376 * one when the synchronous offset
377 * is zero, as a target this bit
378 * is one when the synchronous
379 * offset is at the maximum
380 * defined in SXFER
381 */
382 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
383 * reading CTEST3 unloads a byte
384 * from the FIFO and sets this
385 */
386 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
387 * reading CTEST6 unloads a byte
388 * from the FIFO and sets this
389 */
390 #define CTEST2_TEOP 0x04 /* SCSI true end of process,
391 * indicates a totally finished
392 * transfer
393 */
394 #define CTEST2_DREQ 0x02 /* Data request signal */
395 /* 0x01 is reserved on 700 series chips */
396 #define CTEST2_800_DACK 0x01
397
398 /*
399 * Chip test 3 ro
400 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
401 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
402 * error results if a read is attempted on this register. Also note
403 * that 16 and 32 bit reads of this register will cause corruption.
404 */
405 #define CTEST3_REG_700 (0x17^bE)
406 /* Chip test 3 rw */
407 #define CTEST3_REG_800 (0x1b^bE)
408 #define CTEST3_800_V3 0x80 /* Chip revision */
409 #define CTEST3_800_V2 0x40
410 #define CTEST3_800_V1 0x20
411 #define CTEST3_800_V0 0x10
412 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
413 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
414 #define CTEST3_800_FM 0x02 /* Fetch mode pin */
415 /* bit 0 is reserved on 800 series chips */
416
417 #define CTEST4_REG_400 (0x18^bE) /* Chip test 4 rw */
418 #define CTEST4_REG_800 (0x21^bE) /* Chip test 4 rw */
419 /* 0x80 is reserved on 700 series chips */
420 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
421 #define CTEST4_ZMOD 0x40 /* High impedance mode */
422 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
423 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
424 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
425 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
426 * redirects writes from SODL
427 * to the SCSI FIFO.
428 */
429 #define CTEST4_800_MPEE 0x08 /* Enable parity checking
430 during master cycles on PCI
431 bus */
432
433 /*
434 * These bits send the contents of the CTEST6 register to the appropriate
435 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
436 * the high bit means the low two bits select the byte lane.
437 */
438 #define CTEST4_FBL2 0x04
439 #define CTEST4_FBL1 0x02
440 #define CTEST4_FBL0 0x01
441 #define CTEST4_FBL_MASK 0x07
442 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
443 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
444 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
445 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
446 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
447
448
449 #define CTEST5_REG_700 (0x19^bE) /* Chip test 5 rw */
450 #define CTEST5_REG_800 (0x22^bE) /* Chip test 5 rw */
451 /*
452 * Clock Address Incrementor. When set, it increments the
453 * DNAD register to the next bus size boundary. It automatically
454 * resets itself when the operation is complete.
455 */
456 #define CTEST5_ADCK 0x80
457 /*
458 * Clock Byte Counter. When set, it decrements the DBC register to
459 * the next bus size boundary.
460 */
461 #define CTEST5_BBCK 0x40
462 /*
463 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
464 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
465 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
466 * be cleared when a synchronous transfer fails. When written, it is
467 * automatically cleared after the SCSI synchronous offset counter is
468 * reset.
469 */
470 /* Bit 5 is reserved on 800 series chips */
471 #define CTEST5_700_ROFF 0x20
472 /*
473 * Master Control for Set or Reset pulses. When 1, causes the low
474 * four bits of register to set when set, 0 causes the low bits to
475 * clear when set.
476 */
477 #define CTEST5_MASR 0x10
478 #define CTEST5_DDIR 0x08 /* DMA direction */
479 /*
480 * Bits 2-0 are reserved on 800 series chips
481 */
482 #define CTEST5_700_EOP 0x04 /* End of process */
483 #define CTEST5_700_DREQ 0x02 /* Data request */
484 #define CTEST5_700_DACK 0x01 /* Data acknowledge */
485
486 /*
487 * Chip test 6 rw - writing to this register writes to the byte
488 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
489 * register.
490 */
491 #define CTEST6_REG_700 (0x1a^bE)
492 #define CTEST6_REG_800 (0x23^bE)
493
494 #define CTEST7_REG (0x1b^bE) /* Chip test 7 rw */
495 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
496 #define CTEST7_10_SC1 0x40 /* Snoop control bits */
497 #define CTEST7_10_SC0 0x20
498 #define CTEST7_10_SC_MASK 0x60
499 #define CTEST7_STD 0x10 /* Selection timeout disable */
500 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
501 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
502 #define CTEST7_10_TT1 0x02 /* Transfer type */
503 #define CTEST7_DIFF 0x01 /* Differential mode */
504
505 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
506
507
508 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
509
510 #define DFIFO_REG (0x20^bE) /* DMA FIFO rw */
511 /*
512 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
513 * moved into the CTEST8 register.
514 */
515 #define DFIFO_BO6 0x40
516 #define DFIFO_BO5 0x20
517 #define DFIFO_BO4 0x10
518 #define DFIFO_BO3 0x08
519 #define DFIFO_BO2 0x04
520 #define DFIFO_BO1 0x02
521 #define DFIFO_BO0 0x01
522 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
523
524 /*
525 * Interrupt status rw
526 * Note that this is the only register which can be read while SCSI
527 * SCRIPTS are being executed.
528 */
529 #define ISTAT_REG_700 (0x21^bE)
530 #define ISTAT_REG_800 (0x14^bE)
531 #define ISTAT_ABRT 0x80 /* Software abort, write
532 *1 to abort, wait for interrupt. */
533 #define ISTAT_10_SRST 0x40 /* software reset */
534 #define ISTAT_10_SIGP 0x20 /* signal script */
535 #define ISTAT_CON 0x08 /* 1 when connected */
536 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
537 #define ISTAT_700_PRE 0x04 /* Pointer register empty.
538 * Set to 1 when DSPS and DSP
539 * registers are empty in pipeline
540 * mode, always set otherwise.
541 */
542 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
543 * SCSI portion of SIOP see
544 * SSTAT0
545 */
546 #define ISTAT_DIP 0x01 /* DMA interrupt pending
547 * see DSTAT
548 */
549
550 #define CTEST8_REG (0x22^bE) /* Chip test 8 rw */
551 #define CTEST8_10_V3 0x80 /* Chip revision */
552 #define CTEST8_10_V2 0x40
553 #define CTEST8_10_V1 0x20
554 #define CTEST8_10_V0 0x10
555 #define CTEST8_10_V_MASK 0xf0
556 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
557 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
558 #define CTEST8_10_FM 0x02 /* Fetch pin mode */
559 #define CTEST8_10_SM 0x01 /* Snoop pin mode */
560
561
562 #define LCRC_REG_10 (0x23^bE)
563
564 /*
565 * 0x24 through 0x27 are the DMA byte counter register. Instructions
566 * write their high 8 bits into the DCMD register, the low 24 bits into
567 * the DBC register.
568 *
569 * Function is dependent on the command type being executed.
570 */
571
572
573 #define DBC_REG 0x24
574 /*
575 * For Block Move Instructions, DBC is a 24 bit quantity representing
576 * the number of bytes to transfer.
577 * For Transfer Control Instructions, DBC is bit fielded as follows :
578 */
579 /* Bits 20 - 23 should be clear */
580 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
581 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
582 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
583 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
584 /* Bits 8 - 15 are reserved on some implementations ? */
585 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
586 #define DBC_TCI_MASK_SHIFT 8
587 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
588 #define DBC_TCI_DATA_SHIFT 0
589
590 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
591 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
592 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
593 #define DBC_RWRI_ADDRESS_SHIFT 16
594
595
596 /*
597 * DMA command r/w
598 */
599 #define DCMD_REG (0x27^bE)
600 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
601 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
602 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
603 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
604 #define DCMD_BMI_MSG 0x04 /* instruction */
605
606 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
607 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
608 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
609
610 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
611
612 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
613 instruction */
614 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
615 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
616 #define DCMD_TCI_MSG 0x04 /* instruction */
617 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
618 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
619 #define DCMD_TCI_OP_CALL 0x08 /* CALL */
620 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
621 #define DCMD_TCI_OP_INT 0x18 /* INT */
622
623 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
624 instruction */
625 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
626 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
627 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
628 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
629
630 #define DCMD_RWRI_OP_MASK 0x07
631 #define DCMD_RWRI_OP_MOVE 0x00
632 #define DCMD_RWRI_OP_SHL 0x01
633 #define DCMD_RWRI_OP_OR 0x02
634 #define DCMD_RWRI_OP_XOR 0x03
635 #define DCMD_RWRI_OP_AND 0x04
636 #define DCMD_RWRI_OP_SHR 0x05
637 #define DCMD_RWRI_OP_ADD 0x06
638 #define DCMD_RWRI_OP_ADDC 0x07
639
640 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
641 (three words) */
642
643
644 #define DNAD_REG 0x28 /* through 0x2b DMA next address for
645 data */
646 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
647 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
648 save rw */
649 #define DMODE_BL1 0x80 /* Burst length bits */
650 #define DMODE_BL0 0x40
651 #define DMODE_BL_MASK 0xc0
652 /* Burst lengths (800) */
653 #define DMODE_BL_2 0x00 /* 2 transfer */
654 #define DMODE_BL_4 0x40 /* 4 transfers */
655 #define DMODE_BL_8 0x80 /* 8 transfers */
656 #define DMODE_BL_16 0xc0 /* 16 transfers */
657
658 #define DMODE_10_BL_1 0x00 /* 1 transfer */
659 #define DMODE_10_BL_2 0x40 /* 2 transfers */
660 #define DMODE_10_BL_4 0x80 /* 4 transfers */
661 #define DMODE_10_BL_8 0xc0 /* 8 transfers */
662 #define DMODE_10_FC2 0x20 /* Driven to FC2 pin */
663 #define DMODE_10_FC1 0x10 /* Driven to FC1 pin */
664 #define DMODE_710_PD 0x08 /* Program/data on FC0 pin */
665 #define DMODE_710_UO 0x02 /* User prog. output */
666
667 #define DMODE_MAN 0x01 /* Manual start mode,
668 * requires a 1 to be written
669 * to the start DMA bit in the DCNTL
670 * register to run scripts
671 */
672
673 /* NCR53c800 series only */
674 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
675 /* NCR53c710 only */
676 #define SCRATCHB_REG_10 0x34 /* through 0x37 scratch rw */
677
678 #define DMODE_REG (0x38^bE) /* DMA mode rw, NCR53c710 and newer */
679 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
680 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
681 #define DMODE_800_ERL 0x08 /* Enable Read Line */
682
683 #define DIEN_REG (0x39^bE) /* DMA interrupt enable rw */
684 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
685 #define DIEN_800_MDPE 0x40 /* Master data parity error */
686 #define DIEN_800_BF 0x20 /* BUS fault */
687 #define DIEN_700_BF 0x20 /* BUS fault */
688 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
689 #define DIEN_SSI 0x08 /* Enable single step interrupt */
690 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
691 * interrupt
692 */
693 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
694 #define DIEN_700_OPC 0x01 /* Enable illegal instruction
695 * interrupt
696 */
697 #define DIEN_800_IID 0x01 /* Same meaning, different name */
698
699 /*
700 * DMA watchdog timer rw
701 * set in 16 CLK input periods.
702 */
703 #define DWT_REG (0x3a^bE)
704
705 /* DMA control rw */
706 #define DCNTL_REG (0x3b^bE)
707 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
708 #define DCNTL_700_CF0 0x40
709 #define DCNTL_700_CF_MASK 0xc0
710 /* Clock divisors Divisor SCLK range (MHZ) */
711 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
712 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
713 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
714 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
715
716 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
717 #define DCNTL_SSM 0x10 /* Single step mode */
718 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
719 * after selection */
720 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
721 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
722 /* 0x02 is reserved */
723 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
724 #define DCNTL_10_EA 0x20 /* Enable Ack - needed for MVME16x */
725
726 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
727 /* NCR53c710 only */
728 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
729
730 #define SIEN1_REG_800 (0x41^bE)
731 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
732 #define SIEN1_800_GEN 0x02 /* general purpose timer */
733 #define SIEN1_800_HTH 0x01 /* handshake to handshake */
734
735 #define SIST1_REG_800 (0x43^bE)
736 #define SIST1_800_STO 0x04 /* selection/reselection timeout */
737 #define SIST1_800_GEN 0x02 /* general purpose timer */
738 #define SIST1_800_HTH 0x01 /* handshake to handshake */
739
740 #define SLPAR_REG_800 (0x44^bE) /* Parity */
741
742 #define MACNTL_REG_800 (0x46^bE) /* Memory access control */
743 #define MACNTL_800_TYP3 0x80
744 #define MACNTL_800_TYP2 0x40
745 #define MACNTL_800_TYP1 0x20
746 #define MACNTL_800_TYP0 0x10
747 #define MACNTL_800_DWR 0x08
748 #define MACNTL_800_DRD 0x04
749 #define MACNTL_800_PSCPT 0x02
750 #define MACNTL_800_SCPTS 0x01
751
752 #define GPCNTL_REG_800 (0x47^bE) /* General Purpose Pin Control */
753
754 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
755 #define STIME0_REG_800 (0x48^bE) /* SCSI Timer Register 0 */
756 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
757 #define STIME0_800_HTH_SHIFT 4
758 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
759 #define STIME0_800_SEL_SHIFT 0
760
761 #define STIME1_REG_800 (0x49^bE)
762 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
763
764 #define RESPID_REG_800 (0x4a^bE) /* Response ID, bit fielded. 8
765 bits on narrow chips, 16 on WIDE */
766
767 #define STEST0_REG_800 (0x4c^bE)
768 #define STEST0_800_SLT 0x08 /* Selection response logic test */
769 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
770 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
771 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
772
773 #define STEST1_REG_800 (0x4d^bE)
774 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
775
776 #define STEST2_REG_800 (0x4e^bE)
777 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
778 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
779 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
780 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
781 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
782 #define STEST2_800_LOW 0x01 /* SCSI low level mode */
783
784 #define STEST3_REG_800 (0x4f^bE)
785 #define STEST3_800_TE 0x80 /* Enable active negation */
786 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
787 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
788 #define STEST3_800_DSI 0x10 /* Disable single initiator response */
789 #define STEST3_800_TTM 0x04 /* Time test mode */
790 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
791 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
792
793 #define ISTAT_REG ISTAT_REG_700
794 #define SCRATCH_REG SCRATCHB_REG_10
795
796 #ifdef MEM_MAPPED
797 #define NCR_read8(address) \
798 (unsigned int)readb((u32)(host->base) + ((u32)(address)))
799
800 #define NCR_read32(address) \
801 (unsigned int) readl((u32)(host->base) + (u32)(address))
802
803 #define NCR_write8(address,value) \
804 { DEB(DEB_REGS, printk("NCR: %02x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \
805 *(volatile unsigned char *) \
806 ((u32)(host->base) + (u32)(address)) = (value); }
807
808 #define NCR_write32(address,value) \
809 { DEB(DEB_REGS, printk("NCR: %08x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \
810 *(volatile unsigned long *) \
811 ((u32)(host->base) + (u32)(address)) = (value); }
812 #else
813 #define NCR_read8(address) \
814 inb((u32)(host->base) + (address))
815
816 #define NCR_read32(address) \
817 inl((u32)(host->base) + (address))
818
819 #define NCR_write8(address,value) \
820 { DEB(DEB_REGS, printk("NCR: %02x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \
821 outb((value), (u32)(host->base) + (u32)(address)); }
822
823 #define NCR_write32(address,value) \
824 { DEB(DEB_REGS, printk("NCR: %08x => %08x\n", (u32)(value), ((u32)(host->base) + (u32)(address)))); \
825 outl((value), (u32)(host->base) + (u32)(address)); }
826 #endif
827
828 /* Patch arbitrary 32 bit words in the script */
829 #define patch_abs_32(script, offset, symbol, value) \
830 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
831 (u32)); ++i) { \
832 (script)[A_##symbol##_used[i] - (offset)] += (value); \
833 DEB(DEB_FIXUP, printk("scsi%d: %s reference %d at 0x%x in %s is now 0x%x\n",\
834 host->host_no, #symbol, i, A_##symbol##_used[i] - \
835 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
836 (offset)])); \
837 }
838
839 #endif
840 #endif
841
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