1 /******************************************************************************
2 ** High Performance device driver for the Symbios 53C896 controller.
3 **
4 ** Copyright (C) 1998-2000 Gerard Roudier <groudier@club-internet.fr>
5 **
6 ** This driver also supports all the Symbios 53C8XX controller family,
7 ** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8 ** revisions of 53C815 controllers.
9 **
10 ** This driver is based on the Linux port of the FreeBSD ncr driver.
11 **
12 ** Copyright (C) 1994 Wolfgang Stanglmeier
13 **
14 **-----------------------------------------------------------------------------
15 **
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
20 **
21 ** This program is distributed in the hope that it will be useful,
22 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ** GNU General Public License for more details.
25 **
26 ** You should have received a copy of the GNU General Public License
27 ** along with this program; if not, write to the Free Software
28 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 **
30 **-----------------------------------------------------------------------------
31 **
32 ** The Linux port of the FreeBSD ncr driver has been achieved in
33 ** november 1995 by:
34 **
35 ** Gerard Roudier <groudier@club-internet.fr>
36 **
37 ** Being given that this driver originates from the FreeBSD version, and
38 ** in order to keep synergy on both, any suggested enhancements and corrections
39 ** received on Linux are automatically a potential candidate for the FreeBSD
40 ** version.
41 **
42 ** The original driver has been written for 386bsd and FreeBSD by
43 ** Wolfgang Stanglmeier <wolf@cologne.de>
44 ** Stefan Esser <se@mi.Uni-Koeln.de>
45 **
46 **-----------------------------------------------------------------------------
47 **
48 ** Major contributions:
49 ** --------------------
50 **
51 ** NVRAM detection and reading.
52 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53 **
54 *******************************************************************************
55 */
56
57 #ifndef SYM53C8XX_DEFS_H
58 #define SYM53C8XX_DEFS_H
59
60 /*
61 ** Check supported Linux versions
62 */
63
64 #if !defined(LINUX_VERSION_CODE)
65 #include <linux/version.h>
66 #endif
67 #include <linux/config.h>
68
69 #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
70
71 /*
72 * NCR PQS/PDS special device support.
73 */
74 #ifdef CONFIG_SCSI_NCR53C8XX_PQS_PDS
75 #define SCSI_NCR_PQS_PDS_SUPPORT
76 #endif
77
78 /*
79 * No more an option, enabled by default.
80 */
81 #ifndef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
82 #define CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
83 #endif
84
85 /*
86 ** These options are not tunable from 'make config'
87 */
88 #define SCSI_NCR_PROC_INFO_SUPPORT
89
90 /*
91 ** If you want a driver as small as possible, donnot define the
92 ** following options.
93 */
94 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
95 #define SCSI_NCR_DEBUG_INFO_SUPPORT
96 #define SCSI_NCR_PCI_FIX_UP_SUPPORT
97 #ifdef SCSI_NCR_PROC_INFO_SUPPORT
98 # ifdef CONFIG_SCSI_NCR53C8XX_PROFILE
99 # define SCSI_NCR_PROFILE_SUPPORT
100 # endif
101 # define SCSI_NCR_USER_COMMAND_SUPPORT
102 # define SCSI_NCR_USER_INFO_SUPPORT
103 #endif
104
105 /*
106 ** To disable integrity checking, do not define the
107 ** following option.
108 */
109 #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
110 # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
111 #endif
112
113 /*==========================================================
114 **
115 ** nvram settings - #define SCSI_NCR_NVRAM_SUPPORT to enable
116 **
117 **==========================================================
118 */
119
120 #ifdef CONFIG_SCSI_NCR53C8XX_NVRAM_DETECT
121 #define SCSI_NCR_NVRAM_SUPPORT
122 /* #define SCSI_NCR_DEBUG_NVRAM */
123 #endif
124
125 /* ---------------------------------------------------------------------
126 ** Take into account kernel configured parameters.
127 ** Most of these options can be overridden at startup by a command line.
128 ** ---------------------------------------------------------------------
129 */
130
131 /*
132 * For Ultra2 and Ultra3 SCSI support option, use special features.
133 *
134 * Value (default) means:
135 * bit 0 : all features enabled, except:
136 * bit 1 : PCI Write And Invalidate.
137 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
138 *
139 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
140 * enabled by the driver.
141 */
142 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
143
144 /*
145 * For Ultra2 and Ultra3 SCSI support allow 80Mhz synchronous data transfers.
146 * Value means:
147 * 0 - Ultra speeds disabled
148 * 1 - Ultra enabled (Maximum 20Mtrans/sec)
149 * 2 - Ultra2 enabled (Maximum 40Mtrans/sec)
150 * 3 - Ultra3 enabled (Maximum 80Mtrans/sec)
151 *
152 * Use boot options sym53c8xx=ultra:3 to enable Ultra3 support.
153 */
154
155 #define SCSI_NCR_SETUP_ULTRA_SCSI (3)
156 #define SCSI_NCR_MAX_SYNC (80)
157
158 /*
159 * Allow tags from 2 to 256, default 8
160 */
161 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
162 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
163 #define SCSI_NCR_MAX_TAGS (2)
164 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
165 #define SCSI_NCR_MAX_TAGS (256)
166 #else
167 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
168 #endif
169 #else
170 #define SCSI_NCR_MAX_TAGS (8)
171 #endif
172
173 /*
174 * Allow tagged command queuing support if configured with default number
175 * of tags set to max (see above).
176 */
177 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
178 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
179 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
180 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
181 #else
182 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
183 #endif
184
185 /*
186 * Use normal IO if configured. Forced for alpha and ppc.
187 */
188 #if defined(CONFIG_SCSI_NCR53C8XX_IOMAPPED)
189 #define SCSI_NCR_IOMAPPED
190 #elif defined(__alpha__) || defined(__powerpc__)
191 #define SCSI_NCR_IOMAPPED
192 #elif defined(__sparc__)
193 #undef SCSI_NCR_IOMAPPED
194 #endif
195
196 /*
197 * Immediate arbitration
198 */
199 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
200 #define SCSI_NCR_IARB_SUPPORT
201 #endif
202
203 /*
204 * Should we enable DAC cycles on sparc64 platforms?
205 * Until further investigation we do not enable it
206 * anywhere at the moment.
207 */
208 #undef SCSI_NCR_USE_64BIT_DAC
209
210 /*
211 * Sync transfer frequency at startup.
212 * Allow from 5Mhz to 80Mhz default 20 Mhz.
213 */
214 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
215 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
216 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
217 #undef CONFIG_SCSI_NCR53C8XX_SYNC
218 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
219 #endif
220
221 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
222 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
223 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
224 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
225 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
226 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
227 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
228 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
229 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
230 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
231 #else
232 #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
233 #endif
234
235 /*
236 * Disallow disconnections at boot-up
237 */
238 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
239 #define SCSI_NCR_SETUP_DISCONNECTION (0)
240 #else
241 #define SCSI_NCR_SETUP_DISCONNECTION (1)
242 #endif
243
244 /*
245 * Force synchronous negotiation for all targets
246 */
247 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
248 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
249 #else
250 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
251 #endif
252
253 /*
254 * Disable master parity checking (flawed hardwares need that)
255 */
256 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
257 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
258 #else
259 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
260 #endif
261
262 /*
263 * Disable scsi parity checking (flawed devices may need that)
264 */
265 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
266 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
267 #else
268 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
269 #endif
270
271 /*
272 * Vendor specific stuff
273 */
274 #ifdef CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT
275 #define SCSI_NCR_SETUP_LED_PIN (1)
276 #define SCSI_NCR_SETUP_DIFF_SUPPORT (4)
277 #else
278 #define SCSI_NCR_SETUP_LED_PIN (0)
279 #define SCSI_NCR_SETUP_DIFF_SUPPORT (0)
280 #endif
281
282 /*
283 * Settle time after reset at boot-up
284 */
285 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
286
287 /*
288 ** Bridge quirks work-around option defaulted to 1.
289 */
290 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
291 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
292 #endif
293
294 /*
295 ** Work-around common bridge misbehaviour.
296 **
297 ** - Do not flush posted writes in the opposite
298 ** direction on read.
299 ** - May reorder DMA writes to memory.
300 **
301 ** This option should not affect performances
302 ** significantly, so it is the default.
303 */
304 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
305 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
306 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
307 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
308
309 /*
310 ** Same as option 1, but also deal with
311 ** misconfigured interrupts.
312 **
313 ** - Edge triggerred instead of level sensitive.
314 ** - No interrupt line connected.
315 ** - IRQ number misconfigured.
316 **
317 ** If no interrupt is delivered, the driver will
318 ** catch the interrupt conditions 10 times per
319 ** second. No need to say that this option is
320 ** not recommended.
321 */
322 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
323 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
324 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
325 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
326 #define SCSI_NCR_PCIQ_BROKEN_INTR
327
328 /*
329 ** Some bridge designers decided to flush
330 ** everything prior to deliver the interrupt.
331 ** This option tries to deal with such a
332 ** behaviour.
333 */
334 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
335 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
336 #endif
337
338 /*
339 ** Other parameters not configurable with "make config"
340 ** Avoid to change these constants, unless you know what you are doing.
341 */
342
343 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
344 #define SCSI_NCR_MAX_SCATTER (127)
345 #define SCSI_NCR_MAX_TARGET (16)
346
347 /*
348 ** Compute some desirable value for CAN_QUEUE
349 ** and CMD_PER_LUN.
350 ** The driver will use lower values if these
351 ** ones appear to be too large.
352 */
353 #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
354 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
355
356 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
357 #define SCSI_NCR_TIMER_INTERVAL (HZ)
358
359 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
360 #define SCSI_NCR_MAX_LUN (16)
361 #else
362 #define SCSI_NCR_MAX_LUN (1)
363 #endif
364
365 #ifndef HOSTS_C
366
367 /*
368 ** These simple macros limit expression involving
369 ** kernel time values (jiffies) to some that have
370 ** chance not to be too much incorrect. :-)
371 */
372 #define ktime_get(o) (jiffies + (u_long) o)
373 #define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0)
374 #define ktime_dif(a, b) ((long)(a) - (long)(b))
375 /* These ones are not used in this driver */
376 #define ktime_add(a, o) ((a) + (u_long)(o))
377 #define ktime_sub(a, o) ((a) - (u_long)(o))
378
379 /*
380 ** IO functions definition for big/little endian support.
381 ** For now, the NCR is only supported in little endian addressing mode,
382 ** and big endian byte ordering is only supported for the PPC.
383 ** MMIO is not used on PPC.
384 */
385
386 #ifdef __BIG_ENDIAN
387
388 #if LINUX_VERSION_CODE < LinuxVersionCode(2,1,0)
389 #error "BIG ENDIAN byte ordering needs kernel version >= 2.1.0"
390 #endif
391
392 #if defined(__powerpc__)
393 #define inw_l2b inw
394 #define inl_l2b inl
395 #define outw_b2l outw
396 #define outl_b2l outl
397 #elif defined(__sparc__)
398 #define readw_l2b readw
399 #define readl_l2b readl
400 #define writew_b2l writew
401 #define writel_b2l writel
402 #else
403 #error "Support for BIG ENDIAN is only available for PowerPC and SPARC"
404 #endif
405
406 #else /* little endian */
407
408 #if defined(__i386__) /* i386 implements full FLAT memory/MMIO model */
409 #define inw_raw inw
410 #define inl_raw inl
411 #define outw_raw outw
412 #define outl_raw outl
413 #define readb_raw(a) (*(volatile unsigned char *) (a))
414 #define readw_raw(a) (*(volatile unsigned short *) (a))
415 #define readl_raw(a) (*(volatile unsigned int *) (a))
416 #define writeb_raw(b,a) ((*(volatile unsigned char *) (a)) = (b))
417 #define writew_raw(b,a) ((*(volatile unsigned short *) (a)) = (b))
418 #define writel_raw(b,a) ((*(volatile unsigned int *) (a)) = (b))
419
420 #else /* Other little-endian (for now alpha) */
421 #define inw_raw inw
422 #define inl_raw inl
423 #define outw_raw outw
424 #define outl_raw outl
425 #define readw_raw readw
426 #define readl_raw readl
427 #define writew_raw writew
428 #define writel_raw writel
429
430 #endif
431 #endif
432
433 #ifdef SCSI_NCR_BIG_ENDIAN
434 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
435 #endif
436
437 /*
438 ** NCR53C8XX Device Ids
439 */
440
441 #ifndef PCI_DEVICE_ID_NCR_53C810
442 #define PCI_DEVICE_ID_NCR_53C810 1
443 #endif
444
445 #ifndef PCI_DEVICE_ID_NCR_53C810AP
446 #define PCI_DEVICE_ID_NCR_53C810AP 5
447 #endif
448
449 #ifndef PCI_DEVICE_ID_NCR_53C815
450 #define PCI_DEVICE_ID_NCR_53C815 4
451 #endif
452
453 #ifndef PCI_DEVICE_ID_NCR_53C820
454 #define PCI_DEVICE_ID_NCR_53C820 2
455 #endif
456
457 #ifndef PCI_DEVICE_ID_NCR_53C825
458 #define PCI_DEVICE_ID_NCR_53C825 3
459 #endif
460
461 #ifndef PCI_DEVICE_ID_NCR_53C860
462 #define PCI_DEVICE_ID_NCR_53C860 6
463 #endif
464
465 #ifndef PCI_DEVICE_ID_NCR_53C875
466 #define PCI_DEVICE_ID_NCR_53C875 0xf
467 #endif
468
469 #ifndef PCI_DEVICE_ID_NCR_53C875J
470 #define PCI_DEVICE_ID_NCR_53C875J 0x8f
471 #endif
472
473 #ifndef PCI_DEVICE_ID_NCR_53C885
474 #define PCI_DEVICE_ID_NCR_53C885 0xd
475 #endif
476
477 #ifndef PCI_DEVICE_ID_NCR_53C895
478 #define PCI_DEVICE_ID_NCR_53C895 0xc
479 #endif
480
481 #ifndef PCI_DEVICE_ID_NCR_53C896
482 #define PCI_DEVICE_ID_NCR_53C896 0xb
483 #endif
484
485 #ifndef PCI_DEVICE_ID_NCR_53C895A
486 #define PCI_DEVICE_ID_NCR_53C895A 0x12
487 #endif
488
489 #ifndef PCI_DEVICE_ID_NCR_53C1510D
490 #define PCI_DEVICE_ID_NCR_53C1510D 0xa
491 #endif
492
493 #ifndef PCI_DEVICE_ID_LSI_53C1010
494 #define PCI_DEVICE_ID_LSI_53C1010 0x20
495 #endif
496
497 #ifndef PCI_DEVICE_ID_LSI_53C1010_66
498 #define PCI_DEVICE_ID_LSI_53C1010_66 0x21
499 #endif
500
501
502 /*
503 ** NCR53C8XX devices features table.
504 */
505 typedef struct {
506 unsigned short device_id;
507 unsigned short revision_id;
508 char *name;
509 unsigned char burst_max; /* log-base-2 of max burst */
510 unsigned char offset_max;
511 unsigned char nr_divisor;
512 unsigned int features;
513 #define FE_LED0 (1<<0)
514 #define FE_WIDE (1<<1) /* Wide data transfers */
515 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
516 #define FE_ULTRA2 (1<<3) /* Ultra 2 - 40 Mtrans/sec */
517 #define FE_DBLR (1<<4) /* Clock doubler present */
518 #define FE_QUAD (1<<5) /* Clock quadrupler present */
519 #define FE_ERL (1<<6) /* Enable read line */
520 #define FE_CLSE (1<<7) /* Cache line size enable */
521 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
522 #define FE_ERMP (1<<9) /* Enable read multiple */
523 #define FE_BOF (1<<10) /* Burst opcode fetch */
524 #define FE_DFS (1<<11) /* DMA fifo size */
525 #define FE_PFEN (1<<12) /* Prefetch enable */
526 #define FE_LDSTR (1<<13) /* Load/Store supported */
527 #define FE_RAM (1<<14) /* On chip RAM present */
528 #define FE_CLK80 (1<<15) /* Board clock is 80 MHz */
529 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
530 #define FE_64BIT (1<<17) /* Supports 64-bit addressing */
531 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
532 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
533 #define FE_LEDC (1<<20) /* Hardware control of LED */
534 #define FE_DIFF (1<<21) /* Support Differential SCSI */
535 #define FE_ULTRA3 (1<<22) /* Ultra-3 80Mtrans/sec */
536 #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
537
538 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
539 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
540 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
541 } ncr_chip;
542
543 /*
544 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 3.
545 ** Memory Read transaction terminated by a retry followed by
546 ** Memory Read Line command.
547 */
548 #define FE_CACHE0_SET (FE_CACHE_SET & ~FE_ERL)
549
550 /*
551 ** DEL 397 - 53C875 Rev 3 - Part Number 609-0392410 - ITEM 5.
552 ** On paper, this errata is harmless. But it is a good reason for
553 ** using a shorter programmed burst length (64 DWORDS instead of 128).
554 */
555
556 #define SCSI_NCR_CHIP_TABLE \
557 { \
558 {PCI_DEVICE_ID_NCR_53C810, 0x0f, "810", 4, 8, 4, \
559 FE_ERL} \
560 , \
561 {PCI_DEVICE_ID_NCR_53C810, 0xff, "810a", 4, 8, 4, \
562 FE_CACHE_SET|FE_LDSTR|FE_PFEN|FE_BOF} \
563 , \
564 {PCI_DEVICE_ID_NCR_53C815, 0xff, "815", 4, 8, 4, \
565 FE_ERL|FE_BOF} \
566 , \
567 {PCI_DEVICE_ID_NCR_53C820, 0xff, "820", 4, 8, 4, \
568 FE_WIDE|FE_ERL} \
569 , \
570 {PCI_DEVICE_ID_NCR_53C825, 0x0f, "825", 4, 8, 4, \
571 FE_WIDE|FE_ERL|FE_BOF|FE_DIFF} \
572 , \
573 {PCI_DEVICE_ID_NCR_53C825, 0xff, "825a", 6, 8, 4, \
574 FE_WIDE|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM|FE_DIFF} \
575 , \
576 {PCI_DEVICE_ID_NCR_53C860, 0xff, "860", 4, 8, 5, \
577 FE_ULTRA|FE_CLK80|FE_CACHE_SET|FE_BOF|FE_LDSTR|FE_PFEN} \
578 , \
579 {PCI_DEVICE_ID_NCR_53C875, 0x01, "875", 6, 16, 5, \
580 FE_WIDE|FE_ULTRA|FE_CLK80|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|\
581 FE_RAM|FE_DIFF} \
582 , \
583 {PCI_DEVICE_ID_NCR_53C875, 0x0f, "875", 6, 16, 5, \
584 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
585 FE_RAM|FE_DIFF} \
586 , \
587 {PCI_DEVICE_ID_NCR_53C875, 0x1f, "876", 6, 16, 5, \
588 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
589 FE_RAM|FE_DIFF} \
590 , \
591 {PCI_DEVICE_ID_NCR_53C875, 0x2f, "875E", 6, 16, 5, \
592 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
593 FE_RAM|FE_DIFF} \
594 , \
595 {PCI_DEVICE_ID_NCR_53C875, 0xff, "876", 6, 16, 5, \
596 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
597 FE_RAM|FE_DIFF} \
598 , \
599 {PCI_DEVICE_ID_NCR_53C875J,0xff, "875J", 6, 16, 5, \
600 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
601 FE_RAM} \
602 , \
603 {PCI_DEVICE_ID_NCR_53C885, 0xff, "885", 6, 16, 5, \
604 FE_WIDE|FE_ULTRA|FE_DBLR|FE_CACHE0_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
605 FE_RAM|FE_DIFF} \
606 , \
607 {PCI_DEVICE_ID_NCR_53C895, 0xff, "895", 6, 31, 7, \
608 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
609 FE_RAM} \
610 , \
611 {PCI_DEVICE_ID_NCR_53C896, 0xff, "896", 6, 31, 7, \
612 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
613 FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC} \
614 , \
615 {PCI_DEVICE_ID_NCR_53C895A, 0xff, "895a", 6, 31, 7, \
616 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
617 FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC} \
618 , \
619 {PCI_DEVICE_ID_NCR_53C1510D, 0xff, "1510D", 7, 31, 7, \
620 FE_WIDE|FE_ULTRA2|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
621 FE_RAM|FE_IO256} \
622 , \
623 {PCI_DEVICE_ID_LSI_53C1010, 0xff, "1010", 6, 62, 7, \
624 FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
625 FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3} \
626 , \
627 {PCI_DEVICE_ID_LSI_53C1010_66, 0xff, "1010_66", 6, 62, 7, \
628 FE_WIDE|FE_QUAD|FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN| \
629 FE_RAM|FE_RAM8K|FE_64BIT|FE_IO256|FE_NOPM|FE_LEDC|FE_ULTRA3|FE_66MHZ} \
630 }
631
632 /*
633 * List of supported NCR chip ids
634 */
635 #define SCSI_NCR_CHIP_IDS \
636 { \
637 PCI_DEVICE_ID_NCR_53C810, \
638 PCI_DEVICE_ID_NCR_53C815, \
639 PCI_DEVICE_ID_NCR_53C820, \
640 PCI_DEVICE_ID_NCR_53C825, \
641 PCI_DEVICE_ID_NCR_53C860, \
642 PCI_DEVICE_ID_NCR_53C875, \
643 PCI_DEVICE_ID_NCR_53C875J, \
644 PCI_DEVICE_ID_NCR_53C885, \
645 PCI_DEVICE_ID_NCR_53C895, \
646 PCI_DEVICE_ID_NCR_53C896, \
647 PCI_DEVICE_ID_NCR_53C895A, \
648 PCI_DEVICE_ID_NCR_53C1510D, \
649 PCI_DEVICE_ID_LSI_53C1010, \
650 PCI_DEVICE_ID_LSI_53C1010_66 \
651 }
652
653 /*
654 ** Driver setup structure.
655 **
656 ** This structure is initialized from linux config options.
657 ** It can be overridden at boot-up by the boot command line.
658 */
659 #define SCSI_NCR_MAX_EXCLUDES 8
660 struct ncr_driver_setup {
661 u_char master_parity;
662 u_char scsi_parity;
663 u_char disconnection;
664 u_char special_features;
665 u_char ultra_scsi;
666 u_char force_sync_nego;
667 u_char reverse_probe;
668 u_char pci_fix_up;
669 u_char use_nvram;
670 u_char verbose;
671 u_char default_tags;
672 u_short default_sync;
673 u_short debug;
674 u_char burst_max;
675 u_char led_pin;
676 u_char max_wide;
677 u_char settle_delay;
678 u_char diff_support;
679 u_char irqm;
680 u_char bus_check;
681 u_char optimize;
682 u_char recovery;
683 u_char host_id;
684 u_short iarb;
685 u_long excludes[SCSI_NCR_MAX_EXCLUDES];
686 char tag_ctrl[100];
687 };
688
689 /*
690 ** Initial setup.
691 ** Can be overriden at startup by a command line.
692 */
693 #define SCSI_NCR_DRIVER_SETUP \
694 { \
695 SCSI_NCR_SETUP_MASTER_PARITY, \
696 SCSI_NCR_SETUP_SCSI_PARITY, \
697 SCSI_NCR_SETUP_DISCONNECTION, \
698 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
699 SCSI_NCR_SETUP_ULTRA_SCSI, \
700 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
701 0, \
702 0, \
703 1, \
704 1, \
705 SCSI_NCR_SETUP_DEFAULT_TAGS, \
706 SCSI_NCR_SETUP_DEFAULT_SYNC, \
707 0x0200, \
708 7, \
709 SCSI_NCR_SETUP_LED_PIN, \
710 1, \
711 SCSI_NCR_SETUP_SETTLE_TIME, \
712 SCSI_NCR_SETUP_DIFF_SUPPORT, \
713 0, \
714 1, \
715 0, \
716 0, \
717 255, \
718 0x00 \
719 }
720
721 /*
722 ** Boot fail safe setup.
723 ** Override initial setup from boot command line:
724 ** ncr53c8xx=safe:y
725 */
726 #define SCSI_NCR_DRIVER_SAFE_SETUP \
727 { \
728 0, \
729 1, \
730 0, \
731 0, \
732 0, \
733 0, \
734 0, \
735 0, \
736 1, \
737 2, \
738 0, \
739 255, \
740 0x00, \
741 255, \
742 0, \
743 0, \
744 10, \
745 1, \
746 1, \
747 1, \
748 0, \
749 0, \
750 255 \
751 }
752
753 #ifdef SCSI_NCR_NVRAM_SUPPORT
754 /*
755 ** Symbios NvRAM data format
756 */
757 #define SYMBIOS_NVRAM_SIZE 368
758 #define SYMBIOS_NVRAM_ADDRESS 0x100
759
760 struct Symbios_nvram {
761 /* Header 6 bytes */
762 u_short type; /* 0x0000 */
763 u_short byte_count; /* excluding header/trailer */
764 u_short checksum;
765
766 /* Controller set up 20 bytes */
767 u_char v_major; /* 0x00 */
768 u_char v_minor; /* 0x30 */
769 u_int32 boot_crc;
770 u_short flags;
771 #define SYMBIOS_SCAM_ENABLE (1)
772 #define SYMBIOS_PARITY_ENABLE (1<<1)
773 #define SYMBIOS_VERBOSE_MSGS (1<<2)
774 #define SYMBIOS_CHS_MAPPING (1<<3)
775 #define SYMBIOS_NO_NVRAM (1<<3) /* ??? */
776 u_short flags1;
777 #define SYMBIOS_SCAN_HI_LO (1)
778 u_short term_state;
779 #define SYMBIOS_TERM_CANT_PROGRAM (0)
780 #define SYMBIOS_TERM_ENABLED (1)
781 #define SYMBIOS_TERM_DISABLED (2)
782 u_short rmvbl_flags;
783 #define SYMBIOS_RMVBL_NO_SUPPORT (0)
784 #define SYMBIOS_RMVBL_BOOT_DEVICE (1)
785 #define SYMBIOS_RMVBL_MEDIA_INSTALLED (2)
786 u_char host_id;
787 u_char num_hba; /* 0x04 */
788 u_char num_devices; /* 0x10 */
789 u_char max_scam_devices; /* 0x04 */
790 u_char num_valid_scam_devives; /* 0x00 */
791 u_char rsvd;
792
793 /* Boot order 14 bytes * 4 */
794 struct Symbios_host{
795 u_short type; /* 4:8xx / 0:nok */
796 u_short device_id; /* PCI device id */
797 u_short vendor_id; /* PCI vendor id */
798 u_char bus_nr; /* PCI bus number */
799 u_char device_fn; /* PCI device/function number << 3*/
800 u_short word8;
801 u_short flags;
802 #define SYMBIOS_INIT_SCAN_AT_BOOT (1)
803 u_short io_port; /* PCI io_port address */
804 } host[4];
805
806 /* Targets 8 bytes * 16 */
807 struct Symbios_target {
808 u_char flags;
809 #define SYMBIOS_DISCONNECT_ENABLE (1)
810 #define SYMBIOS_SCAN_AT_BOOT_TIME (1<<1)
811 #define SYMBIOS_SCAN_LUNS (1<<2)
812 #define SYMBIOS_QUEUE_TAGS_ENABLED (1<<3)
813 u_char rsvd;
814 u_char bus_width; /* 0x08/0x10 */
815 u_char sync_offset;
816 u_short sync_period; /* 4*period factor */
817 u_short timeout;
818 } target[16];
819 /* Scam table 8 bytes * 4 */
820 struct Symbios_scam {
821 u_short id;
822 u_short method;
823 #define SYMBIOS_SCAM_DEFAULT_METHOD (0)
824 #define SYMBIOS_SCAM_DONT_ASSIGN (1)
825 #define SYMBIOS_SCAM_SET_SPECIFIC_ID (2)
826 #define SYMBIOS_SCAM_USE_ORDER_GIVEN (3)
827 u_short status;
828 #define SYMBIOS_SCAM_UNKNOWN (0)
829 #define SYMBIOS_SCAM_DEVICE_NOT_FOUND (1)
830 #define SYMBIOS_SCAM_ID_NOT_SET (2)
831 #define SYMBIOS_SCAM_ID_VALID (3)
832 u_char target_id;
833 u_char rsvd;
834 } scam[4];
835
836 u_char spare_devices[15*8];
837 u_char trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */
838 };
839 typedef struct Symbios_nvram Symbios_nvram;
840 typedef struct Symbios_host Symbios_host;
841 typedef struct Symbios_target Symbios_target;
842 typedef struct Symbios_scam Symbios_scam;
843
844 /*
845 ** Tekram NvRAM data format.
846 */
847 #define TEKRAM_NVRAM_SIZE 64
848 #define TEKRAM_93C46_NVRAM_ADDRESS 0
849 #define TEKRAM_24C16_NVRAM_ADDRESS 0x40
850
851 struct Tekram_nvram {
852 struct Tekram_target {
853 u_char flags;
854 #define TEKRAM_PARITY_CHECK (1)
855 #define TEKRAM_SYNC_NEGO (1<<1)
856 #define TEKRAM_DISCONNECT_ENABLE (1<<2)
857 #define TEKRAM_START_CMD (1<<3)
858 #define TEKRAM_TAGGED_COMMANDS (1<<4)
859 #define TEKRAM_WIDE_NEGO (1<<5)
860 u_char sync_index;
861 u_short word2;
862 } target[16];
863 u_char host_id;
864 u_char flags;
865 #define TEKRAM_MORE_THAN_2_DRIVES (1)
866 #define TEKRAM_DRIVES_SUP_1GB (1<<1)
867 #define TEKRAM_RESET_ON_POWER_ON (1<<2)
868 #define TEKRAM_ACTIVE_NEGATION (1<<3)
869 #define TEKRAM_IMMEDIATE_SEEK (1<<4)
870 #define TEKRAM_SCAN_LUNS (1<<5)
871 #define TEKRAM_REMOVABLE_FLAGS (3<<6) /* 0: disable; 1: boot device; 2:all */
872 u_char boot_delay_index;
873 u_char max_tags_index;
874 u_short flags1;
875 #define TEKRAM_F2_F6_ENABLED (1)
876 u_short spare[29];
877 };
878 typedef struct Tekram_nvram Tekram_nvram;
879 typedef struct Tekram_target Tekram_target;
880
881 #endif /* SCSI_NCR_NVRAM_SUPPORT */
882
883 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
884
885 /*-----------------------------------------------------------------
886 **
887 ** The ncr 53c810 register structure.
888 **
889 **-----------------------------------------------------------------
890 */
891
892 struct ncr_reg {
893 /*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
894
895 /*01*/ u_char nc_scntl1; /* no reset */
896 #define ISCON 0x10 /* connected to scsi */
897 #define CRST 0x08 /* force reset */
898 #define IARB 0x02 /* immediate arbitration */
899
900 /*02*/ u_char nc_scntl2; /* no disconnect expected */
901 #define SDU 0x80 /* cmd: disconnect will raise error */
902 #define CHM 0x40 /* sta: chained mode */
903 #define WSS 0x08 /* sta: wide scsi send [W]*/
904 #define WSR 0x01 /* sta: wide scsi received [W]*/
905
906 /*03*/ u_char nc_scntl3; /* cnf system clock dependent */
907 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
908 #define ULTRA 0x80 /* cmd: ULTRA enable */
909 /* bits 0-2, 7 rsvd for C1010 */
910
911 /*04*/ u_char nc_scid; /* cnf host adapter scsi address */
912 #define RRE 0x40 /* r/w:e enable response to resel. */
913 #define SRE 0x20 /* r/w:e enable response to select */
914
915 /*05*/ u_char nc_sxfer; /* ### Sync speed and count */
916 /* bits 6-7 rsvd for C1010 */
917
918 /*06*/ u_char nc_sdid; /* ### Destination-ID */
919
920 /*07*/ u_char nc_gpreg; /* ??? IO-Pins */
921
922 /*08*/ u_char nc_sfbr; /* ### First byte in phase */
923
924 /*09*/ u_char nc_socl;
925 #define CREQ 0x80 /* r/w: SCSI-REQ */
926 #define CACK 0x40 /* r/w: SCSI-ACK */
927 #define CBSY 0x20 /* r/w: SCSI-BSY */
928 #define CSEL 0x10 /* r/w: SCSI-SEL */
929 #define CATN 0x08 /* r/w: SCSI-ATN */
930 #define CMSG 0x04 /* r/w: SCSI-MSG */
931 #define CC_D 0x02 /* r/w: SCSI-C_D */
932 #define CI_O 0x01 /* r/w: SCSI-I_O */
933
934 /*0a*/ u_char nc_ssid;
935
936 /*0b*/ u_char nc_sbcl;
937
938 /*0c*/ u_char nc_dstat;
939 #define DFE 0x80 /* sta: dma fifo empty */
940 #define MDPE 0x40 /* int: master data parity error */
941 #define BF 0x20 /* int: script: bus fault */
942 #define ABRT 0x10 /* int: script: command aborted */
943 #define SSI 0x08 /* int: script: single step */
944 #define SIR 0x04 /* int: script: interrupt instruct. */
945 #define IID 0x01 /* int: script: illegal instruct. */
946
947 /*0d*/ u_char nc_sstat0;
948 #define ILF 0x80 /* sta: data in SIDL register lsb */
949 #define ORF 0x40 /* sta: data in SODR register lsb */
950 #define OLF 0x20 /* sta: data in SODL register lsb */
951 #define AIP 0x10 /* sta: arbitration in progress */
952 #define LOA 0x08 /* sta: arbitration lost */
953 #define WOA 0x04 /* sta: arbitration won */
954 #define IRST 0x02 /* sta: scsi reset signal */
955 #define SDP 0x01 /* sta: scsi parity signal */
956
957 /*0e*/ u_char nc_sstat1;
958 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
959
960 /*0f*/ u_char nc_sstat2;
961 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
962 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
963 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
964 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
965 #define LDSC 0x02 /* sta: disconnect & reconnect */
966
967 /*10*/ u_char nc_dsa; /* --> Base page */
968 /*11*/ u_char nc_dsa1;
969 /*12*/ u_char nc_dsa2;
970 /*13*/ u_char nc_dsa3;
971
972 /*14*/ u_char nc_istat; /* --> Main Command and status */
973 #define CABRT 0x80 /* cmd: abort current operation */
974 #define SRST 0x40 /* mod: reset chip */
975 #define SIGP 0x20 /* r/w: message from host to ncr */
976 #define SEM 0x10 /* r/w: message between host + ncr */
977 #define CON 0x08 /* sta: connected to scsi */
978 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
979 #define SIP 0x02 /* sta: scsi-interrupt */
980 #define DIP 0x01 /* sta: host/script interrupt */
981
982 /*15*/ u_char nc_istat1; /* 896 only */
983 /*16*/ u_char nc_mbox0; /* 896 only */
984 /*17*/ u_char nc_mbox1; /* 896 only */
985
986 /*18*/ u_char nc_ctest0;
987 /*19*/ u_char nc_ctest1;
988
989 /*1a*/ u_char nc_ctest2;
990 #define CSIGP 0x40
991 /* bits 0-2,7 rsvd for C1010 */
992
993 /*1b*/ u_char nc_ctest3;
994 #define FLF 0x08 /* cmd: flush dma fifo */
995 #define CLF 0x04 /* cmd: clear dma fifo */
996 #define FM 0x02 /* mod: fetch pin mode */
997 #define WRIE 0x01 /* mod: write and invalidate enable */
998 /* bits 4-7 rsvd for C1010 */
999
1000 /*1c*/ u_int32 nc_temp; /* ### Temporary stack */
1001
1002 /*20*/ u_char nc_dfifo;
1003 /*21*/ u_char nc_ctest4;
1004 #define BDIS 0x80 /* mod: burst disable */
1005 #define MPEE 0x08 /* mod: master parity error enable */
1006
1007 /*22*/ u_char nc_ctest5;
1008 #define DFS 0x20 /* mod: dma fifo size */
1009 /* bits 0-1, 3-7 rsvd for C1010 */
1010 /*23*/ u_char nc_ctest6;
1011
1012 /*24*/ u_int32 nc_dbc; /* ### Byte count and command */
1013 /*28*/ u_int32 nc_dnad; /* ### Next command register */
1014 /*2c*/ u_int32 nc_dsp; /* --> Script Pointer */
1015 /*30*/ u_int32 nc_dsps; /* --> Script pointer save/opcode#2 */
1016
1017 /*34*/ u_char nc_scratcha; /* Temporary register a */
1018 /*35*/ u_char nc_scratcha1;
1019 /*36*/ u_char nc_scratcha2;
1020 /*37*/ u_char nc_scratcha3;
1021
1022 /*38*/ u_char nc_dmode;
1023 #define BL_2 0x80 /* mod: burst length shift value +2 */
1024 #define BL_1 0x40 /* mod: burst length shift value +1 */
1025 #define ERL 0x08 /* mod: enable read line */
1026 #define ERMP 0x04 /* mod: enable read multiple */
1027 #define BOF 0x02 /* mod: burst op code fetch */
1028
1029 /*39*/ u_char nc_dien;
1030 /*3a*/ u_char nc_sbr;
1031
1032 /*3b*/ u_char nc_dcntl; /* --> Script execution control */
1033 #define CLSE 0x80 /* mod: cache line size enable */
1034 #define PFF 0x40 /* cmd: pre-fetch flush */
1035 #define PFEN 0x20 /* mod: pre-fetch enable */
1036 #define SSM 0x10 /* mod: single step mode */
1037 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
1038 #define STD 0x04 /* cmd: start dma mode */
1039 #define IRQD 0x02 /* mod: irq disable */
1040 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
1041 /* bits 0-1 rsvd for C1010 */
1042
1043 /*3c*/ u_int32 nc_adder;
1044
1045 /*40*/ u_short nc_sien; /* -->: interrupt enable */
1046 /*42*/ u_short nc_sist; /* <--: interrupt status */
1047 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
1048 #define STO 0x0400/* sta: timeout (select) */
1049 #define GEN 0x0200/* sta: timeout (general) */
1050 #define HTH 0x0100/* sta: timeout (handshake) */
1051 #define MA 0x80 /* sta: phase mismatch */
1052 #define CMP 0x40 /* sta: arbitration complete */
1053 #define SEL 0x20 /* sta: selected by another device */
1054 #define RSL 0x10 /* sta: reselected by another device*/
1055 #define SGE 0x08 /* sta: gross error (over/underflow)*/
1056 #define UDC 0x04 /* sta: unexpected disconnect */
1057 #define RST 0x02 /* sta: scsi bus reset detected */
1058 #define PAR 0x01 /* sta: scsi parity error */
1059
1060 /*44*/ u_char nc_slpar;
1061 /*45*/ u_char nc_swide;
1062 /*46*/ u_char nc_macntl;
1063 /*47*/ u_char nc_gpcntl;
1064 /*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
1065 /*49*/ u_char nc_stime1; /* cmd: timeout user defined */
1066 /*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
1067
1068 /*4c*/ u_char nc_stest0;
1069
1070 /*4d*/ u_char nc_stest1;
1071 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
1072 #define DBLEN 0x08 /* clock doubler running */
1073 #define DBLSEL 0x04 /* clock doubler selected */
1074
1075
1076 /*4e*/ u_char nc_stest2;
1077 #define ROF 0x40 /* reset scsi offset (after gross error!) */
1078 #define EXT 0x02 /* extended filtering */
1079
1080 /*4f*/ u_char nc_stest3;
1081 #define TE 0x80 /* c: tolerAnt enable */
1082 #define HSC 0x20 /* c: Halt SCSI Clock */
1083 #define CSF 0x02 /* c: clear scsi fifo */
1084
1085 /*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
1086 /*52*/ u_char nc_stest4;
1087 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
1088 #define SMODE_HVD 0x40 /* High Voltage Differential */
1089 #define SMODE_SE 0x80 /* Single Ended */
1090 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
1091 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
1092 /* bits 0-5 rsvd for C1010 */
1093
1094 /*53*/ u_char nc_53_;
1095 /*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
1096 /*56*/ u_char nc_ccntl0; /* Chip Control 0 (896) */
1097 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
1098 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
1099 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
1100 #define DISFC 0x10 /* Disable Auto FIFO Clear */
1101 #define DILS 0x02 /* Disable Internal Load/Store */
1102 #define DPR 0x01 /* Disable Pipe Req */
1103
1104 /*57*/ u_char nc_ccntl1; /* Chip Control 1 (896) */
1105 #define ZMOD 0x80 /* High Impedance Mode */
1106 #define DIC 0x10 /* Disable Internal Cycles */
1107 #define DDAC 0x08 /* Disable Dual Address Cycle */
1108 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
1109 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
1110 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
1111
1112 /*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
1113 /*5a*/ u_short nc_5a_;
1114
1115 /*5c*/ u_char nc_scr0; /* Working register B */
1116 /*5d*/ u_char nc_scr1; /* */
1117 /*5e*/ u_char nc_scr2; /* */
1118 /*5f*/ u_char nc_scr3; /* */
1119
1120 /*60*/ u_char nc_scrx[64]; /* Working register C-R */
1121 /*a0*/ u_int32 nc_mmrs; /* Memory Move Read Selector */
1122 /*a4*/ u_int32 nc_mmws; /* Memory Move Write Selector */
1123 /*a8*/ u_int32 nc_sfs; /* Script Fetch Selector */
1124 /*ac*/ u_int32 nc_drs; /* DSA Relative Selector */
1125 /*b0*/ u_int32 nc_sbms; /* Static Block Move Selector */
1126 /*b4*/ u_int32 nc_dbms; /* Dynamic Block Move Selector */
1127 /*b8*/ u_int32 nc_dnad64; /* DMA Next Address 64 */
1128 /*bc*/ u_short nc_scntl4; /* C1010 only */
1129 #define U3EN 0x80 /* Enable Ultra 3 */
1130 #define AIPEN 0x40 /* Allow check upper byte lanes */
1131 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
1132 transfer edge */
1133 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
1134 transfer edge */
1135
1136 /*be*/ u_char nc_aipcntl0; /* Epat Control 1 C1010 only */
1137 /*bf*/ u_char nc_aipcntl1; /* AIP Control C1010_66 Only */
1138
1139 /*c0*/ u_int32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
1140 /*c4*/ u_int32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
1141 /*c8*/ u_char nc_rbc; /* Remaining Byte Count */
1142 /*c9*/ u_char nc_rbc1; /* */
1143 /*ca*/ u_char nc_rbc2; /* */
1144 /*cb*/ u_char nc_rbc3; /* */
1145
1146 /*cc*/ u_char nc_ua; /* Updated Address */
1147 /*cd*/ u_char nc_ua1; /* */
1148 /*ce*/ u_char nc_ua2; /* */
1149 /*cf*/ u_char nc_ua3; /* */
1150 /*d0*/ u_int32 nc_esa; /* Entry Storage Address */
1151 /*d4*/ u_char nc_ia; /* Instruction Address */
1152 /*d5*/ u_char nc_ia1;
1153 /*d6*/ u_char nc_ia2;
1154 /*d7*/ u_char nc_ia3;
1155 /*d8*/ u_int32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
1156 /*dc*/ u_int32 nc_csbc; /* Cumulative SCSI Byte Count */
1157
1158 /* Following for C1010 only */
1159 /*e0*/ u_short nc_crcpad; /* CRC Value */
1160 /*e2*/ u_char nc_crccntl0; /* CRC control register */
1161 #define SNDCRC 0x10 /* Send CRC Request */
1162 /*e3*/ u_char nc_crccntl1; /* CRC control register */
1163 /*e4*/ u_int32 nc_crcdata; /* CRC data register */
1164 /*e8*/ u_int32 nc_e8_; /* rsvd */
1165 /*ec*/ u_int32 nc_ec_; /* rsvd */
1166 /*f0*/ u_short nc_dfbc; /* DMA FIFO byte count */
1167
1168 };
1169
1170 /*-----------------------------------------------------------
1171 **
1172 ** Utility macros for the script.
1173 **
1174 **-----------------------------------------------------------
1175 */
1176
1177 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
1178 #define REG(r) REGJ (nc_, r)
1179
1180 typedef u_int32 ncrcmd;
1181
1182 /*-----------------------------------------------------------
1183 **
1184 ** SCSI phases
1185 **
1186 ** DT phases illegal for ncr driver.
1187 **
1188 **-----------------------------------------------------------
1189 */
1190
1191 #define SCR_DATA_OUT 0x00000000
1192 #define SCR_DATA_IN 0x01000000
1193 #define SCR_COMMAND 0x02000000
1194 #define SCR_STATUS 0x03000000
1195 #define SCR_DT_DATA_OUT 0x04000000
1196 #define SCR_DT_DATA_IN 0x05000000
1197 #define SCR_MSG_OUT 0x06000000
1198 #define SCR_MSG_IN 0x07000000
1199
1200 #define SCR_ILG_OUT 0x04000000
1201 #define SCR_ILG_IN 0x05000000
1202
1203 /*-----------------------------------------------------------
1204 **
1205 ** Data transfer via SCSI.
1206 **
1207 **-----------------------------------------------------------
1208 **
1209 ** MOVE_ABS (LEN)
1210 ** <<start address>>
1211 **
1212 ** MOVE_IND (LEN)
1213 ** <<dnad_offset>>
1214 **
1215 ** MOVE_TBL
1216 ** <<dnad_offset>>
1217 **
1218 **-----------------------------------------------------------
1219 */
1220
1221 #define OPC_MOVE 0x08000000
1222
1223 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
1224 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
1225 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
1226
1227 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
1228 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
1229 #define SCR_CHMOV_TBL (0x10000000)
1230
1231 struct scr_tblmove {
1232 u_int32 size;
1233 u_int32 addr;
1234 };
1235
1236 /*-----------------------------------------------------------
1237 **
1238 ** Selection
1239 **
1240 **-----------------------------------------------------------
1241 **
1242 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
1243 ** <<alternate_address>>
1244 **
1245 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
1246 ** <<alternate_address>>
1247 **
1248 **-----------------------------------------------------------
1249 */
1250
1251 #define SCR_SEL_ABS 0x40000000
1252 #define SCR_SEL_ABS_ATN 0x41000000
1253 #define SCR_SEL_TBL 0x42000000
1254 #define SCR_SEL_TBL_ATN 0x43000000
1255
1256 struct scr_tblsel {
1257 u_char sel_scntl4;
1258 u_char sel_sxfer;
1259 u_char sel_id;
1260 u_char sel_scntl3;
1261 };
1262
1263 #define SCR_JMP_REL 0x04000000
1264 #define SCR_ID(id) (((u_int32)(id)) << 16)
1265
1266 /*-----------------------------------------------------------
1267 **
1268 ** Waiting for Disconnect or Reselect
1269 **
1270 **-----------------------------------------------------------
1271 **
1272 ** WAIT_DISC
1273 ** dummy: <<alternate_address>>
1274 **
1275 ** WAIT_RESEL
1276 ** <<alternate_address>>
1277 **
1278 **-----------------------------------------------------------
1279 */
1280
1281 #define SCR_WAIT_DISC 0x48000000
1282 #define SCR_WAIT_RESEL 0x50000000
1283
1284 /*-----------------------------------------------------------
1285 **
1286 ** Bit Set / Reset
1287 **
1288 **-----------------------------------------------------------
1289 **
1290 ** SET (flags {|.. })
1291 **
1292 ** CLR (flags {|.. })
1293 **
1294 **-----------------------------------------------------------
1295 */
1296
1297 #define SCR_SET(f) (0x58000000 | (f))
1298 #define SCR_CLR(f) (0x60000000 | (f))
1299
1300 #define SCR_CARRY 0x00000400
1301 #define SCR_TRG 0x00000200
1302 #define SCR_ACK 0x00000040
1303 #define SCR_ATN 0x00000008
1304
1305
1306
1307
1308 /*-----------------------------------------------------------
1309 **
1310 ** Memory to memory move
1311 **
1312 **-----------------------------------------------------------
1313 **
1314 ** COPY (bytecount)
1315 ** << source_address >>
1316 ** << destination_address >>
1317 **
1318 ** SCR_COPY sets the NO FLUSH option by default.
1319 ** SCR_COPY_F does not set this option.
1320 **
1321 ** For chips which do not support this option,
1322 ** ncr_copy_and_bind() will remove this bit.
1323 **-----------------------------------------------------------
1324 */
1325
1326 #define SCR_NO_FLUSH 0x01000000
1327
1328 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1329 #define SCR_COPY_F(n) (0xc0000000 | (n))
1330
1331 /*-----------------------------------------------------------
1332 **
1333 ** Register move and binary operations
1334 **
1335 **-----------------------------------------------------------
1336 **
1337 ** SFBR_REG (reg, op, data) reg = SFBR op data
1338 ** << 0 >>
1339 **
1340 ** REG_SFBR (reg, op, data) SFBR = reg op data
1341 ** << 0 >>
1342 **
1343 ** REG_REG (reg, op, data) reg = reg op data
1344 ** << 0 >>
1345 **
1346 **-----------------------------------------------------------
1347 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
1348 ** of SFBR register can be used as data (SCR_SFBR_DATA).
1349 ** The 896 has additionnal IO registers starting at
1350 ** offset 0x80. Bit 7 of register offset is stored in
1351 ** bit 7 of the SCRIPTS instruction first DWORD.
1352 **-----------------------------------------------------------
1353 */
1354
1355 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1356
1357 #define SCR_SFBR_REG(reg,op,data) \
1358 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1359
1360 #define SCR_REG_SFBR(reg,op,data) \
1361 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1362
1363 #define SCR_REG_REG(reg,op,data) \
1364 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1365
1366
1367 #define SCR_LOAD 0x00000000
1368 #define SCR_SHL 0x01000000
1369 #define SCR_OR 0x02000000
1370 #define SCR_XOR 0x03000000
1371 #define SCR_AND 0x04000000
1372 #define SCR_SHR 0x05000000
1373 #define SCR_ADD 0x06000000
1374 #define SCR_ADDC 0x07000000
1375
1376 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1377
1378 /*-----------------------------------------------------------
1379 **
1380 ** FROM_REG (reg) SFBR = reg
1381 ** << 0 >>
1382 **
1383 ** TO_REG (reg) reg = SFBR
1384 ** << 0 >>
1385 **
1386 ** LOAD_REG (reg, data) reg = <data>
1387 ** << 0 >>
1388 **
1389 ** LOAD_SFBR(data) SFBR = <data>
1390 ** << 0 >>
1391 **
1392 **-----------------------------------------------------------
1393 */
1394
1395 #define SCR_FROM_REG(reg) \
1396 SCR_REG_SFBR(reg,SCR_OR,0)
1397
1398 #define SCR_TO_REG(reg) \
1399 SCR_SFBR_REG(reg,SCR_OR,0)
1400
1401 #define SCR_LOAD_REG(reg,data) \
1402 SCR_REG_REG(reg,SCR_LOAD,data)
1403
1404 #define SCR_LOAD_SFBR(data) \
1405 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1406
1407 /*-----------------------------------------------------------
1408 **
1409 ** LOAD from memory to register.
1410 ** STORE from register to memory.
1411 **
1412 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1413 **
1414 **-----------------------------------------------------------
1415 **
1416 ** LOAD_ABS (LEN)
1417 ** <<start address>>
1418 **
1419 ** LOAD_REL (LEN) (DSA relative)
1420 ** <<dsa_offset>>
1421 **
1422 **-----------------------------------------------------------
1423 */
1424
1425 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1426 #define SCR_NO_FLUSH2 0x02000000
1427 #define SCR_DSA_REL2 0x10000000
1428
1429 #define SCR_LOAD_R(reg, how, n) \
1430 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1431
1432 #define SCR_STORE_R(reg, how, n) \
1433 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1434
1435 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1436 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1437 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1438 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1439
1440 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1441 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1442 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1443 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1444
1445
1446 /*-----------------------------------------------------------
1447 **
1448 ** Waiting for Disconnect or Reselect
1449 **
1450 **-----------------------------------------------------------
1451 **
1452 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1453 ** <<address>>
1454 **
1455 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1456 ** <<distance>>
1457 **
1458 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1459 ** <<address>>
1460 **
1461 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1462 ** <<distance>>
1463 **
1464 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1465 ** <<dummy>>
1466 **
1467 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1468 ** <<ident>>
1469 **
1470 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1471 ** <<ident>>
1472 **
1473 ** Conditions:
1474 ** WHEN (phase)
1475 ** IF (phase)
1476 ** CARRYSET
1477 ** DATA (data, mask)
1478 **
1479 **-----------------------------------------------------------
1480 */
1481
1482 #define SCR_NO_OP 0x80000000
1483 #define SCR_JUMP 0x80080000
1484 #define SCR_JUMP64 0x80480000
1485 #define SCR_JUMPR 0x80880000
1486 #define SCR_CALL 0x88080000
1487 #define SCR_CALLR 0x88880000
1488 #define SCR_RETURN 0x90080000
1489 #define SCR_INT 0x98080000
1490 #define SCR_INT_FLY 0x98180000
1491
1492 #define IFFALSE(arg) (0x00080000 | (arg))
1493 #define IFTRUE(arg) (0x00000000 | (arg))
1494
1495 #define WHEN(phase) (0x00030000 | (phase))
1496 #define IF(phase) (0x00020000 | (phase))
1497
1498 #define DATA(D) (0x00040000 | ((D) & 0xff))
1499 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1500
1501 #define CARRYSET (0x00200000)
1502
1503 /*-----------------------------------------------------------
1504 **
1505 ** SCSI constants.
1506 **
1507 **-----------------------------------------------------------
1508 */
1509
1510 /*
1511 ** Messages
1512 */
1513
1514 #define M_COMPLETE (0x00)
1515 #define M_EXTENDED (0x01)
1516 #define M_SAVE_DP (0x02)
1517 #define M_RESTORE_DP (0x03)
1518 #define M_DISCONNECT (0x04)
1519 #define M_ID_ERROR (0x05)
1520 #define M_ABORT (0x06)
1521 #define M_REJECT (0x07)
1522 #define M_NOOP (0x08)
1523 #define M_PARITY (0x09)
1524 #define M_LCOMPLETE (0x0a)
1525 #define M_FCOMPLETE (0x0b)
1526 #define M_RESET (0x0c)
1527 #define M_ABORT_TAG (0x0d)
1528 #define M_CLEAR_QUEUE (0x0e)
1529 #define M_INIT_REC (0x0f)
1530 #define M_REL_REC (0x10)
1531 #define M_TERMINATE (0x11)
1532 #define M_SIMPLE_TAG (0x20)
1533 #define M_HEAD_TAG (0x21)
1534 #define M_ORDERED_TAG (0x22)
1535 #define M_IGN_RESIDUE (0x23)
1536 #define M_IDENTIFY (0x80)
1537
1538 #define M_X_MODIFY_DP (0x00)
1539 #define M_X_SYNC_REQ (0x01)
1540 #define M_X_WIDE_REQ (0x03)
1541 #define M_X_PPR_REQ (0x04)
1542
1543 /*
1544 ** Status
1545 */
1546
1547 #define S_GOOD (0x00)
1548 #define S_CHECK_COND (0x02)
1549 #define S_COND_MET (0x04)
1550 #define S_BUSY (0x08)
1551 #define S_INT (0x10)
1552 #define S_INT_COND_MET (0x14)
1553 #define S_CONFLICT (0x18)
1554 #define S_TERMINATED (0x20)
1555 #define S_QUEUE_FULL (0x28)
1556 #define S_ILLEGAL (0xff)
1557 #define S_SENSE (0x80)
1558
1559 /*
1560 * End of ncrreg from FreeBSD
1561 */
1562
1563 #endif /* !defined HOSTS_C */
1564
1565 #endif /* defined SYM53C8XX_DEFS_H */
1566
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