1 #ifndef __CS461X_H
2 #define __CS461X_H
3
4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for Cirrus Logic CS461x chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 #ifndef PCI_VENDOR_ID_CIRRUS
26 #define PCI_VENDOR_ID_CIRRUS 0x1013
27 #endif
28 #ifndef PCI_DEVICE_ID_CIRRUS_4610
29 #define PCI_DEVICE_ID_CIRRUS_4610 0x6001
30 #endif
31 #ifndef PCI_DEVICE_ID_CIRRUS_4612
32 #define PCI_DEVICE_ID_CIRRUS_4612 0x6003
33 #endif
34 #ifndef PCI_DEVICE_ID_CIRRUS_4615
35 #define PCI_DEVICE_ID_CIRRUS_4615 0x6004
36 #endif
37
38 /*
39 * Direct registers
40 */
41
42 /*
43 * The following define the offsets of the registers accessed via base address
44 * register zero on the CS461x part.
45 */
46 #define BA0_HISR 0x00000000
47 #define BA0_HSR0 0x00000004
48 #define BA0_HICR 0x00000008
49 #define BA0_DMSR 0x00000100
50 #define BA0_HSAR 0x00000110
51 #define BA0_HDAR 0x00000114
52 #define BA0_HDMR 0x00000118
53 #define BA0_HDCR 0x0000011C
54 #define BA0_PFMC 0x00000200
55 #define BA0_PFCV1 0x00000204
56 #define BA0_PFCV2 0x00000208
57 #define BA0_PCICFG00 0x00000300
58 #define BA0_PCICFG04 0x00000304
59 #define BA0_PCICFG08 0x00000308
60 #define BA0_PCICFG0C 0x0000030C
61 #define BA0_PCICFG10 0x00000310
62 #define BA0_PCICFG14 0x00000314
63 #define BA0_PCICFG18 0x00000318
64 #define BA0_PCICFG1C 0x0000031C
65 #define BA0_PCICFG20 0x00000320
66 #define BA0_PCICFG24 0x00000324
67 #define BA0_PCICFG28 0x00000328
68 #define BA0_PCICFG2C 0x0000032C
69 #define BA0_PCICFG30 0x00000330
70 #define BA0_PCICFG34 0x00000334
71 #define BA0_PCICFG38 0x00000338
72 #define BA0_PCICFG3C 0x0000033C
73 #define BA0_CLKCR1 0x00000400
74 #define BA0_CLKCR2 0x00000404
75 #define BA0_PLLM 0x00000408
76 #define BA0_PLLCC 0x0000040C
77 #define BA0_FRR 0x00000410
78 #define BA0_CFL1 0x00000414
79 #define BA0_CFL2 0x00000418
80 #define BA0_SERMC1 0x00000420
81 #define BA0_SERMC2 0x00000424
82 #define BA0_SERC1 0x00000428
83 #define BA0_SERC2 0x0000042C
84 #define BA0_SERC3 0x00000430
85 #define BA0_SERC4 0x00000434
86 #define BA0_SERC5 0x00000438
87 #define BA0_SERBSP 0x0000043C
88 #define BA0_SERBST 0x00000440
89 #define BA0_SERBCM 0x00000444
90 #define BA0_SERBAD 0x00000448
91 #define BA0_SERBCF 0x0000044C
92 #define BA0_SERBWP 0x00000450
93 #define BA0_SERBRP 0x00000454
94 #ifndef NO_CS4612
95 #define BA0_ASER_FADDR 0x00000458
96 #endif
97 #define BA0_ACCTL 0x00000460
98 #define BA0_ACSTS 0x00000464
99 #define BA0_ACOSV 0x00000468
100 #define BA0_ACCAD 0x0000046C
101 #define BA0_ACCDA 0x00000470
102 #define BA0_ACISV 0x00000474
103 #define BA0_ACSAD 0x00000478
104 #define BA0_ACSDA 0x0000047C
105 #define BA0_JSPT 0x00000480
106 #define BA0_JSCTL 0x00000484
107 #define BA0_JSC1 0x00000488
108 #define BA0_JSC2 0x0000048C
109 #define BA0_MIDCR 0x00000490
110 #define BA0_MIDSR 0x00000494
111 #define BA0_MIDWP 0x00000498
112 #define BA0_MIDRP 0x0000049C
113 #define BA0_JSIO 0x000004A0
114 #ifndef NO_CS4612
115 #define BA0_ASER_MASTER 0x000004A4
116 #endif
117 #define BA0_CFGI 0x000004B0
118 #define BA0_SSVID 0x000004B4
119 #define BA0_GPIOR 0x000004B8
120 #ifndef NO_CS4612
121 #define BA0_EGPIODR 0x000004BC
122 #define BA0_EGPIOPTR 0x000004C0
123 #define BA0_EGPIOTR 0x000004C4
124 #define BA0_EGPIOWR 0x000004C8
125 #define BA0_EGPIOSR 0x000004CC
126 #define BA0_SERC6 0x000004D0
127 #define BA0_SERC7 0x000004D4
128 #define BA0_SERACC 0x000004D8
129 #define BA0_ACCTL2 0x000004E0
130 #define BA0_ACSTS2 0x000004E4
131 #define BA0_ACOSV2 0x000004E8
132 #define BA0_ACCAD2 0x000004EC
133 #define BA0_ACCDA2 0x000004F0
134 #define BA0_ACISV2 0x000004F4
135 #define BA0_ACSAD2 0x000004F8
136 #define BA0_ACSDA2 0x000004FC
137 #define BA0_IOTAC0 0x00000500
138 #define BA0_IOTAC1 0x00000504
139 #define BA0_IOTAC2 0x00000508
140 #define BA0_IOTAC3 0x0000050C
141 #define BA0_IOTAC4 0x00000510
142 #define BA0_IOTAC5 0x00000514
143 #define BA0_IOTAC6 0x00000518
144 #define BA0_IOTAC7 0x0000051C
145 #define BA0_IOTAC8 0x00000520
146 #define BA0_IOTAC9 0x00000524
147 #define BA0_IOTAC10 0x00000528
148 #define BA0_IOTAC11 0x0000052C
149 #define BA0_IOTFR0 0x00000540
150 #define BA0_IOTFR1 0x00000544
151 #define BA0_IOTFR2 0x00000548
152 #define BA0_IOTFR3 0x0000054C
153 #define BA0_IOTFR4 0x00000550
154 #define BA0_IOTFR5 0x00000554
155 #define BA0_IOTFR6 0x00000558
156 #define BA0_IOTFR7 0x0000055C
157 #define BA0_IOTFIFO 0x00000580
158 #define BA0_IOTRRD 0x00000584
159 #define BA0_IOTFP 0x00000588
160 #define BA0_IOTCR 0x0000058C
161 #define BA0_DPCID 0x00000590
162 #define BA0_DPCIA 0x00000594
163 #define BA0_DPCIC 0x00000598
164 #define BA0_PCPCIR 0x00000600
165 #define BA0_PCPCIG 0x00000604
166 #define BA0_PCPCIEN 0x00000608
167 #define BA0_EPCIPMC 0x00000610
168 #endif
169
170 /*
171 * The following define the offsets of the registers and memories accessed via
172 * base address register one on the CS461x part.
173 */
174 #define BA1_SP_DMEM0 0x00000000
175 #define BA1_SP_DMEM1 0x00010000
176 #define BA1_SP_PMEM 0x00020000
177 #define BA1_SP_REG 0x00030000
178 #define BA1_SPCR 0x00030000
179 #define BA1_DREG 0x00030004
180 #define BA1_DSRWP 0x00030008
181 #define BA1_TWPR 0x0003000C
182 #define BA1_SPWR 0x00030010
183 #define BA1_SPIR 0x00030014
184 #define BA1_FGR1 0x00030020
185 #define BA1_SPCS 0x00030028
186 #define BA1_SDSR 0x0003002C
187 #define BA1_FRMT 0x00030030
188 #define BA1_FRCC 0x00030034
189 #define BA1_FRSC 0x00030038
190 #define BA1_OMNI_MEM 0x000E0000
191
192 /*
193 * The following defines are for the flags in the host interrupt status
194 * register.
195 */
196 #define HISR_VC_MASK 0x0000FFFF
197 #define HISR_VC0 0x00000001
198 #define HISR_VC1 0x00000002
199 #define HISR_VC2 0x00000004
200 #define HISR_VC3 0x00000008
201 #define HISR_VC4 0x00000010
202 #define HISR_VC5 0x00000020
203 #define HISR_VC6 0x00000040
204 #define HISR_VC7 0x00000080
205 #define HISR_VC8 0x00000100
206 #define HISR_VC9 0x00000200
207 #define HISR_VC10 0x00000400
208 #define HISR_VC11 0x00000800
209 #define HISR_VC12 0x00001000
210 #define HISR_VC13 0x00002000
211 #define HISR_VC14 0x00004000
212 #define HISR_VC15 0x00008000
213 #define HISR_INT0 0x00010000
214 #define HISR_INT1 0x00020000
215 #define HISR_DMAI 0x00040000
216 #define HISR_FROVR 0x00080000
217 #define HISR_MIDI 0x00100000
218 #ifdef NO_CS4612
219 #define HISR_RESERVED 0x0FE00000
220 #else
221 #define HISR_SBINT 0x00200000
222 #define HISR_RESERVED 0x0FC00000
223 #endif
224 #define HISR_H0P 0x40000000
225 #define HISR_INTENA 0x80000000
226
227 /*
228 * The following defines are for the flags in the host signal register 0.
229 */
230 #define HSR0_VC_MASK 0xFFFFFFFF
231 #define HSR0_VC16 0x00000001
232 #define HSR0_VC17 0x00000002
233 #define HSR0_VC18 0x00000004
234 #define HSR0_VC19 0x00000008
235 #define HSR0_VC20 0x00000010
236 #define HSR0_VC21 0x00000020
237 #define HSR0_VC22 0x00000040
238 #define HSR0_VC23 0x00000080
239 #define HSR0_VC24 0x00000100
240 #define HSR0_VC25 0x00000200
241 #define HSR0_VC26 0x00000400
242 #define HSR0_VC27 0x00000800
243 #define HSR0_VC28 0x00001000
244 #define HSR0_VC29 0x00002000
245 #define HSR0_VC30 0x00004000
246 #define HSR0_VC31 0x00008000
247 #define HSR0_VC32 0x00010000
248 #define HSR0_VC33 0x00020000
249 #define HSR0_VC34 0x00040000
250 #define HSR0_VC35 0x00080000
251 #define HSR0_VC36 0x00100000
252 #define HSR0_VC37 0x00200000
253 #define HSR0_VC38 0x00400000
254 #define HSR0_VC39 0x00800000
255 #define HSR0_VC40 0x01000000
256 #define HSR0_VC41 0x02000000
257 #define HSR0_VC42 0x04000000
258 #define HSR0_VC43 0x08000000
259 #define HSR0_VC44 0x10000000
260 #define HSR0_VC45 0x20000000
261 #define HSR0_VC46 0x40000000
262 #define HSR0_VC47 0x80000000
263
264 /*
265 * The following defines are for the flags in the host interrupt control
266 * register.
267 */
268 #define HICR_IEV 0x00000001
269 #define HICR_CHGM 0x00000002
270
271 /*
272 * The following defines are for the flags in the DMA status register.
273 */
274 #define DMSR_HP 0x00000001
275 #define DMSR_HR 0x00000002
276 #define DMSR_SP 0x00000004
277 #define DMSR_SR 0x00000008
278
279 /*
280 * The following defines are for the flags in the host DMA source address
281 * register.
282 */
283 #define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
284 #define HSAR_DSP_ADDR_MASK 0x0000FFFF
285 #define HSAR_MEMID_MASK 0x000F0000
286 #define HSAR_MEMID_SP_DMEM0 0x00000000
287 #define HSAR_MEMID_SP_DMEM1 0x00010000
288 #define HSAR_MEMID_SP_PMEM 0x00020000
289 #define HSAR_MEMID_SP_DEBUG 0x00030000
290 #define HSAR_MEMID_OMNI_MEM 0x000E0000
291 #define HSAR_END 0x40000000
292 #define HSAR_ERR 0x80000000
293
294 /*
295 * The following defines are for the flags in the host DMA destination address
296 * register.
297 */
298 #define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
299 #define HDAR_DSP_ADDR_MASK 0x0000FFFF
300 #define HDAR_MEMID_MASK 0x000F0000
301 #define HDAR_MEMID_SP_DMEM0 0x00000000
302 #define HDAR_MEMID_SP_DMEM1 0x00010000
303 #define HDAR_MEMID_SP_PMEM 0x00020000
304 #define HDAR_MEMID_SP_DEBUG 0x00030000
305 #define HDAR_MEMID_OMNI_MEM 0x000E0000
306 #define HDAR_END 0x40000000
307 #define HDAR_ERR 0x80000000
308
309 /*
310 * The following defines are for the flags in the host DMA control register.
311 */
312 #define HDMR_AC_MASK 0x0000F000
313 #define HDMR_AC_8_16 0x00001000
314 #define HDMR_AC_M_S 0x00002000
315 #define HDMR_AC_B_L 0x00004000
316 #define HDMR_AC_S_U 0x00008000
317
318 /*
319 * The following defines are for the flags in the host DMA control register.
320 */
321 #define HDCR_COUNT_MASK 0x000003FF
322 #define HDCR_DONE 0x00004000
323 #define HDCR_OPT 0x00008000
324 #define HDCR_WBD 0x00400000
325 #define HDCR_WBS 0x00800000
326 #define HDCR_DMS_MASK 0x07000000
327 #define HDCR_DMS_LINEAR 0x00000000
328 #define HDCR_DMS_16_DWORDS 0x01000000
329 #define HDCR_DMS_32_DWORDS 0x02000000
330 #define HDCR_DMS_64_DWORDS 0x03000000
331 #define HDCR_DMS_128_DWORDS 0x04000000
332 #define HDCR_DMS_256_DWORDS 0x05000000
333 #define HDCR_DMS_512_DWORDS 0x06000000
334 #define HDCR_DMS_1024_DWORDS 0x07000000
335 #define HDCR_DH 0x08000000
336 #define HDCR_SMS_MASK 0x70000000
337 #define HDCR_SMS_LINEAR 0x00000000
338 #define HDCR_SMS_16_DWORDS 0x10000000
339 #define HDCR_SMS_32_DWORDS 0x20000000
340 #define HDCR_SMS_64_DWORDS 0x30000000
341 #define HDCR_SMS_128_DWORDS 0x40000000
342 #define HDCR_SMS_256_DWORDS 0x50000000
343 #define HDCR_SMS_512_DWORDS 0x60000000
344 #define HDCR_SMS_1024_DWORDS 0x70000000
345 #define HDCR_SH 0x80000000
346 #define HDCR_COUNT_SHIFT 0
347
348 /*
349 * The following defines are for the flags in the performance monitor control
350 * register.
351 */
352 #define PFMC_C1SS_MASK 0x0000001F
353 #define PFMC_C1EV 0x00000020
354 #define PFMC_C1RS 0x00008000
355 #define PFMC_C2SS_MASK 0x001F0000
356 #define PFMC_C2EV 0x00200000
357 #define PFMC_C2RS 0x80000000
358 #define PFMC_C1SS_SHIFT 0
359 #define PFMC_C2SS_SHIFT 16
360 #define PFMC_BUS_GRANT 0
361 #define PFMC_GRANT_AFTER_REQ 1
362 #define PFMC_TRANSACTION 2
363 #define PFMC_DWORD_TRANSFER 3
364 #define PFMC_SLAVE_READ 4
365 #define PFMC_SLAVE_WRITE 5
366 #define PFMC_PREEMPTION 6
367 #define PFMC_DISCONNECT_RETRY 7
368 #define PFMC_INTERRUPT 8
369 #define PFMC_BUS_OWNERSHIP 9
370 #define PFMC_TRANSACTION_LAG 10
371 #define PFMC_PCI_CLOCK 11
372 #define PFMC_SERIAL_CLOCK 12
373 #define PFMC_SP_CLOCK 13
374
375 /*
376 * The following defines are for the flags in the performance counter value 1
377 * register.
378 */
379 #define PFCV1_PC1V_MASK 0xFFFFFFFF
380 #define PFCV1_PC1V_SHIFT 0
381
382 /*
383 * The following defines are for the flags in the performance counter value 2
384 * register.
385 */
386 #define PFCV2_PC2V_MASK 0xFFFFFFFF
387 #define PFCV2_PC2V_SHIFT 0
388
389 /*
390 * The following defines are for the flags in the clock control register 1.
391 */
392 #define CLKCR1_OSCS 0x00000001
393 #define CLKCR1_OSCP 0x00000002
394 #define CLKCR1_PLLSS_MASK 0x0000000C
395 #define CLKCR1_PLLSS_SERIAL 0x00000000
396 #define CLKCR1_PLLSS_CRYSTAL 0x00000004
397 #define CLKCR1_PLLSS_PCI 0x00000008
398 #define CLKCR1_PLLSS_RESERVED 0x0000000C
399 #define CLKCR1_PLLP 0x00000010
400 #define CLKCR1_SWCE 0x00000020
401 #define CLKCR1_PLLOS 0x00000040
402
403 /*
404 * The following defines are for the flags in the clock control register 2.
405 */
406 #define CLKCR2_PDIVS_MASK 0x0000000F
407 #define CLKCR2_PDIVS_1 0x00000001
408 #define CLKCR2_PDIVS_2 0x00000002
409 #define CLKCR2_PDIVS_4 0x00000004
410 #define CLKCR2_PDIVS_7 0x00000007
411 #define CLKCR2_PDIVS_8 0x00000008
412 #define CLKCR2_PDIVS_16 0x00000000
413
414 /*
415 * The following defines are for the flags in the PLL multiplier register.
416 */
417 #define PLLM_MASK 0x000000FF
418 #define PLLM_SHIFT 0
419
420 /*
421 * The following defines are for the flags in the PLL capacitor coefficient
422 * register.
423 */
424 #define PLLCC_CDR_MASK 0x00000007
425 #ifndef NO_CS4610
426 #define PLLCC_CDR_240_350_MHZ 0x00000000
427 #define PLLCC_CDR_184_265_MHZ 0x00000001
428 #define PLLCC_CDR_144_205_MHZ 0x00000002
429 #define PLLCC_CDR_111_160_MHZ 0x00000003
430 #define PLLCC_CDR_87_123_MHZ 0x00000004
431 #define PLLCC_CDR_67_96_MHZ 0x00000005
432 #define PLLCC_CDR_52_74_MHZ 0x00000006
433 #define PLLCC_CDR_45_58_MHZ 0x00000007
434 #endif
435 #ifndef NO_CS4612
436 #define PLLCC_CDR_271_398_MHZ 0x00000000
437 #define PLLCC_CDR_227_330_MHZ 0x00000001
438 #define PLLCC_CDR_167_239_MHZ 0x00000002
439 #define PLLCC_CDR_150_215_MHZ 0x00000003
440 #define PLLCC_CDR_107_154_MHZ 0x00000004
441 #define PLLCC_CDR_98_140_MHZ 0x00000005
442 #define PLLCC_CDR_73_104_MHZ 0x00000006
443 #define PLLCC_CDR_63_90_MHZ 0x00000007
444 #endif
445 #define PLLCC_LPF_MASK 0x000000F8
446 #ifndef NO_CS4610
447 #define PLLCC_LPF_23850_60000_KHZ 0x00000000
448 #define PLLCC_LPF_7960_26290_KHZ 0x00000008
449 #define PLLCC_LPF_4160_10980_KHZ 0x00000018
450 #define PLLCC_LPF_1740_4580_KHZ 0x00000038
451 #define PLLCC_LPF_724_1910_KHZ 0x00000078
452 #define PLLCC_LPF_317_798_KHZ 0x000000F8
453 #endif
454 #ifndef NO_CS4612
455 #define PLLCC_LPF_25580_64530_KHZ 0x00000000
456 #define PLLCC_LPF_14360_37270_KHZ 0x00000008
457 #define PLLCC_LPF_6100_16020_KHZ 0x00000018
458 #define PLLCC_LPF_2540_6690_KHZ 0x00000038
459 #define PLLCC_LPF_1050_2780_KHZ 0x00000078
460 #define PLLCC_LPF_450_1160_KHZ 0x000000F8
461 #endif
462
463 /*
464 * The following defines are for the flags in the feature reporting register.
465 */
466 #define FRR_FAB_MASK 0x00000003
467 #define FRR_MASK_MASK 0x0000001C
468 #ifdef NO_CS4612
469 #define FRR_CFOP_MASK 0x000000E0
470 #else
471 #define FRR_CFOP_MASK 0x00000FE0
472 #endif
473 #define FRR_CFOP_NOT_DVD 0x00000020
474 #define FRR_CFOP_A3D 0x00000040
475 #define FRR_CFOP_128_PIN 0x00000080
476 #ifndef NO_CS4612
477 #define FRR_CFOP_CS4280 0x00000800
478 #endif
479 #define FRR_FAB_SHIFT 0
480 #define FRR_MASK_SHIFT 2
481 #define FRR_CFOP_SHIFT 5
482
483 /*
484 * The following defines are for the flags in the configuration load 1
485 * register.
486 */
487 #define CFL1_CLOCK_SOURCE_MASK 0x00000003
488 #define CFL1_CLOCK_SOURCE_CS423X 0x00000000
489 #define CFL1_CLOCK_SOURCE_AC97 0x00000001
490 #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
491 #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
492 #define CFL1_VALID_DATA_MASK 0x000000FF
493
494 /*
495 * The following defines are for the flags in the configuration load 2
496 * register.
497 */
498 #define CFL2_VALID_DATA_MASK 0x000000FF
499
500 /*
501 * The following defines are for the flags in the serial port master control
502 * register 1.
503 */
504 #define SERMC1_MSPE 0x00000001
505 #define SERMC1_PTC_MASK 0x0000000E
506 #define SERMC1_PTC_CS423X 0x00000000
507 #define SERMC1_PTC_AC97 0x00000002
508 #define SERMC1_PTC_DAC 0x00000004
509 #define SERMC1_PLB 0x00000010
510 #define SERMC1_XLB 0x00000020
511
512 /*
513 * The following defines are for the flags in the serial port master control
514 * register 2.
515 */
516 #define SERMC2_LROE 0x00000001
517 #define SERMC2_MCOE 0x00000002
518 #define SERMC2_MCDIV 0x00000004
519
520 /*
521 * The following defines are for the flags in the serial port 1 configuration
522 * register.
523 */
524 #define SERC1_SO1EN 0x00000001
525 #define SERC1_SO1F_MASK 0x0000000E
526 #define SERC1_SO1F_CS423X 0x00000000
527 #define SERC1_SO1F_AC97 0x00000002
528 #define SERC1_SO1F_DAC 0x00000004
529 #define SERC1_SO1F_SPDIF 0x00000006
530
531 /*
532 * The following defines are for the flags in the serial port 2 configuration
533 * register.
534 */
535 #define SERC2_SI1EN 0x00000001
536 #define SERC2_SI1F_MASK 0x0000000E
537 #define SERC2_SI1F_CS423X 0x00000000
538 #define SERC2_SI1F_AC97 0x00000002
539 #define SERC2_SI1F_ADC 0x00000004
540 #define SERC2_SI1F_SPDIF 0x00000006
541
542 /*
543 * The following defines are for the flags in the serial port 3 configuration
544 * register.
545 */
546 #define SERC3_SO2EN 0x00000001
547 #define SERC3_SO2F_MASK 0x00000006
548 #define SERC3_SO2F_DAC 0x00000000
549 #define SERC3_SO2F_SPDIF 0x00000002
550
551 /*
552 * The following defines are for the flags in the serial port 4 configuration
553 * register.
554 */
555 #define SERC4_SO3EN 0x00000001
556 #define SERC4_SO3F_MASK 0x00000006
557 #define SERC4_SO3F_DAC 0x00000000
558 #define SERC4_SO3F_SPDIF 0x00000002
559
560 /*
561 * The following defines are for the flags in the serial port 5 configuration
562 * register.
563 */
564 #define SERC5_SI2EN 0x00000001
565 #define SERC5_SI2F_MASK 0x00000006
566 #define SERC5_SI2F_ADC 0x00000000
567 #define SERC5_SI2F_SPDIF 0x00000002
568
569 /*
570 * The following defines are for the flags in the serial port backdoor sample
571 * pointer register.
572 */
573 #define SERBSP_FSP_MASK 0x0000000F
574 #define SERBSP_FSP_SHIFT 0
575
576 /*
577 * The following defines are for the flags in the serial port backdoor status
578 * register.
579 */
580 #define SERBST_RRDY 0x00000001
581 #define SERBST_WBSY 0x00000002
582
583 /*
584 * The following defines are for the flags in the serial port backdoor command
585 * register.
586 */
587 #define SERBCM_RDC 0x00000001
588 #define SERBCM_WRC 0x00000002
589
590 /*
591 * The following defines are for the flags in the serial port backdoor address
592 * register.
593 */
594 #ifdef NO_CS4612
595 #define SERBAD_FAD_MASK 0x000000FF
596 #else
597 #define SERBAD_FAD_MASK 0x000001FF
598 #endif
599 #define SERBAD_FAD_SHIFT 0
600
601 /*
602 * The following defines are for the flags in the serial port backdoor
603 * configuration register.
604 */
605 #define SERBCF_HBP 0x00000001
606
607 /*
608 * The following defines are for the flags in the serial port backdoor write
609 * port register.
610 */
611 #define SERBWP_FWD_MASK 0x000FFFFF
612 #define SERBWP_FWD_SHIFT 0
613
614 /*
615 * The following defines are for the flags in the serial port backdoor read
616 * port register.
617 */
618 #define SERBRP_FRD_MASK 0x000FFFFF
619 #define SERBRP_FRD_SHIFT 0
620
621 /*
622 * The following defines are for the flags in the async FIFO address register.
623 */
624 #ifndef NO_CS4612
625 #define ASER_FADDR_A1_MASK 0x000001FF
626 #define ASER_FADDR_EN1 0x00008000
627 #define ASER_FADDR_A2_MASK 0x01FF0000
628 #define ASER_FADDR_EN2 0x80000000
629 #define ASER_FADDR_A1_SHIFT 0
630 #define ASER_FADDR_A2_SHIFT 16
631 #endif
632
633 /*
634 * The following defines are for the flags in the AC97 control register.
635 */
636 #define ACCTL_RSTN 0x00000001
637 #define ACCTL_ESYN 0x00000002
638 #define ACCTL_VFRM 0x00000004
639 #define ACCTL_DCV 0x00000008
640 #define ACCTL_CRW 0x00000010
641 #define ACCTL_ASYN 0x00000020
642 #ifndef NO_CS4612
643 #define ACCTL_TC 0x00000040
644 #endif
645
646 /*
647 * The following defines are for the flags in the AC97 status register.
648 */
649 #define ACSTS_CRDY 0x00000001
650 #define ACSTS_VSTS 0x00000002
651 #ifndef NO_CS4612
652 #define ACSTS_WKUP 0x00000004
653 #endif
654
655 /*
656 * The following defines are for the flags in the AC97 output slot valid
657 * register.
658 */
659 #define ACOSV_SLV3 0x00000001
660 #define ACOSV_SLV4 0x00000002
661 #define ACOSV_SLV5 0x00000004
662 #define ACOSV_SLV6 0x00000008
663 #define ACOSV_SLV7 0x00000010
664 #define ACOSV_SLV8 0x00000020
665 #define ACOSV_SLV9 0x00000040
666 #define ACOSV_SLV10 0x00000080
667 #define ACOSV_SLV11 0x00000100
668 #define ACOSV_SLV12 0x00000200
669
670 /*
671 * The following defines are for the flags in the AC97 command address
672 * register.
673 */
674 #define ACCAD_CI_MASK 0x0000007F
675 #define ACCAD_CI_SHIFT 0
676
677 /*
678 * The following defines are for the flags in the AC97 command data register.
679 */
680 #define ACCDA_CD_MASK 0x0000FFFF
681 #define ACCDA_CD_SHIFT 0
682
683 /*
684 * The following defines are for the flags in the AC97 input slot valid
685 * register.
686 */
687 #define ACISV_ISV3 0x00000001
688 #define ACISV_ISV4 0x00000002
689 #define ACISV_ISV5 0x00000004
690 #define ACISV_ISV6 0x00000008
691 #define ACISV_ISV7 0x00000010
692 #define ACISV_ISV8 0x00000020
693 #define ACISV_ISV9 0x00000040
694 #define ACISV_ISV10 0x00000080
695 #define ACISV_ISV11 0x00000100
696 #define ACISV_ISV12 0x00000200
697
698 /*
699 * The following defines are for the flags in the AC97 status address
700 * register.
701 */
702 #define ACSAD_SI_MASK 0x0000007F
703 #define ACSAD_SI_SHIFT 0
704
705 /*
706 * The following defines are for the flags in the AC97 status data register.
707 */
708 #define ACSDA_SD_MASK 0x0000FFFF
709 #define ACSDA_SD_SHIFT 0
710
711 /*
712 * The following defines are for the flags in the joystick poll/trigger
713 * register.
714 */
715 #define JSPT_CAX 0x00000001
716 #define JSPT_CAY 0x00000002
717 #define JSPT_CBX 0x00000004
718 #define JSPT_CBY 0x00000008
719 #define JSPT_BA1 0x00000010
720 #define JSPT_BA2 0x00000020
721 #define JSPT_BB1 0x00000040
722 #define JSPT_BB2 0x00000080
723
724 /*
725 * The following defines are for the flags in the joystick control register.
726 */
727 #define JSCTL_SP_MASK 0x00000003
728 #define JSCTL_SP_SLOW 0x00000000
729 #define JSCTL_SP_MEDIUM_SLOW 0x00000001
730 #define JSCTL_SP_MEDIUM_FAST 0x00000002
731 #define JSCTL_SP_FAST 0x00000003
732 #define JSCTL_ARE 0x00000004
733
734 /*
735 * The following defines are for the flags in the joystick coordinate pair 1
736 * readback register.
737 */
738 #define JSC1_Y1V_MASK 0x0000FFFF
739 #define JSC1_X1V_MASK 0xFFFF0000
740 #define JSC1_Y1V_SHIFT 0
741 #define JSC1_X1V_SHIFT 16
742
743 /*
744 * The following defines are for the flags in the joystick coordinate pair 2
745 * readback register.
746 */
747 #define JSC2_Y2V_MASK 0x0000FFFF
748 #define JSC2_X2V_MASK 0xFFFF0000
749 #define JSC2_Y2V_SHIFT 0
750 #define JSC2_X2V_SHIFT 16
751
752 /*
753 * The following defines are for the flags in the MIDI control register.
754 */
755 #define MIDCR_TXE 0x00000001 /* Enable transmitting. */
756 #define MIDCR_RXE 0x00000002 /* Enable receiving. */
757 #define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
758 #define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
759 #define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
760 #define MIDCR_MRST 0x00000020 /* Reset interface. */
761
762 /*
763 * The following defines are for the flags in the MIDI status register.
764 */
765 #define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
766 #define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
767
768 /*
769 * The following defines are for the flags in the MIDI write port register.
770 */
771 #define MIDWP_MWD_MASK 0x000000FF
772 #define MIDWP_MWD_SHIFT 0
773
774 /*
775 * The following defines are for the flags in the MIDI read port register.
776 */
777 #define MIDRP_MRD_MASK 0x000000FF
778 #define MIDRP_MRD_SHIFT 0
779
780 /*
781 * The following defines are for the flags in the joystick GPIO register.
782 */
783 #define JSIO_DAX 0x00000001
784 #define JSIO_DAY 0x00000002
785 #define JSIO_DBX 0x00000004
786 #define JSIO_DBY 0x00000008
787 #define JSIO_AXOE 0x00000010
788 #define JSIO_AYOE 0x00000020
789 #define JSIO_BXOE 0x00000040
790 #define JSIO_BYOE 0x00000080
791
792 /*
793 * The following defines are for the flags in the master async/sync serial
794 * port enable register.
795 */
796 #ifndef NO_CS4612
797 #define ASER_MASTER_ME 0x00000001
798 #endif
799
800 /*
801 * The following defines are for the flags in the configuration interface
802 * register.
803 */
804 #define CFGI_CLK 0x00000001
805 #define CFGI_DOUT 0x00000002
806 #define CFGI_DIN_EEN 0x00000004
807 #define CFGI_EELD 0x00000008
808
809 /*
810 * The following defines are for the flags in the subsystem ID and vendor ID
811 * register.
812 */
813 #define SSVID_VID_MASK 0x0000FFFF
814 #define SSVID_SID_MASK 0xFFFF0000
815 #define SSVID_VID_SHIFT 0
816 #define SSVID_SID_SHIFT 16
817
818 /*
819 * The following defines are for the flags in the GPIO pin interface register.
820 */
821 #define GPIOR_VOLDN 0x00000001
822 #define GPIOR_VOLUP 0x00000002
823 #define GPIOR_SI2D 0x00000004
824 #define GPIOR_SI2OE 0x00000008
825
826 /*
827 * The following defines are for the flags in the extended GPIO pin direction
828 * register.
829 */
830 #ifndef NO_CS4612
831 #define EGPIODR_GPOE0 0x00000001
832 #define EGPIODR_GPOE1 0x00000002
833 #define EGPIODR_GPOE2 0x00000004
834 #define EGPIODR_GPOE3 0x00000008
835 #define EGPIODR_GPOE4 0x00000010
836 #define EGPIODR_GPOE5 0x00000020
837 #define EGPIODR_GPOE6 0x00000040
838 #define EGPIODR_GPOE7 0x00000080
839 #define EGPIODR_GPOE8 0x00000100
840 #endif
841
842 /*
843 * The following defines are for the flags in the extended GPIO pin polarity/
844 * type register.
845 */
846 #ifndef NO_CS4612
847 #define EGPIOPTR_GPPT0 0x00000001
848 #define EGPIOPTR_GPPT1 0x00000002
849 #define EGPIOPTR_GPPT2 0x00000004
850 #define EGPIOPTR_GPPT3 0x00000008
851 #define EGPIOPTR_GPPT4 0x00000010
852 #define EGPIOPTR_GPPT5 0x00000020
853 #define EGPIOPTR_GPPT6 0x00000040
854 #define EGPIOPTR_GPPT7 0x00000080
855 #define EGPIOPTR_GPPT8 0x00000100
856 #endif
857
858 /*
859 * The following defines are for the flags in the extended GPIO pin sticky
860 * register.
861 */
862 #ifndef NO_CS4612
863 #define EGPIOTR_GPS0 0x00000001
864 #define EGPIOTR_GPS1 0x00000002
865 #define EGPIOTR_GPS2 0x00000004
866 #define EGPIOTR_GPS3 0x00000008
867 #define EGPIOTR_GPS4 0x00000010
868 #define EGPIOTR_GPS5 0x00000020
869 #define EGPIOTR_GPS6 0x00000040
870 #define EGPIOTR_GPS7 0x00000080
871 #define EGPIOTR_GPS8 0x00000100
872 #endif
873
874 /*
875 * The following defines are for the flags in the extended GPIO ping wakeup
876 * register.
877 */
878 #ifndef NO_CS4612
879 #define EGPIOWR_GPW0 0x00000001
880 #define EGPIOWR_GPW1 0x00000002
881 #define EGPIOWR_GPW2 0x00000004
882 #define EGPIOWR_GPW3 0x00000008
883 #define EGPIOWR_GPW4 0x00000010
884 #define EGPIOWR_GPW5 0x00000020
885 #define EGPIOWR_GPW6 0x00000040
886 #define EGPIOWR_GPW7 0x00000080
887 #define EGPIOWR_GPW8 0x00000100
888 #endif
889
890 /*
891 * The following defines are for the flags in the extended GPIO pin status
892 * register.
893 */
894 #ifndef NO_CS4612
895 #define EGPIOSR_GPS0 0x00000001
896 #define EGPIOSR_GPS1 0x00000002
897 #define EGPIOSR_GPS2 0x00000004
898 #define EGPIOSR_GPS3 0x00000008
899 #define EGPIOSR_GPS4 0x00000010
900 #define EGPIOSR_GPS5 0x00000020
901 #define EGPIOSR_GPS6 0x00000040
902 #define EGPIOSR_GPS7 0x00000080
903 #define EGPIOSR_GPS8 0x00000100
904 #endif
905
906 /*
907 * The following defines are for the flags in the serial port 6 configuration
908 * register.
909 */
910 #ifndef NO_CS4612
911 #define SERC6_ASDO2EN 0x00000001
912 #endif
913
914 /*
915 * The following defines are for the flags in the serial port 7 configuration
916 * register.
917 */
918 #ifndef NO_CS4612
919 #define SERC7_ASDI2EN 0x00000001
920 #define SERC7_POSILB 0x00000002
921 #define SERC7_SIPOLB 0x00000004
922 #define SERC7_SOSILB 0x00000008
923 #define SERC7_SISOLB 0x00000010
924 #endif
925
926 /*
927 * The following defines are for the flags in the serial port AC link
928 * configuration register.
929 */
930 #ifndef NO_CS4612
931 #define SERACC_CODEC_TYPE_MASK 0x00000001
932 #define SERACC_CODEC_TYPE_1_03 0x00000000
933 #define SERACC_CODEC_TYPE_2_0 0x00000001
934 #define SERACC_TWO_CODECS 0x00000002
935 #define SERACC_MDM 0x00000004
936 #define SERACC_HSP 0x00000008
937 #endif
938
939 /*
940 * The following defines are for the flags in the AC97 control register 2.
941 */
942 #ifndef NO_CS4612
943 #define ACCTL2_RSTN 0x00000001
944 #define ACCTL2_ESYN 0x00000002
945 #define ACCTL2_VFRM 0x00000004
946 #define ACCTL2_DCV 0x00000008
947 #define ACCTL2_CRW 0x00000010
948 #define ACCTL2_ASYN 0x00000020
949 #endif
950
951 /*
952 * The following defines are for the flags in the AC97 status register 2.
953 */
954 #ifndef NO_CS4612
955 #define ACSTS2_CRDY 0x00000001
956 #define ACSTS2_VSTS 0x00000002
957 #endif
958
959 /*
960 * The following defines are for the flags in the AC97 output slot valid
961 * register 2.
962 */
963 #ifndef NO_CS4612
964 #define ACOSV2_SLV3 0x00000001
965 #define ACOSV2_SLV4 0x00000002
966 #define ACOSV2_SLV5 0x00000004
967 #define ACOSV2_SLV6 0x00000008
968 #define ACOSV2_SLV7 0x00000010
969 #define ACOSV2_SLV8 0x00000020
970 #define ACOSV2_SLV9 0x00000040
971 #define ACOSV2_SLV10 0x00000080
972 #define ACOSV2_SLV11 0x00000100
973 #define ACOSV2_SLV12 0x00000200
974 #endif
975
976 /*
977 * The following defines are for the flags in the AC97 command address
978 * register 2.
979 */
980 #ifndef NO_CS4612
981 #define ACCAD2_CI_MASK 0x0000007F
982 #define ACCAD2_CI_SHIFT 0
983 #endif
984
985 /*
986 * The following defines are for the flags in the AC97 command data register
987 * 2.
988 */
989 #ifndef NO_CS4612
990 #define ACCDA2_CD_MASK 0x0000FFFF
991 #define ACCDA2_CD_SHIFT 0
992 #endif
993
994 /*
995 * The following defines are for the flags in the AC97 input slot valid
996 * register 2.
997 */
998 #ifndef NO_CS4612
999 #define ACISV2_ISV3 0x00000001
1000 #define ACISV2_ISV4 0x00000002
1001 #define ACISV2_ISV5 0x00000004
1002 #define ACISV2_ISV6 0x00000008
1003 #define ACISV2_ISV7 0x00000010
1004 #define ACISV2_ISV8 0x00000020
1005 #define ACISV2_ISV9 0x00000040
1006 #define ACISV2_ISV10 0x00000080
1007 #define ACISV2_ISV11 0x00000100
1008 #define ACISV2_ISV12 0x00000200
1009 #endif
1010
1011 /*
1012 * The following defines are for the flags in the AC97 status address
1013 * register 2.
1014 */
1015 #ifndef NO_CS4612
1016 #define ACSAD2_SI_MASK 0x0000007F
1017 #define ACSAD2_SI_SHIFT 0
1018 #endif
1019
1020 /*
1021 * The following defines are for the flags in the AC97 status data register 2.
1022 */
1023 #ifndef NO_CS4612
1024 #define ACSDA2_SD_MASK 0x0000FFFF
1025 #define ACSDA2_SD_SHIFT 0
1026 #endif
1027
1028 /*
1029 * The following defines are for the flags in the I/O trap address and control
1030 * registers (all 12).
1031 */
1032 #ifndef NO_CS4612
1033 #define IOTAC_SA_MASK 0x0000FFFF
1034 #define IOTAC_MSK_MASK 0x000F0000
1035 #define IOTAC_IODC_MASK 0x06000000
1036 #define IOTAC_IODC_16_BIT 0x00000000
1037 #define IOTAC_IODC_10_BIT 0x02000000
1038 #define IOTAC_IODC_12_BIT 0x04000000
1039 #define IOTAC_WSPI 0x08000000
1040 #define IOTAC_RSPI 0x10000000
1041 #define IOTAC_WSE 0x20000000
1042 #define IOTAC_WE 0x40000000
1043 #define IOTAC_RE 0x80000000
1044 #define IOTAC_SA_SHIFT 0
1045 #define IOTAC_MSK_SHIFT 16
1046 #endif
1047
1048 /*
1049 * The following defines are for the flags in the I/O trap fast read registers
1050 * (all 8).
1051 */
1052 #ifndef NO_CS4612
1053 #define IOTFR_D_MASK 0x0000FFFF
1054 #define IOTFR_A_MASK 0x000F0000
1055 #define IOTFR_R_MASK 0x0F000000
1056 #define IOTFR_ALL 0x40000000
1057 #define IOTFR_VL 0x80000000
1058 #define IOTFR_D_SHIFT 0
1059 #define IOTFR_A_SHIFT 16
1060 #define IOTFR_R_SHIFT 24
1061 #endif
1062
1063 /*
1064 * The following defines are for the flags in the I/O trap FIFO register.
1065 */
1066 #ifndef NO_CS4612
1067 #define IOTFIFO_BA_MASK 0x00003FFF
1068 #define IOTFIFO_S_MASK 0x00FF0000
1069 #define IOTFIFO_OF 0x40000000
1070 #define IOTFIFO_SPIOF 0x80000000
1071 #define IOTFIFO_BA_SHIFT 0
1072 #define IOTFIFO_S_SHIFT 16
1073 #endif
1074
1075 /*
1076 * The following defines are for the flags in the I/O trap retry read data
1077 * register.
1078 */
1079 #ifndef NO_CS4612
1080 #define IOTRRD_D_MASK 0x0000FFFF
1081 #define IOTRRD_RDV 0x80000000
1082 #define IOTRRD_D_SHIFT 0
1083 #endif
1084
1085 /*
1086 * The following defines are for the flags in the I/O trap FIFO pointer
1087 * register.
1088 */
1089 #ifndef NO_CS4612
1090 #define IOTFP_CA_MASK 0x00003FFF
1091 #define IOTFP_PA_MASK 0x3FFF0000
1092 #define IOTFP_CA_SHIFT 0
1093 #define IOTFP_PA_SHIFT 16
1094 #endif
1095
1096 /*
1097 * The following defines are for the flags in the I/O trap control register.
1098 */
1099 #ifndef NO_CS4612
1100 #define IOTCR_ITD 0x00000001
1101 #define IOTCR_HRV 0x00000002
1102 #define IOTCR_SRV 0x00000004
1103 #define IOTCR_DTI 0x00000008
1104 #define IOTCR_DFI 0x00000010
1105 #define IOTCR_DDP 0x00000020
1106 #define IOTCR_JTE 0x00000040
1107 #define IOTCR_PPE 0x00000080
1108 #endif
1109
1110 /*
1111 * The following defines are for the flags in the direct PCI data register.
1112 */
1113 #ifndef NO_CS4612
1114 #define DPCID_D_MASK 0xFFFFFFFF
1115 #define DPCID_D_SHIFT 0
1116 #endif
1117
1118 /*
1119 * The following defines are for the flags in the direct PCI address register.
1120 */
1121 #ifndef NO_CS4612
1122 #define DPCIA_A_MASK 0xFFFFFFFF
1123 #define DPCIA_A_SHIFT 0
1124 #endif
1125
1126 /*
1127 * The following defines are for the flags in the direct PCI command register.
1128 */
1129 #ifndef NO_CS4612
1130 #define DPCIC_C_MASK 0x0000000F
1131 #define DPCIC_C_IOREAD 0x00000002
1132 #define DPCIC_C_IOWRITE 0x00000003
1133 #define DPCIC_BE_MASK 0x000000F0
1134 #endif
1135
1136 /*
1137 * The following defines are for the flags in the PC/PCI request register.
1138 */
1139 #ifndef NO_CS4612
1140 #define PCPCIR_RDC_MASK 0x00000007
1141 #define PCPCIR_C_MASK 0x00007000
1142 #define PCPCIR_REQ 0x00008000
1143 #define PCPCIR_RDC_SHIFT 0
1144 #define PCPCIR_C_SHIFT 12
1145 #endif
1146
1147 /*
1148 * The following defines are for the flags in the PC/PCI grant register.
1149 */
1150 #ifndef NO_CS4612
1151 #define PCPCIG_GDC_MASK 0x00000007
1152 #define PCPCIG_VL 0x00008000
1153 #define PCPCIG_GDC_SHIFT 0
1154 #endif
1155
1156 /*
1157 * The following defines are for the flags in the PC/PCI master enable
1158 * register.
1159 */
1160 #ifndef NO_CS4612
1161 #define PCPCIEN_EN 0x00000001
1162 #endif
1163
1164 /*
1165 * The following defines are for the flags in the extended PCI power
1166 * management control register.
1167 */
1168 #ifndef NO_CS4612
1169 #define EPCIPMC_GWU 0x00000001
1170 #define EPCIPMC_FSPC 0x00000002
1171 #endif
1172
1173 /*
1174 * The following defines are for the flags in the SP control register.
1175 */
1176 #define SPCR_RUN 0x00000001
1177 #define SPCR_STPFR 0x00000002
1178 #define SPCR_RUNFR 0x00000004
1179 #define SPCR_TICK 0x00000008
1180 #define SPCR_DRQEN 0x00000020
1181 #define SPCR_RSTSP 0x00000040
1182 #define SPCR_OREN 0x00000080
1183 #ifndef NO_CS4612
1184 #define SPCR_PCIINT 0x00000100
1185 #define SPCR_OINTD 0x00000200
1186 #define SPCR_CRE 0x00008000
1187 #endif
1188
1189 /*
1190 * The following defines are for the flags in the debug index register.
1191 */
1192 #define DREG_REGID_MASK 0x0000007F
1193 #define DREG_DEBUG 0x00000080
1194 #define DREG_RGBK_MASK 0x00000700
1195 #define DREG_TRAP 0x00000800
1196 #if !defined(NO_CS4612)
1197 #if !defined(NO_CS4615)
1198 #define DREG_TRAPX 0x00001000
1199 #endif
1200 #endif
1201 #define DREG_REGID_SHIFT 0
1202 #define DREG_RGBK_SHIFT 8
1203 #define DREG_RGBK_REGID_MASK 0x0000077F
1204 #define DREG_REGID_R0 0x00000010
1205 #define DREG_REGID_R1 0x00000011
1206 #define DREG_REGID_R2 0x00000012
1207 #define DREG_REGID_R3 0x00000013
1208 #define DREG_REGID_R4 0x00000014
1209 #define DREG_REGID_R5 0x00000015
1210 #define DREG_REGID_R6 0x00000016
1211 #define DREG_REGID_R7 0x00000017
1212 #define DREG_REGID_R8 0x00000018
1213 #define DREG_REGID_R9 0x00000019
1214 #define DREG_REGID_RA 0x0000001A
1215 #define DREG_REGID_RB 0x0000001B
1216 #define DREG_REGID_RC 0x0000001C
1217 #define DREG_REGID_RD 0x0000001D
1218 #define DREG_REGID_RE 0x0000001E
1219 #define DREG_REGID_RF 0x0000001F
1220 #define DREG_REGID_RA_BUS_LOW 0x00000020
1221 #define DREG_REGID_RA_BUS_HIGH 0x00000038
1222 #define DREG_REGID_YBUS_LOW 0x00000050
1223 #define DREG_REGID_YBUS_HIGH 0x00000058
1224 #define DREG_REGID_TRAP_0 0x00000100
1225 #define DREG_REGID_TRAP_1 0x00000101
1226 #define DREG_REGID_TRAP_2 0x00000102
1227 #define DREG_REGID_TRAP_3 0x00000103
1228 #define DREG_REGID_TRAP_4 0x00000104
1229 #define DREG_REGID_TRAP_5 0x00000105
1230 #define DREG_REGID_TRAP_6 0x00000106
1231 #define DREG_REGID_TRAP_7 0x00000107
1232 #define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
1233 #define DREG_REGID_TOP_OF_STACK 0x0000010F
1234 #if !defined(NO_CS4612)
1235 #if !defined(NO_CS4615)
1236 #define DREG_REGID_TRAP_8 0x00000110
1237 #define DREG_REGID_TRAP_9 0x00000111
1238 #define DREG_REGID_TRAP_10 0x00000112
1239 #define DREG_REGID_TRAP_11 0x00000113
1240 #define DREG_REGID_TRAP_12 0x00000114
1241 #define DREG_REGID_TRAP_13 0x00000115
1242 #define DREG_REGID_TRAP_14 0x00000116
1243 #define DREG_REGID_TRAP_15 0x00000117
1244 #define DREG_REGID_TRAP_16 0x00000118
1245 #define DREG_REGID_TRAP_17 0x00000119
1246 #define DREG_REGID_TRAP_18 0x0000011A
1247 #define DREG_REGID_TRAP_19 0x0000011B
1248 #define DREG_REGID_TRAP_20 0x0000011C
1249 #define DREG_REGID_TRAP_21 0x0000011D
1250 #define DREG_REGID_TRAP_22 0x0000011E
1251 #define DREG_REGID_TRAP_23 0x0000011F
1252 #endif
1253 #endif
1254 #define DREG_REGID_RSA0_LOW 0x00000200
1255 #define DREG_REGID_RSA0_HIGH 0x00000201
1256 #define DREG_REGID_RSA1_LOW 0x00000202
1257 #define DREG_REGID_RSA1_HIGH 0x00000203
1258 #define DREG_REGID_RSA2 0x00000204
1259 #define DREG_REGID_RSA3 0x00000205
1260 #define DREG_REGID_RSI0_LOW 0x00000206
1261 #define DREG_REGID_RSI0_HIGH 0x00000207
1262 #define DREG_REGID_RSI1 0x00000208
1263 #define DREG_REGID_RSI2 0x00000209
1264 #define DREG_REGID_SAGUSTATUS 0x0000020A
1265 #define DREG_REGID_RSCONFIG01_LOW 0x0000020B
1266 #define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
1267 #define DREG_REGID_RSCONFIG23_LOW 0x0000020D
1268 #define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
1269 #define DREG_REGID_RSDMA01E 0x0000020F
1270 #define DREG_REGID_RSDMA23E 0x00000210
1271 #define DREG_REGID_RSD0_LOW 0x00000211
1272 #define DREG_REGID_RSD0_HIGH 0x00000212
1273 #define DREG_REGID_RSD1_LOW 0x00000213
1274 #define DREG_REGID_RSD1_HIGH 0x00000214
1275 #define DREG_REGID_RSD2_LOW 0x00000215
1276 #define DREG_REGID_RSD2_HIGH 0x00000216
1277 #define DREG_REGID_RSD3_LOW 0x00000217
1278 #define DREG_REGID_RSD3_HIGH 0x00000218
1279 #define DREG_REGID_SRAR_HIGH 0x0000021A
1280 #define DREG_REGID_SRAR_LOW 0x0000021B
1281 #define DREG_REGID_DMA_STATE 0x0000021C
1282 #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
1283 #define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
1284 #define DREG_REGID_CPU_STATUS 0x00000300
1285 #define DREG_REGID_MAC_MODE 0x00000301
1286 #define DREG_REGID_STACK_AND_REPEAT 0x00000302
1287 #define DREG_REGID_INDEX0 0x00000304
1288 #define DREG_REGID_INDEX1 0x00000305
1289 #define DREG_REGID_DMA_STATE_0_3 0x00000400
1290 #define DREG_REGID_DMA_STATE_4_7 0x00000404
1291 #define DREG_REGID_DMA_STATE_8_11 0x00000408
1292 #define DREG_REGID_DMA_STATE_12_15 0x0000040C
1293 #define DREG_REGID_DMA_STATE_16_19 0x00000410
1294 #define DREG_REGID_DMA_STATE_20_23 0x00000414
1295 #define DREG_REGID_DMA_STATE_24_27 0x00000418
1296 #define DREG_REGID_DMA_STATE_28_31 0x0000041C
1297 #define DREG_REGID_DMA_STATE_32_35 0x00000420
1298 #define DREG_REGID_DMA_STATE_36_39 0x00000424
1299 #define DREG_REGID_DMA_STATE_40_43 0x00000428
1300 #define DREG_REGID_DMA_STATE_44_47 0x0000042C
1301 #define DREG_REGID_DMA_STATE_48_51 0x00000430
1302 #define DREG_REGID_DMA_STATE_52_55 0x00000434
1303 #define DREG_REGID_DMA_STATE_56_59 0x00000438
1304 #define DREG_REGID_DMA_STATE_60_63 0x0000043C
1305 #define DREG_REGID_DMA_STATE_64_67 0x00000440
1306 #define DREG_REGID_DMA_STATE_68_71 0x00000444
1307 #define DREG_REGID_DMA_STATE_72_75 0x00000448
1308 #define DREG_REGID_DMA_STATE_76_79 0x0000044C
1309 #define DREG_REGID_DMA_STATE_80_83 0x00000450
1310 #define DREG_REGID_DMA_STATE_84_87 0x00000454
1311 #define DREG_REGID_DMA_STATE_88_91 0x00000458
1312 #define DREG_REGID_DMA_STATE_92_95 0x0000045C
1313 #define DREG_REGID_TRAP_SELECT 0x00000500
1314 #define DREG_REGID_TRAP_WRITE_0 0x00000500
1315 #define DREG_REGID_TRAP_WRITE_1 0x00000501
1316 #define DREG_REGID_TRAP_WRITE_2 0x00000502
1317 #define DREG_REGID_TRAP_WRITE_3 0x00000503
1318 #define DREG_REGID_TRAP_WRITE_4 0x00000504
1319 #define DREG_REGID_TRAP_WRITE_5 0x00000505
1320 #define DREG_REGID_TRAP_WRITE_6 0x00000506
1321 #define DREG_REGID_TRAP_WRITE_7 0x00000507
1322 #if !defined(NO_CS4612)
1323 #if !defined(NO_CS4615)
1324 #define DREG_REGID_TRAP_WRITE_8 0x00000510
1325 #define DREG_REGID_TRAP_WRITE_9 0x00000511
1326 #define DREG_REGID_TRAP_WRITE_10 0x00000512
1327 #define DREG_REGID_TRAP_WRITE_11 0x00000513
1328 #define DREG_REGID_TRAP_WRITE_12 0x00000514
1329 #define DREG_REGID_TRAP_WRITE_13 0x00000515
1330 #define DREG_REGID_TRAP_WRITE_14 0x00000516
1331 #define DREG_REGID_TRAP_WRITE_15 0x00000517
1332 #define DREG_REGID_TRAP_WRITE_16 0x00000518
1333 #define DREG_REGID_TRAP_WRITE_17 0x00000519
1334 #define DREG_REGID_TRAP_WRITE_18 0x0000051A
1335 #define DREG_REGID_TRAP_WRITE_19 0x0000051B
1336 #define DREG_REGID_TRAP_WRITE_20 0x0000051C
1337 #define DREG_REGID_TRAP_WRITE_21 0x0000051D
1338 #define DREG_REGID_TRAP_WRITE_22 0x0000051E
1339 #define DREG_REGID_TRAP_WRITE_23 0x0000051F
1340 #endif
1341 #endif
1342 #define DREG_REGID_MAC0_ACC0_LOW 0x00000600
1343 #define DREG_REGID_MAC0_ACC1_LOW 0x00000601
1344 #define DREG_REGID_MAC0_ACC2_LOW 0x00000602
1345 #define DREG_REGID_MAC0_ACC3_LOW 0x00000603
1346 #define DREG_REGID_MAC1_ACC0_LOW 0x00000604
1347 #define DREG_REGID_MAC1_ACC1_LOW 0x00000605
1348 #define DREG_REGID_MAC1_ACC2_LOW 0x00000606
1349 #define DREG_REGID_MAC1_ACC3_LOW 0x00000607
1350 #define DREG_REGID_MAC0_ACC0_MID 0x00000608
1351 #define DREG_REGID_MAC0_ACC1_MID 0x00000609
1352 #define DREG_REGID_MAC0_ACC2_MID 0x0000060A
1353 #define DREG_REGID_MAC0_ACC3_MID 0x0000060B
1354 #define DREG_REGID_MAC1_ACC0_MID 0x0000060C
1355 #define DREG_REGID_MAC1_ACC1_MID 0x0000060D
1356 #define DREG_REGID_MAC1_ACC2_MID 0x0000060E
1357 #define DREG_REGID_MAC1_ACC3_MID 0x0000060F
1358 #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
1359 #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
1360 #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
1361 #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
1362 #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
1363 #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
1364 #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
1365 #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
1366 #define DREG_REGID_RSHOUT_LOW 0x00000620
1367 #define DREG_REGID_RSHOUT_MID 0x00000628
1368 #define DREG_REGID_RSHOUT_HIGH 0x00000630
1369
1370 /*
1371 * The following defines are for the flags in the DMA stream requestor write
1372 */
1373 #define DSRWP_DSR_MASK 0x0000000F
1374 #define DSRWP_DSR_BG_RQ 0x00000001
1375 #define DSRWP_DSR_PRIORITY_MASK 0x00000006
1376 #define DSRWP_DSR_PRIORITY_0 0x00000000
1377 #define DSRWP_DSR_PRIORITY_1 0x00000002
1378 #define DSRWP_DSR_PRIORITY_2 0x00000004
1379 #define DSRWP_DSR_PRIORITY_3 0x00000006
1380 #define DSRWP_DSR_RQ_PENDING 0x00000008
1381
1382 /*
1383 * The following defines are for the flags in the trap write port register.
1384 */
1385 #define TWPR_TW_MASK 0x0000FFFF
1386 #define TWPR_TW_SHIFT 0
1387
1388 /*
1389 * The following defines are for the flags in the stack pointer write
1390 * register.
1391 */
1392 #define SPWR_STKP_MASK 0x0000000F
1393 #define SPWR_STKP_SHIFT 0
1394
1395 /*
1396 * The following defines are for the flags in the SP interrupt register.
1397 */
1398 #define SPIR_FRI 0x00000001
1399 #define SPIR_DOI 0x00000002
1400 #define SPIR_GPI2 0x00000004
1401 #define SPIR_GPI3 0x00000008
1402 #define SPIR_IP0 0x00000010
1403 #define SPIR_IP1 0x00000020
1404 #define SPIR_IP2 0x00000040
1405 #define SPIR_IP3 0x00000080
1406
1407 /*
1408 * The following defines are for the flags in the functional group 1 register.
1409 */
1410 #define FGR1_F1S_MASK 0x0000FFFF
1411 #define FGR1_F1S_SHIFT 0
1412
1413 /*
1414 * The following defines are for the flags in the SP clock status register.
1415 */
1416 #define SPCS_FRI 0x00000001
1417 #define SPCS_DOI 0x00000002
1418 #define SPCS_GPI2 0x00000004
1419 #define SPCS_GPI3 0x00000008
1420 #define SPCS_IP0 0x00000010
1421 #define SPCS_IP1 0x00000020
1422 #define SPCS_IP2 0x00000040
1423 #define SPCS_IP3 0x00000080
1424 #define SPCS_SPRUN 0x00000100
1425 #define SPCS_SLEEP 0x00000200
1426 #define SPCS_FG 0x00000400
1427 #define SPCS_ORUN 0x00000800
1428 #define SPCS_IRQ 0x00001000
1429 #define SPCS_FGN_MASK 0x0000E000
1430 #define SPCS_FGN_SHIFT 13
1431
1432 /*
1433 * The following defines are for the flags in the SP DMA requestor status
1434 * register.
1435 */
1436 #define SDSR_DCS_MASK 0x000000FF
1437 #define SDSR_DCS_SHIFT 0
1438 #define SDSR_DCS_NONE 0x00000007
1439
1440 /*
1441 * The following defines are for the flags in the frame timer register.
1442 */
1443 #define FRMT_FTV_MASK 0x0000FFFF
1444 #define FRMT_FTV_SHIFT 0
1445
1446 /*
1447 * The following defines are for the flags in the frame timer current count
1448 * register.
1449 */
1450 #define FRCC_FCC_MASK 0x0000FFFF
1451 #define FRCC_FCC_SHIFT 0
1452
1453 /*
1454 * The following defines are for the flags in the frame timer save count
1455 * register.
1456 */
1457 #define FRSC_FCS_MASK 0x0000FFFF
1458 #define FRSC_FCS_SHIFT 0
1459
1460 /*
1461 * The following define the various flags stored in the scatter/gather
1462 * descriptors.
1463 */
1464 #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
1465 #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
1466 #define DMA_SG_SAMPLE_END_FLAG 0x10000000
1467 #define DMA_SG_LOOP_END_FLAG 0x20000000
1468 #define DMA_SG_SIGNAL_END_FLAG 0x40000000
1469 #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
1470 #define DMA_SG_NEXT_ENTRY_SHIFT 3
1471 #define DMA_SG_SAMPLE_END_SHIFT 16
1472
1473 /*
1474 * The following define the offsets of the fields within the on-chip generic
1475 * DMA requestor.
1476 */
1477 #define DMA_RQ_CONTROL1 0x00000000
1478 #define DMA_RQ_CONTROL2 0x00000004
1479 #define DMA_RQ_SOURCE_ADDR 0x00000008
1480 #define DMA_RQ_DESTINATION_ADDR 0x0000000C
1481 #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
1482 #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
1483 #define DMA_RQ_LOOP_START_ADDR 0x00000018
1484 #define DMA_RQ_POST_LOOP_ADDR 0x0000001C
1485 #define DMA_RQ_PAGE_MAP_ADDR 0x00000020
1486
1487 /*
1488 * The following defines are for the flags in the first control word of the
1489 * on-chip generic DMA requestor.
1490 */
1491 #define DMA_RQ_C1_COUNT_MASK 0x000003FF
1492 #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
1493 #define DMA_RQ_C1_SOURCE_GATHER 0x00002000
1494 #define DMA_RQ_C1_DONE_FLAG 0x00004000
1495 #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
1496 #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
1497 #define DMA_RQ_C1_FULL_PAGE 0x00000000
1498 #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
1499 #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
1500 #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
1501 #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
1502 #define DMA_RQ_C1_NOT_LOOP_END 0x00000000
1503 #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
1504 #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
1505 #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
1506 #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
1507 #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
1508 #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
1509 #define DMA_RQ_C1_PM_RESERVED 0x00200000
1510 #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
1511 #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
1512 #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
1513 #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
1514 #define DMA_RQ_C1_DEST_LINEAR 0x00000000
1515 #define DMA_RQ_C1_DEST_MOD16 0x01000000
1516 #define DMA_RQ_C1_DEST_MOD32 0x02000000
1517 #define DMA_RQ_C1_DEST_MOD64 0x03000000
1518 #define DMA_RQ_C1_DEST_MOD128 0x04000000
1519 #define DMA_RQ_C1_DEST_MOD256 0x05000000
1520 #define DMA_RQ_C1_DEST_MOD512 0x06000000
1521 #define DMA_RQ_C1_DEST_MOD1024 0x07000000
1522 #define DMA_RQ_C1_DEST_ON_HOST 0x08000000
1523 #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
1524 #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
1525 #define DMA_RQ_C1_SOURCE_MOD16 0x10000000
1526 #define DMA_RQ_C1_SOURCE_MOD32 0x20000000
1527 #define DMA_RQ_C1_SOURCE_MOD64 0x30000000
1528 #define DMA_RQ_C1_SOURCE_MOD128 0x40000000
1529 #define DMA_RQ_C1_SOURCE_MOD256 0x50000000
1530 #define DMA_RQ_C1_SOURCE_MOD512 0x60000000
1531 #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
1532 #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
1533 #define DMA_RQ_C1_COUNT_SHIFT 0
1534
1535 /*
1536 * The following defines are for the flags in the second control word of the
1537 * on-chip generic DMA requestor.
1538 */
1539 #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
1540 #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
1541 #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
1542 #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
1543 #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
1544 #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
1545 #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
1546 #define DMA_RQ_C2_AC_NONE 0x00000000
1547 #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
1548 #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
1549 #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
1550 #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
1551 #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
1552 #define DMA_RQ_C2_LOOP_MASK 0x30000000
1553 #define DMA_RQ_C2_NO_LOOP 0x00000000
1554 #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
1555 #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
1556 #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
1557 #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
1558 #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
1559 #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
1560 #define DMA_RQ_C2_LOOP_END_SHIFT 16
1561
1562 /*
1563 * The following defines are for the flags in the source and destination words
1564 * of the on-chip generic DMA requestor.
1565 */
1566 #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
1567 #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
1568 #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
1569 #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
1570 #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
1571 #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
1572 #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
1573 #define DMA_RQ_SD_END_FLAG 0x40000000
1574 #define DMA_RQ_SD_ERROR_FLAG 0x80000000
1575 #define DMA_RQ_SD_ADDRESS_SHIFT 0
1576
1577 /*
1578 * The following defines are for the flags in the page map address word of the
1579 * on-chip generic DMA requestor.
1580 */
1581 #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
1582 #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
1583 #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
1584 #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
1585
1586 #define BA1_VARIDEC_BUF_1 0x000
1587
1588 #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
1589 #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
1590 #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
1591 #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
1592 #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
1593 #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
1594 #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
1595
1596 #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
1597 #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
1598 #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
1599 #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
1600 #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
1601 #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
1602 #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
1603 #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
1604
1605 #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
1606 #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
1607 #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
1608 #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
1609
1610 /*
1611 *
1612 */
1613
1614 #define CS461X_MODE_OUTPUT (1<<0) /* MIDI UART - output */
1615 #define CS461X_MODE_INPUT (1<<1) /* MIDI UART - input */
1616
1617 #endif /* __CS461X_H */
1618
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