1 #ifndef __TRID4DWAVE_H
2 #define __TRID4DWAVE_H
3
4 /*
5 * audio@tridentmicro.com
6 * Fri Feb 19 15:55:28 MST 1999
7 * Definitions for Trident 4DWave DX/NX chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26 /* PCI vendor and device ID */
27 #ifndef PCI_VENDOR_ID_TRIDENT
28 #define PCI_VENDOR_ID_TRIDENT 0x1023
29 #endif
30
31 #ifndef PCI_VENDOR_ID_SI
32 #define PCI_VENDOR_ID_SI 0x0139
33 #endif
34
35 #ifndef PCI_VENDOR_ID_ALI
36 #define PCI_VENDOR_ID_ALI 0x10b9
37 #endif
38
39 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
40 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
41 #endif
42
43 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
44 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
45 #endif
46
47 #ifndef PCI_DEVICE_ID_SI_7018
48 #define PCI_DEVICE_ID_SI_7018 0x7018
49 #endif
50
51 #ifndef PCI_DEVICE_ID_ALI_5451
52 #define PCI_DEVICE_ID_ALI_5451 0x5451
53 #endif
54
55 #ifndef PCI_DEVICE_ID_ALI_1533
56 #define PCI_DEVICE_ID_ALI_1533 0x1533
57 #endif
58
59 #ifndef FALSE
60 #define FALSE 0
61 #define TRUE 1
62 #endif
63
64 #define CHANNEL_REGS 5
65 #define CHANNEL_START 0xe0 // The first bytes of the contiguous register space.
66
67 #define BANK_A 0
68 #define BANK_B 1
69 #define NR_BANKS 2
70
71 #define TRIDENT_FMT_STEREO 0x01
72 #define TRIDENT_FMT_16BIT 0x02
73 #define TRIDENT_FMT_MASK 0x03
74
75 #define DAC_RUNNING 0x01
76 #define ADC_RUNNING 0x02
77
78 /* Register Addresses */
79
80 /* operational registers common to DX, NX, 7018 */
81 enum trident_op_registers {
82 T4D_REC_CH = 0x70,
83 T4D_START_A = 0x80, T4D_STOP_A = 0x84,
84 T4D_DLY_A = 0x88, T4D_SIGN_CSO_A = 0x8c,
85 T4D_CSPF_A = 0x90, T4D_CEBC_A = 0x94,
86 T4D_AINT_A = 0x98, T4D_EINT_A = 0x9c,
87 T4D_LFO_GC_CIR = 0xa0, T4D_AINTEN_A = 0xa4,
88 T4D_MUSICVOL_WAVEVOL = 0xa8, T4D_SBDELTA_DELTA_R = 0xac,
89 T4D_MISCINT = 0xb0, T4D_START_B = 0xb4,
90 T4D_STOP_B = 0xb8, T4D_CSPF_B = 0xbc,
91 T4D_SBBL_SBCL = 0xc0, T4D_SBCTRL_SBE2R_SBDD = 0xc4,
92 T4D_STIMER = 0xc8, T4D_LFO_B_I2S_DELTA = 0xcc,
93 T4D_AINT_B = 0xd8, T4D_AINTEN_B = 0xdc
94 };
95
96 enum ali_op_registers {
97 ALI_SCTRL = 0x48,
98 ALI_GLOBAL_CONTROL = 0xd4,
99 ALI_STIMER = 0xc8,
100 ALI_SPDIF_CS = 0x70,
101 ALI_SPDIF_CTRL = 0x74
102 };
103
104 enum ali_registers_number {
105 ALI_GLOBAL_REGS = 56,
106 ALI_CHANNEL_REGS = 8,
107 ALI_MIXER_REGS = 20
108 };
109
110 enum ali_sctrl_control_bit {
111 ALI_SPDIF_OUT_ENABLE = 0x20
112 };
113
114 enum ali_global_control_bit {
115 ALI_SPDIF_OUT_SEL_PCM = 0x00000400,
116 ALI_SPDIF_IN_SUPPORT = 0x00000800,
117 ALI_SPDIF_OUT_CH_ENABLE = 0x00008000,
118 ALI_SPDIF_IN_CH_ENABLE = 0x00080000,
119 ALI_PCM_IN_DISABLE = 0x7fffffff,
120 ALI_PCM_IN_ENABLE = 0x80000000,
121 ALI_SPDIF_IN_CH_DISABLE = 0xfff7ffff,
122 ALI_SPDIF_OUT_CH_DISABLE = 0xffff7fff,
123 ALI_SPDIF_OUT_SEL_SPDIF = 0xfffffbff
124
125 };
126
127 enum ali_spdif_control_bit {
128 ALI_SPDIF_IN_FUNC_ENABLE = 0x02,
129 ALI_SPDIF_IN_CH_STATUS = 0x40,
130 ALI_SPDIF_OUT_CH_STATUS = 0xbf
131
132 };
133
134 enum ali_control_all {
135 ALI_DISABLE_ALL_IRQ = 0,
136 ALI_CHANNELS = 32,
137 ALI_STOP_ALL_CHANNELS = 0xffffffff,
138 ALI_MULTI_CHANNELS_START_STOP = 0x07800000
139
140 };
141
142 enum ali_pcm_in_channel_num {
143 ALI_NORMAL_CHANNEL = 0,
144 ALI_SPDIF_OUT_CHANNEL = 15,
145 ALI_SPDIF_IN_CHANNEL = 19,
146 ALI_LEF_CHANNEL = 23,
147 ALI_CENTER_CHANNEL = 24,
148 ALI_SURR_RIGHT_CHANNEL = 25,
149 ALI_SURR_LEFT_CHANNEL = 26,
150 ALI_PCM_IN_CHANNEL = 31
151 };
152
153 enum ali_pcm_out_channel_num {
154 ALI_PCM_OUT_CHANNEL_FIRST = 0,
155 ALI_PCM_OUT_CHANNEL_LAST = 31
156 };
157
158 enum ali_ac97_power_control_bit {
159 ALI_EAPD_POWER_DOWN = 0x8000
160 };
161
162 enum ali_update_ptr_flags {
163 ALI_ADDRESS_INT_UPDATE = 0x01
164 };
165
166 enum ali_revision {
167 ALI_5451_V02 = 0x02
168 };
169
170 enum ali_spdif_out_control {
171 ALI_PCM_TO_SPDIF_OUT = 0,
172 ALI_SPDIF_OUT_TO_SPDIF_OUT = 1,
173 ALI_SPDIF_OUT_PCM = 0,
174 ALI_SPDIF_OUT_NON_PCM = 2
175 };
176
177 /* S/PDIF Operational Registers for 4D-NX */
178 enum nx_spdif_registers {
179 NX_SPCTRL_SPCSO = 0x24, NX_SPLBA = 0x28,
180 NX_SPESO = 0x2c, NX_SPCSTATUS = 0x64
181 };
182
183 /* OP registers to access each hardware channel */
184 enum channel_registers {
185 CH_DX_CSO_ALPHA_FMS = 0xe0, CH_DX_ESO_DELTA = 0xe8,
186 CH_DX_FMC_RVOL_CVOL = 0xec,
187 CH_NX_DELTA_CSO = 0xe0, CH_NX_DELTA_ESO = 0xe8,
188 CH_NX_ALPHA_FMS_FMC_RVOL_CVOL = 0xec,
189 CH_LBA = 0xe4,
190 CH_GVSEL_PAN_VOL_CTRL_EC = 0xf0
191 };
192
193 /* registers to read/write/control AC97 codec */
194 enum dx_ac97_registers {
195 DX_ACR0_AC97_W = 0x40, DX_ACR1_AC97_R = 0x44,
196 DX_ACR2_AC97_COM_STAT = 0x48
197 };
198
199 enum nx_ac97_registers {
200 NX_ACR0_AC97_COM_STAT = 0x40, NX_ACR1_AC97_W = 0x44,
201 NX_ACR2_AC97_R_PRIMARY = 0x48, NX_ACR3_AC97_R_SECONDARY = 0x4c
202 };
203
204 enum si_ac97_registers {
205 SI_AC97_WRITE = 0x40, SI_AC97_READ = 0x44,
206 SI_SERIAL_INTF_CTRL = 0x48, SI_AC97_GPIO = 0x4c
207 };
208
209 enum ali_ac97_registers {
210 ALI_AC97_WRITE = 0x40, ALI_AC97_READ = 0x44
211 };
212
213 /* Bit mask for operational registers */
214 #define AC97_REG_ADDR 0x000000ff
215
216 enum ali_ac97_bits {
217 ALI_AC97_BUSY_WRITE = 0x8000, ALI_AC97_BUSY_READ = 0x8000,
218 ALI_AC97_WRITE_ACTION = 0x8000, ALI_AC97_READ_ACTION = 0x8000,
219 ALI_AC97_AUDIO_BUSY = 0x4000, ALI_AC97_SECONDARY = 0x0080,
220 ALI_AC97_READ_MIXER_REGISTER = 0xfeff,
221 ALI_AC97_WRITE_MIXER_REGISTER = 0x0100
222 };
223
224 enum sis7018_ac97_bits {
225 SI_AC97_BUSY_WRITE = 0x8000, SI_AC97_BUSY_READ = 0x8000,
226 SI_AC97_AUDIO_BUSY = 0x4000, SI_AC97_MODEM_BUSY = 0x2000,
227 SI_AC97_SECONDARY = 0x0080
228 };
229
230 enum trident_dx_ac97_bits {
231 DX_AC97_BUSY_WRITE = 0x8000, DX_AC97_BUSY_READ = 0x8000,
232 DX_AC97_READY = 0x0010, DX_AC97_RECORD = 0x0008,
233 DX_AC97_PLAYBACK = 0x0002
234 };
235
236 enum trident_nx_ac97_bits {
237 /* ACR1-3 */
238 NX_AC97_BUSY_WRITE = 0x0800, NX_AC97_BUSY_READ = 0x0800,
239 NX_AC97_BUSY_DATA = 0x0400, NX_AC97_WRITE_SECONDARY = 0x0100,
240 /* ACR0 */
241 NX_AC97_SECONDARY_READY = 0x0040, NX_AC97_SECONDARY_RECORD = 0x0020,
242 NX_AC97_SURROUND_OUTPUT = 0x0010,
243 NX_AC97_PRIMARY_READY = 0x0008, NX_AC97_PRIMARY_RECORD = 0x0004,
244 NX_AC97_PCM_OUTPUT = 0x0002,
245 NX_AC97_WARM_RESET = 0x0001
246 };
247
248 enum serial_intf_ctrl_bits {
249 WARM_REST = 0x00000001, COLD_RESET = 0x00000002,
250 I2S_CLOCK = 0x00000004, PCM_SEC_AC97= 0x00000008,
251 AC97_DBL_RATE = 0x00000010, SPDIF_EN = 0x00000020,
252 I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
253 PCMIN = 0x00000100, LINE1IN = 0x00000200,
254 MICIN = 0x00000400, LINE2IN = 0x00000800,
255 HEAD_SET_IN = 0x00001000, GPIOIN = 0x00002000,
256 /* 7018 spec says id = 01 but the demo board routed to 10
257 SECONDARY_ID= 0x00004000, */
258 SECONDARY_ID= 0x00004000,
259 PCMOUT = 0x00010000, SURROUT = 0x00020000,
260 CENTEROUT = 0x00040000, LFEOUT = 0x00080000,
261 LINE1OUT = 0x00100000, LINE2OUT = 0x00200000,
262 GPIOOUT = 0x00400000,
263 SI_AC97_PRIMARY_READY = 0x01000000,
264 SI_AC97_SECONDARY_READY = 0x02000000,
265 };
266
267 enum global_control_bits {
268 CHANNLE_IDX = 0x0000003f, PB_RESET = 0x00000100,
269 PAUSE_ENG = 0x00000200,
270 OVERRUN_IE = 0x00000400, UNDERRUN_IE = 0x00000800,
271 ENDLP_IE = 0x00001000, MIDLP_IE = 0x00002000,
272 ETOG_IE = 0x00004000,
273 EDROP_IE = 0x00008000, BANK_B_EN = 0x00010000
274 };
275
276 enum channel_control_bits {
277 CHANNEL_LOOP = 0x00001000, CHANNEL_SIGNED = 0x00002000,
278 CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
279 };
280
281 enum channel_attribute {
282 /* playback/record select */
283 CHANNEL_PB = 0x0000, CHANNEL_SPC_PB = 0x4000,
284 CHANNEL_REC = 0x8000, CHANNEL_REC_PB = 0xc000,
285 /* playback destination/record source select */
286 MODEM_LINE1 = 0x0000, MODEM_LINE2 = 0x0400,
287 PCM_LR = 0x0800, HSET = 0x0c00,
288 I2S_LR = 0x1000, CENTER_LFE = 0x1400,
289 SURR_LR = 0x1800, SPDIF_LR = 0x1c00,
290 MIC = 0x1400,
291 /* mist stuff */
292 MONO_LEFT = 0x0000, MONO_RIGHT = 0x0100,
293 MONO_MIX = 0x0200, SRC_ENABLE = 0x0080,
294 };
295
296 enum miscint_bits {
297 PB_UNDERRUN_IRO = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
298 SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
299 OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
300 ENVELOPE_IRQ = 0x00000040, ST_IRQ = 0x00000080,
301 PB_UNDERRUN = 0x00000100, REC_OVERRUN = 0x00000200,
302 MIXER_UNDERFLOW = 0x00000400, MIXER_OVERFLOW = 0x00000800,
303 ST_TARGET_REACHED = 0x00008000, PB_24K_MODE = 0x00010000,
304 ST_IRQ_EN = 0x00800000, ACGPIO_IRQ = 0x01000000
305 };
306
307 #define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
308
309 #define VALIDATE_MAGIC(FOO,MAG) \
310 ({ \
311 if (!(FOO) || (FOO)->magic != MAG) { \
312 printk(invalid_magic,__FUNCTION__); \
313 return -ENXIO; \
314 } \
315 })
316
317 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,TRIDENT_STATE_MAGIC)
318 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,TRIDENT_CARD_MAGIC)
319
320 extern __inline__ unsigned ld2(unsigned int x)
321 {
322 unsigned r = 0;
323
324 if (x >= 0x10000) {
325 x >>= 16;
326 r += 16;
327 }
328 if (x >= 0x100) {
329 x >>= 8;
330 r += 8;
331 }
332 if (x >= 0x10) {
333 x >>= 4;
334 r += 4;
335 }
336 if (x >= 4) {
337 x >>= 2;
338 r += 2;
339 }
340 if (x >= 2)
341 r++;
342 return r;
343 }
344
345 #endif /* __TRID4DWAVE_H */
346
347
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