1 #ifndef __LINUX_UHCI_H
2 #define __LINUX_UHCI_H
3
4 #include <linux/list.h>
5 #include <linux/usb.h>
6
7 /*
8 * This nested spinlock code is courtesy of Davide Libenzi <dlibenzi@maticad.it>
9 */
10 struct s_nested_lock {
11 spinlock_t lock;
12 void *uniq;
13 short int count;
14 };
15
16 #define nested_init(snl) \
17 spin_lock_init(&(snl)->lock); \
18 (snl)->uniq = NULL; \
19 (snl)->count = 0;
20
21 #define nested_lock(snl, flags) \
22 if ((snl)->uniq == current) { \
23 (snl)->count++; \
24 flags = 0; /* No warnings */ \
25 } else { \
26 spin_lock_irqsave(&(snl)->lock, flags); \
27 (snl)->count++; \
28 (snl)->uniq = current; \
29 }
30
31 #define nested_unlock(snl, flags) \
32 if (!--(snl)->count) { \
33 (snl)->uniq = NULL; \
34 spin_unlock_irqrestore(&(snl)->lock, flags); \
35 }
36
37 /*
38 * Universal Host Controller Interface data structures and defines
39 */
40
41 /* Command register */
42 #define USBCMD 0
43 #define USBCMD_RS 0x0001 /* Run/Stop */
44 #define USBCMD_HCRESET 0x0002 /* Host reset */
45 #define USBCMD_GRESET 0x0004 /* Global reset */
46 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
47 #define USBCMD_FGR 0x0010 /* Force Global Resume */
48 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
49 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
50 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
51
52 /* Status register */
53 #define USBSTS 2
54 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
55 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
56 #define USBSTS_RD 0x0004 /* Resume Detect */
57 #define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
58 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
59 #define USBSTS_HCH 0x0020 /* HC Halted */
60
61 /* Interrupt enable register */
62 #define USBINTR 4
63 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
64 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
65 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
66 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
67
68 #define USBFRNUM 6
69 #define USBFLBASEADD 8
70 #define USBSOF 12
71
72 /* USB port status and control registers */
73 #define USBPORTSC1 16
74 #define USBPORTSC2 18
75 #define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
76 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
77 #define USBPORTSC_PE 0x0004 /* Port Enable */
78 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
79 #define USBPORTSC_LS 0x0030 /* Line Status */
80 #define USBPORTSC_RD 0x0040 /* Resume Detect */
81 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
82 #define USBPORTSC_PR 0x0200 /* Port Reset */
83 #define USBPORTSC_SUSP 0x1000 /* Suspend */
84
85 /* Legacy support register */
86 #define USBLEGSUP 0xc0
87 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
88
89 #define UHCI_NULL_DATA_SIZE 0x7FF /* for UHCI controller TD */
90
91 #define UHCI_PTR_BITS 0x000F
92 #define UHCI_PTR_TERM 0x0001
93 #define UHCI_PTR_QH 0x0002
94 #define UHCI_PTR_DEPTH 0x0004
95
96 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
97 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
98 #define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */
99
100 struct uhci_framelist {
101 __u32 frame[UHCI_NUMFRAMES];
102 } __attribute__((aligned(4096)));
103
104 struct uhci_td;
105
106 struct uhci_qh {
107 /* Hardware fields */
108 __u32 link; /* Next queue */
109 __u32 element; /* Queue element pointer */
110
111 /* Software fields */
112 /* Can't use list_head since we want a specific order */
113 struct usb_device *dev; /* The owning device */
114
115 struct uhci_qh *prevqh, *nextqh;
116
117 struct list_head remove_list;
118 } __attribute__((aligned(16)));
119
120 /*
121 * for TD <status>:
122 */
123 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
124 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
125 #define TD_CTRL_C_ERR_SHIFT 27
126 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
127 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
128 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
129 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
130 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
131 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
132 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
133 #define TD_CTRL_NAK (1 << 19) /* NAK Received */
134 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
135 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
136 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
137
138 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
139 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
140
141 #define uhci_status_bits(ctrl_sts) (ctrl_sts & 0xFE0000)
142 #define uhci_actual_length(ctrl_sts) ((ctrl_sts + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
143
144 #define uhci_ptr_to_virt(x) bus_to_virt(x & ~UHCI_PTR_BITS)
145
146 /*
147 * for TD <info>: (a.k.a. Token)
148 */
149 #define TD_TOKEN_TOGGLE 19
150 #define TD_PID 0xFF
151
152 #define uhci_maxlen(token) ((token) >> 21)
153 #define uhci_expected_length(info) (((info >> 21) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
154 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE) & 1)
155 #define uhci_endpoint(token) (((token) >> 15) & 0xf)
156 #define uhci_devaddr(token) (((token) >> 8) & 0x7f)
157 #define uhci_devep(token) (((token) >> 8) & 0x7ff)
158 #define uhci_packetid(token) ((token) & 0xff)
159 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
160 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
161
162 /*
163 * The documentation says "4 words for hardware, 4 words for software".
164 *
165 * That's silly, the hardware doesn't care. The hardware only cares that
166 * the hardware words are 16-byte aligned, and we can have any amount of
167 * sw space after the TD entry as far as I can tell.
168 *
169 * But let's just go with the documentation, at least for 32-bit machines.
170 * On 64-bit machines we probably want to take advantage of the fact that
171 * hw doesn't really care about the size of the sw-only area.
172 *
173 * Alas, not anymore, we have more than 4 words for software, woops
174 */
175 struct uhci_td {
176 /* Hardware fields */
177 __u32 link;
178 __u32 status;
179 __u32 info;
180 __u32 buffer;
181
182 /* Software fields */
183 unsigned int *frameptr; /* Frame list pointer */
184 struct uhci_td *prevtd, *nexttd; /* Previous and next TD in queue */
185
186 struct usb_device *dev;
187 struct urb *urb; /* URB this TD belongs to */
188
189 struct list_head list;
190 } __attribute__((aligned(16)));
191
192 /*
193 * There are various standard queues. We set up several different
194 * queues for each of the three basic queue types: interrupt,
195 * control, and bulk.
196 *
197 * - There are various different interrupt latencies: ranging from
198 * every other USB frame (2 ms apart) to every 256 USB frames (ie
199 * 256 ms apart). Make your choice according to how obnoxious you
200 * want to be on the wire, vs how critical latency is for you.
201 * - The control list is done every frame.
202 * - There are 4 bulk lists, so that up to four devices can have a
203 * bulk list of their own and when run concurrently all four lists
204 * will be be serviced.
205 *
206 * This is a bit misleading, there are various interrupt latencies, but they
207 * vary a bit, interrupt2 isn't exactly 2ms, it can vary up to 4ms since the
208 * other queues can "override" it. interrupt4 can vary up to 8ms, etc. Minor
209 * problem
210 *
211 * In the case of the root hub, these QH's are just head's of qh's. Don't
212 * be scared, it kinda makes sense. Look at this wonderful picture care of
213 * Linus:
214 *
215 * generic- -> dev1- -> generic- -> dev1- -> control- -> bulk- -> ...
216 * iso-QH iso-QH irq-QH irq-QH QH QH
217 * | | | | | |
218 * End dev1-iso-TD1 End dev1-irq-TD1 ... ...
219 * |
220 * dev1-iso-TD2
221 * |
222 * ....
223 *
224 * This may vary a bit (the UHCI docs don't explicitly say you can put iso
225 * transfers in QH's and all of their pictures don't have that either) but
226 * other than that, that is what we're doing now
227 *
228 * And now we don't put Iso transfers in QH's, so we don't waste one on it
229 * --jerdfelt
230 *
231 * To keep with Linus' nomenclature, this is called the QH skeleton. These
232 * labels (below) are only signficant to the root hub's QH's
233 */
234
235 #define UHCI_NUM_SKELTD 10
236 #define skel_int1_td skeltd[0]
237 #define skel_int2_td skeltd[1]
238 #define skel_int4_td skeltd[2]
239 #define skel_int8_td skeltd[3]
240 #define skel_int16_td skeltd[4]
241 #define skel_int32_td skeltd[5]
242 #define skel_int64_td skeltd[6]
243 #define skel_int128_td skeltd[7]
244 #define skel_int256_td skeltd[8]
245 #define skel_term_td skeltd[9] /* To work around PIIX UHCI bug */
246
247 #define UHCI_NUM_SKELQH 4
248 #define skel_ls_control_qh skelqh[0]
249 #define skel_hs_control_qh skelqh[1]
250 #define skel_bulk_qh skelqh[2]
251 #define skel_term_qh skelqh[3]
252
253 /*
254 * Search tree for determining where <interval> fits in the
255 * skelqh[] skeleton.
256 *
257 * An interrupt request should be placed into the slowest skelqh[]
258 * which meets the interval/period/frequency requirement.
259 * An interrupt request is allowed to be faster than <interval> but not slower.
260 *
261 * For a given <interval>, this function returns the appropriate/matching
262 * skelqh[] index value.
263 *
264 * NOTE: For UHCI, we don't really need int256_qh since the maximum interval
265 * is 255 ms. However, we do need an int1_qh since 1 is a valid interval
266 * and we should meet that frequency when requested to do so.
267 * This will require some change(s) to the UHCI skeleton.
268 */
269 static inline int __interval_to_skel(int interval)
270 {
271 if (interval < 16) {
272 if (interval < 4) {
273 if (interval < 2)
274 return 0; /* int1 for 0-1 ms */
275 return 1; /* int2 for 2-3 ms */
276 }
277 if (interval < 8)
278 return 2; /* int4 for 4-7 ms */
279 return 3; /* int8 for 8-15 ms */
280 }
281 if (interval < 64) {
282 if (interval < 32)
283 return 4; /* int16 for 16-31 ms */
284 return 5; /* int32 for 32-63 ms */
285 }
286 if (interval < 128)
287 return 6; /* int64 for 64-127 ms */
288 return 7; /* int128 for 128-255 ms (Max.) */
289 }
290
291 struct virt_root_hub {
292 int devnum; /* Address of Root Hub endpoint */
293 void *urb;
294 void *int_addr;
295 int send;
296 int interval;
297 int numports;
298 int c_p_r[8];
299 struct timer_list rh_int_timer;
300 };
301
302 /*
303 * This describes the full uhci information.
304 *
305 * Note how the "proper" USB information is just
306 * a subset of what the full implementation needs.
307 */
308 struct uhci {
309 /* Grabbed from PCI */
310 int irq;
311 unsigned int io_addr;
312 unsigned int io_size;
313
314 struct list_head uhci_list;
315
316 struct usb_bus *bus;
317
318 struct uhci_td skeltd[UHCI_NUM_SKELTD]; /* Skeleton TD's */
319 struct uhci_qh skelqh[UHCI_NUM_SKELQH]; /* Skeleton QH's */
320
321 spinlock_t framelist_lock;
322 struct uhci_framelist *fl; /* Frame list */
323 int fsbr; /* Full speed bandwidth reclamation */
324
325 spinlock_t qh_remove_lock;
326 struct list_head qh_remove_list;
327
328 spinlock_t urb_remove_lock;
329 struct list_head urb_remove_list;
330
331 struct s_nested_lock urblist_lock;
332 struct list_head urb_list;
333
334 struct virt_root_hub rh; /* private data of the virtual root hub */
335 };
336
337 struct urb_priv {
338 struct urb *urb;
339
340 struct uhci_qh *qh; /* QH for this URB */
341
342 int fsbr : 1; /* URB turned on FSBR */
343 int fsbr_timeout : 1; /* URB timed out on FSBR */
344 int queued : 1; /* QH was queued (not linked in) */
345 int short_control_packet : 1; /* If we get a short packet during */
346 /* a control transfer, retrigger */
347 /* the status phase */
348
349 unsigned long inserttime; /* In jiffies */
350
351 struct list_head list;
352
353 struct list_head urb_queue_list; /* URB's linked together */
354 };
355
356 /* -------------------------------------------------------------------------
357 Virtual Root HUB
358 ------------------------------------------------------------------------- */
359 /* destination of request */
360 #define RH_DEVICE 0x00
361 #define RH_INTERFACE 0x01
362 #define RH_ENDPOINT 0x02
363 #define RH_OTHER 0x03
364
365 #define RH_CLASS 0x20
366 #define RH_VENDOR 0x40
367
368 /* Requests: bRequest << 8 | bmRequestType */
369 #define RH_GET_STATUS 0x0080
370 #define RH_CLEAR_FEATURE 0x0100
371 #define RH_SET_FEATURE 0x0300
372 #define RH_SET_ADDRESS 0x0500
373 #define RH_GET_DESCRIPTOR 0x0680
374 #define RH_SET_DESCRIPTOR 0x0700
375 #define RH_GET_CONFIGURATION 0x0880
376 #define RH_SET_CONFIGURATION 0x0900
377 #define RH_GET_STATE 0x0280
378 #define RH_GET_INTERFACE 0x0A80
379 #define RH_SET_INTERFACE 0x0B00
380 #define RH_SYNC_FRAME 0x0C80
381 /* Our Vendor Specific Request */
382 #define RH_SET_EP 0x2000
383
384 /* Hub port features */
385 #define RH_PORT_CONNECTION 0x00
386 #define RH_PORT_ENABLE 0x01
387 #define RH_PORT_SUSPEND 0x02
388 #define RH_PORT_OVER_CURRENT 0x03
389 #define RH_PORT_RESET 0x04
390 #define RH_PORT_POWER 0x08
391 #define RH_PORT_LOW_SPEED 0x09
392 #define RH_C_PORT_CONNECTION 0x10
393 #define RH_C_PORT_ENABLE 0x11
394 #define RH_C_PORT_SUSPEND 0x12
395 #define RH_C_PORT_OVER_CURRENT 0x13
396 #define RH_C_PORT_RESET 0x14
397
398 /* Hub features */
399 #define RH_C_HUB_LOCAL_POWER 0x00
400 #define RH_C_HUB_OVER_CURRENT 0x01
401 #define RH_DEVICE_REMOTE_WAKEUP 0x00
402 #define RH_ENDPOINT_STALL 0x01
403
404 /* Our Vendor Specific feature */
405 #define RH_REMOVE_EP 0x00
406
407 #define RH_ACK 0x01
408 #define RH_REQ_ERR -1
409 #define RH_NACK 0x00
410
411 /* needed for the debugging code */
412 struct uhci_td *uhci_link_to_td(unsigned int element);
413
414 /* Debugging code */
415 void uhci_show_td(struct uhci_td *td);
416 void uhci_show_status(struct uhci *uhci);
417 void uhci_show_urb_queue(struct urb *urb);
418 void uhci_show_queue(struct uhci_qh *qh);
419 void uhci_show_queues(struct uhci *uhci);
420
421 #endif
422
423
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