1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000 David Brownell <david-b@pacbell.net>
6 *
7 * usb-ohci.h
8 */
9
10
11 static int cc_to_error[16] = {
12
13 /* mapping of the OHCI CC status to error codes */
14 /* No Error */ USB_ST_NOERROR,
15 /* CRC Error */ USB_ST_CRC,
16 /* Bit Stuff */ USB_ST_BITSTUFF,
17 /* Data Togg */ USB_ST_CRC,
18 /* Stall */ USB_ST_STALL,
19 /* DevNotResp */ USB_ST_NORESPONSE,
20 /* PIDCheck */ USB_ST_BITSTUFF,
21 /* UnExpPID */ USB_ST_BITSTUFF,
22 /* DataOver */ USB_ST_DATAOVERRUN,
23 /* DataUnder */ USB_ST_DATAUNDERRUN,
24 /* reservd */ USB_ST_NORESPONSE,
25 /* reservd */ USB_ST_NORESPONSE,
26 /* BufferOver */ USB_ST_BUFFEROVERRUN,
27 /* BuffUnder */ USB_ST_BUFFERUNDERRUN,
28 /* Not Access */ USB_ST_NORESPONSE,
29 /* Not Access */ USB_ST_NORESPONSE
30 };
31
32
33 /* ED States */
34
35 #define ED_NEW 0x00
36 #define ED_UNLINK 0x01
37 #define ED_OPER 0x02
38 #define ED_DEL 0x04
39 #define ED_URB_DEL 0x08
40
41 /* usb_ohci_ed */
42 typedef struct ed {
43 __u32 hwINFO;
44 __u32 hwTailP;
45 __u32 hwHeadP;
46 __u32 hwNextED;
47
48 struct ed * ed_prev;
49 __u8 int_period;
50 __u8 int_branch;
51 __u8 int_load;
52 __u8 int_interval;
53 __u8 state;
54 __u8 type;
55 __u16 last_iso;
56 struct ed * ed_rm_list;
57
58 } ed_t;
59
60
61 /* TD info field */
62 #define TD_CC 0xf0000000
63 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
64 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
65 #define TD_EC 0x0C000000
66 #define TD_T 0x03000000
67 #define TD_T_DATA0 0x02000000
68 #define TD_T_DATA1 0x03000000
69 #define TD_T_TOGGLE 0x00000000
70 #define TD_R 0x00040000
71 #define TD_DI 0x00E00000
72 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
73 #define TD_DP 0x00180000
74 #define TD_DP_SETUP 0x00000000
75 #define TD_DP_IN 0x00100000
76 #define TD_DP_OUT 0x00080000
77
78 #define TD_ISO 0x00010000
79 #define TD_DEL 0x00020000
80
81 /* CC Codes */
82 #define TD_CC_NOERROR 0x00
83 #define TD_CC_CRC 0x01
84 #define TD_CC_BITSTUFFING 0x02
85 #define TD_CC_DATATOGGLEM 0x03
86 #define TD_CC_STALL 0x04
87 #define TD_DEVNOTRESP 0x05
88 #define TD_PIDCHECKFAIL 0x06
89 #define TD_UNEXPECTEDPID 0x07
90 #define TD_DATAOVERRUN 0x08
91 #define TD_DATAUNDERRUN 0x09
92 #define TD_BUFFEROVERRUN 0x0C
93 #define TD_BUFFERUNDERRUN 0x0D
94 #define TD_NOTACCESSED 0x0F
95
96
97 #define MAXPSW 1
98
99 typedef struct td {
100 __u32 hwINFO;
101 __u32 hwCBP; /* Current Buffer Pointer */
102 __u32 hwNextTD; /* Next TD Pointer */
103 __u32 hwBE; /* Memory Buffer End Pointer */
104 __u16 hwPSW[MAXPSW];
105
106 __u8 unused;
107 __u8 index;
108 struct ed * ed;
109 struct td * next_dl_td;
110 urb_t * urb;
111 } td_t;
112
113
114 #define OHCI_ED_SKIP (1 << 14)
115
116 /*
117 * The HCCA (Host Controller Communications Area) is a 256 byte
118 * structure defined in the OHCI spec. that the host controller is
119 * told the base address of. It must be 256-byte aligned.
120 */
121
122 #define NUM_INTS 32 /* part of the OHCI standard */
123 struct ohci_hcca {
124 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
125 __u16 frame_no; /* current frame number */
126 __u16 pad1; /* set to 0 on each frame_no change */
127 __u32 done_head; /* info returned for an interrupt */
128 u8 reserved_for_hc[116];
129 } __attribute((aligned(256)));
130
131
132 /*
133 * Maximum number of root hub ports.
134 */
135 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
136
137 /*
138 * This is the structure of the OHCI controller's memory mapped I/O
139 * region. This is Memory Mapped I/O. You must use the readl() and
140 * writel() macros defined in asm/io.h to access these!!
141 */
142 struct ohci_regs {
143 /* control and status registers */
144 __u32 revision;
145 __u32 control;
146 __u32 cmdstatus;
147 __u32 intrstatus;
148 __u32 intrenable;
149 __u32 intrdisable;
150 /* memory pointers */
151 __u32 hcca;
152 __u32 ed_periodcurrent;
153 __u32 ed_controlhead;
154 __u32 ed_controlcurrent;
155 __u32 ed_bulkhead;
156 __u32 ed_bulkcurrent;
157 __u32 donehead;
158 /* frame counters */
159 __u32 fminterval;
160 __u32 fmremaining;
161 __u32 fmnumber;
162 __u32 periodicstart;
163 __u32 lsthresh;
164 /* Root hub ports */
165 struct ohci_roothub_regs {
166 __u32 a;
167 __u32 b;
168 __u32 status;
169 __u32 portstatus[MAX_ROOT_PORTS];
170 } roothub;
171 } __attribute((aligned(32)));
172
173
174 /* OHCI CONTROL AND STATUS REGISTER MASKS */
175
176 /*
177 * HcControl (control) register masks
178 */
179 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
180 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
181 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
182 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
183 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
184 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
185 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
186 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
187 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
188
189 /* pre-shifted values for HCFS */
190 # define OHCI_USB_RESET (0 << 6)
191 # define OHCI_USB_RESUME (1 << 6)
192 # define OHCI_USB_OPER (2 << 6)
193 # define OHCI_USB_SUSPEND (3 << 6)
194
195 /*
196 * HcCommandStatus (cmdstatus) register masks
197 */
198 #define OHCI_HCR (1 << 0) /* host controller reset */
199 #define OHCI_CLF (1 << 1) /* control list filled */
200 #define OHCI_BLF (1 << 2) /* bulk list filled */
201 #define OHCI_OCR (1 << 3) /* ownership change request */
202 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
203
204 /*
205 * masks used with interrupt registers:
206 * HcInterruptStatus (intrstatus)
207 * HcInterruptEnable (intrenable)
208 * HcInterruptDisable (intrdisable)
209 */
210 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
211 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
212 #define OHCI_INTR_SF (1 << 2) /* start frame */
213 #define OHCI_INTR_RD (1 << 3) /* resume detect */
214 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
215 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
216 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
217 #define OHCI_INTR_OC (1 << 30) /* ownership change */
218 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
219
220
221
222 /* Virtual Root HUB */
223 struct virt_root_hub {
224 int devnum; /* Address of Root Hub endpoint */
225 void * urb;
226 void * int_addr;
227 int send;
228 int interval;
229 struct timer_list rh_int_timer;
230 };
231
232
233 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
234
235 /* destination of request */
236 #define RH_INTERFACE 0x01
237 #define RH_ENDPOINT 0x02
238 #define RH_OTHER 0x03
239
240 #define RH_CLASS 0x20
241 #define RH_VENDOR 0x40
242
243 /* Requests: bRequest << 8 | bmRequestType */
244 #define RH_GET_STATUS 0x0080
245 #define RH_CLEAR_FEATURE 0x0100
246 #define RH_SET_FEATURE 0x0300
247 #define RH_SET_ADDRESS 0x0500
248 #define RH_GET_DESCRIPTOR 0x0680
249 #define RH_SET_DESCRIPTOR 0x0700
250 #define RH_GET_CONFIGURATION 0x0880
251 #define RH_SET_CONFIGURATION 0x0900
252 #define RH_GET_STATE 0x0280
253 #define RH_GET_INTERFACE 0x0A80
254 #define RH_SET_INTERFACE 0x0B00
255 #define RH_SYNC_FRAME 0x0C80
256 /* Our Vendor Specific Request */
257 #define RH_SET_EP 0x2000
258
259
260 /* Hub port features */
261 #define RH_PORT_CONNECTION 0x00
262 #define RH_PORT_ENABLE 0x01
263 #define RH_PORT_SUSPEND 0x02
264 #define RH_PORT_OVER_CURRENT 0x03
265 #define RH_PORT_RESET 0x04
266 #define RH_PORT_POWER 0x08
267 #define RH_PORT_LOW_SPEED 0x09
268
269 #define RH_C_PORT_CONNECTION 0x10
270 #define RH_C_PORT_ENABLE 0x11
271 #define RH_C_PORT_SUSPEND 0x12
272 #define RH_C_PORT_OVER_CURRENT 0x13
273 #define RH_C_PORT_RESET 0x14
274
275 /* Hub features */
276 #define RH_C_HUB_LOCAL_POWER 0x00
277 #define RH_C_HUB_OVER_CURRENT 0x01
278
279 #define RH_DEVICE_REMOTE_WAKEUP 0x00
280 #define RH_ENDPOINT_STALL 0x01
281
282 #define RH_ACK 0x01
283 #define RH_REQ_ERR -1
284 #define RH_NACK 0x00
285
286
287 /* OHCI ROOT HUB REGISTER MASKS */
288
289 /* roothub.portstatus [i] bits */
290 #define RH_PS_CCS 0x00000001 /* current connect status */
291 #define RH_PS_PES 0x00000002 /* port enable status*/
292 #define RH_PS_PSS 0x00000004 /* port suspend status */
293 #define RH_PS_POCI 0x00000008 /* port over current indicator */
294 #define RH_PS_PRS 0x00000010 /* port reset status */
295 #define RH_PS_PPS 0x00000100 /* port power status */
296 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
297 #define RH_PS_CSC 0x00010000 /* connect status change */
298 #define RH_PS_PESC 0x00020000 /* port enable status change */
299 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
300 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
301 #define RH_PS_PRSC 0x00100000 /* port reset status change */
302
303 /* roothub.status bits */
304 #define RH_HS_LPS 0x00000001 /* local power status */
305 #define RH_HS_OCI 0x00000002 /* over current indicator */
306 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
307 #define RH_HS_LPSC 0x00010000 /* local power status change */
308 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
309 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
310
311 /* roothub.b masks */
312 #define RH_B_DR 0x0000ffff /* device removable flags */
313 #define RH_B_PPCM 0xffff0000 /* port power control mask */
314
315 /* roothub.a masks */
316 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
317 #define RH_A_PSM (1 << 8) /* power switching mode */
318 #define RH_A_NPS (1 << 9) /* no power switching */
319 #define RH_A_DT (1 << 10) /* device type (mbz) */
320 #define RH_A_OCPM (1 << 11) /* over current protection mode */
321 #define RH_A_NOCP (1 << 12) /* no over current protection */
322 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
323
324 #define min(a,b) (((a)<(b))?(a):(b))
325
326
327 /* urb */
328 typedef struct
329 {
330 ed_t * ed;
331 __u16 length; // number of tds associated with this request
332 __u16 td_cnt; // number of tds already serviced
333 int state;
334 wait_queue_head_t * wait;
335 td_t * td[0]; // list pointer to all corresponding TDs associated with this request
336
337 } urb_priv_t;
338 #define URB_DEL 1
339
340 /*
341 * This is the full ohci controller description
342 *
343 * Note how the "proper" USB information is just
344 * a subset of what the full implementation needs. (Linus)
345 */
346
347
348 typedef struct ohci {
349 struct ohci_hcca hcca; /* hcca */
350
351 int irq;
352 int disabled; /* e.g. got a UE, we're hung */
353 atomic_t resume_count; /* defending against multiple resumes */
354
355 struct ohci_regs * regs; /* OHCI controller's memory */
356 struct list_head ohci_hcd_list; /* list of all ohci_hcd */
357
358 struct ohci * next; // chain of uhci device contexts
359 // struct list_head urb_list; // list of all pending urbs
360 // spinlock_t urb_list_lock; // lock to keep consistency
361
362 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
363 ed_t * ed_rm_list[2]; /* lists of all endpoints to be removed */
364 ed_t * ed_bulktail; /* last endpoint of bulk list */
365 ed_t * ed_controltail; /* last endpoint of control list */
366 ed_t * ed_isotail; /* last endpoint of iso list */
367 int intrstatus;
368 __u32 hc_control; /* copy of the hc control reg */
369 struct usb_bus * bus;
370 struct usb_device * dev[128];
371 struct virt_root_hub rh;
372
373 /* PCI device handle and settings */
374 struct pci_dev *ohci_dev;
375 u8 pci_latency;
376 } ohci_t;
377
378
379 #define NUM_TDS 0 /* num of preallocated transfer descriptors */
380 #define NUM_EDS 32 /* num of preallocated endpoint descriptors */
381
382 struct ohci_device {
383 ed_t ed[NUM_EDS];
384 int ed_cnt;
385 wait_queue_head_t * wait;
386 };
387
388 // #define ohci_to_usb(ohci) ((ohci)->usb)
389 #define usb_to_ohci(usb) ((struct ohci_device *)(usb)->hcpriv)
390
391 /* hcd */
392 /* endpoint */
393 static int ep_link(ohci_t * ohci, ed_t * ed);
394 static int ep_unlink(ohci_t * ohci, ed_t * ed);
395 static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned int pipe, int interval, int load);
396 static void ep_rm_ed(struct usb_device * usb_dev, ed_t * ed);
397 /* td */
398 static void td_fill(unsigned int info, void * data, int len, urb_t * urb, int index);
399 static void td_submit_urb(urb_t * urb);
400 /* root hub */
401 static int rh_submit_urb(urb_t * urb);
402 static int rh_unlink_urb(urb_t * urb);
403 static int rh_init_int_timer(urb_t * urb);
404
405 /*-------------------------------------------------------------------------*/
406
407 #define ALLOC_FLAGS (in_interrupt () ? GFP_ATOMIC : GFP_KERNEL)
408
409 #ifdef OHCI_MEM_SLAB
410 #define __alloc(t,c) kmem_cache_alloc(c,ALLOC_FLAGS)
411 #define __free(c,x) kmem_cache_free(c,x)
412 static kmem_cache_t *td_cache, *ed_cache;
413
414 /*
415 * WARNING: do NOT use this with "forced slab debug"; it won't respect
416 * our hardware alignment requirement.
417 */
418 #ifndef OHCI_MEM_FLAGS
419 #define OHCI_MEM_FLAGS 0
420 #endif
421
422 static int ohci_mem_init (void)
423 {
424 /* redzoning (or forced debug!) breaks alignment */
425 int flags = (OHCI_MEM_FLAGS) & ~SLAB_RED_ZONE;
426
427 /* TDs accessed by controllers and host */
428 td_cache = kmem_cache_create ("ohci_td", sizeof (struct td), 0,
429 flags | SLAB_HWCACHE_ALIGN, NULL, NULL);
430 if (!td_cache) {
431 dbg ("no TD cache?");
432 return -ENOMEM;
433 }
434
435 /* EDs are accessed by controllers and host; dev part is host-only */
436 ed_cache = kmem_cache_create ("ohci_ed", sizeof (struct ohci_device), 0,
437 flags | SLAB_HWCACHE_ALIGN, NULL, NULL);
438 if (!ed_cache) {
439 dbg ("no ED cache?");
440 kmem_cache_destroy (td_cache);
441 td_cache = 0;
442 return -ENOMEM;
443 }
444 dbg ("slab flags 0x%x", flags);
445 return 0;
446 }
447
448 static void ohci_mem_cleanup (void)
449 {
450 if (ed_cache && kmem_cache_destroy (ed_cache))
451 err ("ed_cache remained");
452 ed_cache = 0;
453
454 if (td_cache && kmem_cache_destroy (td_cache))
455 err ("td_cache remained");
456 td_cache = 0;
457 }
458
459 #else
460 #define __alloc(t,c) kmalloc(sizeof(t),ALLOC_FLAGS)
461 #define __free(dev,x) kfree(x)
462 #define td_cache 0
463 #define ed_cache 0
464
465 static inline int ohci_mem_init (void) { return 0; }
466 static inline void ohci_mem_cleanup (void) { return; }
467
468 /* FIXME: pci_consistent version */
469
470 #endif
471
472
473 /* TDs ... */
474 static inline struct td *
475 td_alloc (struct ohci *hc)
476 {
477 struct td *td = (struct td *) __alloc (struct td, td_cache);
478 return td;
479 }
480
481 static inline void
482 td_free (struct ohci *hc, struct td *td)
483 {
484 __free (td_cache, td);
485 }
486
487
488 /* DEV + EDs ... only the EDs need to be consistent */
489 static inline struct ohci_device *
490 dev_alloc (struct ohci *hc)
491 {
492 struct ohci_device *dev = (struct ohci_device *)
493 __alloc (struct ohci_device, ed_cache);
494 return dev;
495 }
496
497 static inline void
498 dev_free (struct ohci_device *dev)
499 {
500 __free (ed_cache, dev);
501 }
502
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