1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Based off of Geert's atyfb.c and vfb.c.
11 *
12 * TODO:
13 * - panning
14 * - monitor sensing (DDC)
15 * - virtual display
16 * - other platform support (only ppc/x86 supported)
17 * - hardware cursor support
18 * - ioctl()'s
19 *
20 * Please cc: your patches to brad@neruo.com.
21 */
22
23 /*
24 * A special note of gratitude to ATI's devrel for providing documentation,
25 * example code and hardware. Thanks Nitya. -atong and brad
26 */
27
28
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/errno.h>
33 #include <linux/string.h>
34 #include <linux/mm.h>
35 #include <linux/tty.h>
36 #include <linux/malloc.h>
37 #include <linux/vmalloc.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <asm/uaccess.h>
41 #include <linux/fb.h>
42 #include <linux/init.h>
43 #include <linux/selection.h>
44 #include <linux/console.h>
45 #include <linux/pci.h>
46 #include <linux/ioport.h>
47 #include <asm/io.h>
48
49 #ifdef CONFIG_PPC
50 #include <asm/prom.h>
51 #include <asm/pci-bridge.h>
52 #include <video/macmodes.h>
53 #ifdef CONFIG_NVRAM
54 #include <linux/nvram.h>
55 #endif
56 #endif
57
58 #ifdef CONFIG_ADB_PMU
59 #include <linux/adb.h>
60 #include <linux/pmu.h>
61 #endif
62
63 #ifdef CONFIG_PMAC_BACKLIGHT
64 #include <asm/backlight.h>
65 #endif
66
67 #ifdef CONFIG_FB_COMPAT_XPMAC
68 #include <asm/vc_ioctl.h>
69 #endif
70
71 #include <video/fbcon.h>
72 #include <video/fbcon-cfb8.h>
73 #include <video/fbcon-cfb16.h>
74 #include <video/fbcon-cfb24.h>
75 #include <video/fbcon-cfb32.h>
76
77 #ifdef CONFIG_MTRR
78 #include <asm/mtrr.h>
79 #endif
80
81 #include "aty128.h"
82
83 /* Debug flag */
84 #undef DEBUG
85
86 #ifdef DEBUG
87 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
88 #else
89 #define DBG(fmt, args...)
90 #endif
91
92 #ifndef CONFIG_PPC
93 /* default mode */
94 static struct fb_var_screeninfo default_var __initdata = {
95 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
96 640, 480, 640, 480, 0, 0, 8, 0,
97 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
98 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
99 0, FB_VMODE_NONINTERLACED
100 };
101
102 #else /* CONFIG_PPC */
103 /* default to 1024x768 at 75Hz on PPC - this will work
104 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
105 static struct fb_var_screeninfo default_var = {
106 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
107 1024, 768, 1024, 768, 0, 0, 8, 0,
108 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
109 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
110 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
111 };
112 #endif /* CONFIG_PPC */
113
114 #ifndef MODULE
115 /* default modedb mode */
116 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
117 static struct fb_videomode defaultmode __initdata = {
118 refresh: 60,
119 xres: 640,
120 yres: 480,
121 pixclock: 39722,
122 left_margin: 48,
123 right_margin: 16,
124 upper_margin: 33,
125 lower_margin: 10,
126 hsync_len: 96,
127 vsync_len: 2,
128 sync: 0,
129 vmode: FB_VMODE_NONINTERLACED
130 };
131 #endif /* MODULE */
132
133 /* struct to hold chip description information */
134 struct aty128_chip_info {
135 const char *name;
136 unsigned short device;
137 int chip_gen;
138 };
139
140 /* Chip generations */
141 enum {
142 rage_128,
143 rage_128_pro,
144 rage_M3
145 };
146
147 /* supported Rage128 chipsets */
148 static const struct aty128_chip_info aty128_pci_probe_list[] __initdata =
149 {
150 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE, rage_128},
151 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF, rage_128},
152 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK, rage_128},
153 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL, rage_128},
154 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF, rage_128_pro},
155 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR, rage_128_pro},
156 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE, rage_M3},
157 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF, rage_M3},
158 {NULL, 0, rage_128}
159 };
160
161 /* packed BIOS settings */
162 #ifndef CONFIG_PPC
163 typedef struct {
164 u8 clock_chip_type;
165 u8 struct_size;
166 u8 accelerator_entry;
167 u8 VGA_entry;
168 u16 VGA_table_offset;
169 u16 POST_table_offset;
170 u16 XCLK;
171 u16 MCLK;
172 u8 num_PLL_blocks;
173 u8 size_PLL_blocks;
174 u16 PCLK_ref_freq;
175 u16 PCLK_ref_divider;
176 u32 PCLK_min_freq;
177 u32 PCLK_max_freq;
178 u16 MCLK_ref_freq;
179 u16 MCLK_ref_divider;
180 u32 MCLK_min_freq;
181 u32 MCLK_max_freq;
182 u16 XCLK_ref_freq;
183 u16 XCLK_ref_divider;
184 u32 XCLK_min_freq;
185 u32 XCLK_max_freq;
186 } __attribute__ ((packed)) PLL_BLOCK;
187 #endif /* !CONFIG_PPC */
188
189 /* onboard memory information */
190 struct aty128_meminfo {
191 u8 ML;
192 u8 MB;
193 u8 Trcd;
194 u8 Trp;
195 u8 Twr;
196 u8 CL;
197 u8 Tr2w;
198 u8 LoopLatency;
199 u8 DspOn;
200 u8 Rloop;
201 const char *name;
202 };
203
204 /* various memory configurations */
205 static const struct aty128_meminfo sdr_128 =
206 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
207 static const struct aty128_meminfo sdr_64 =
208 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
209 static const struct aty128_meminfo sdr_sgram =
210 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
211 static const struct aty128_meminfo ddr_sgram =
212 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
213
214 static const char *aty128fb_name = "ATY Rage128";
215 static char fontname[40] __initdata = { 0 };
216 static int noaccel __initdata = 0;
217
218 #ifndef MODULE
219 static const char *mode_option __initdata = NULL;
220 #endif
221
222 #ifdef CONFIG_PPC
223 static int default_vmode __initdata = VMODE_1024_768_60;
224 static int default_cmode __initdata = CMODE_8;
225 #endif
226
227 #ifdef CONFIG_MTRR
228 static int mtrr = 1;
229 #endif
230
231 /* PLL constants */
232 struct aty128_constants {
233 u32 dotclock;
234 u32 ppll_min;
235 u32 ppll_max;
236 u32 ref_divider;
237 u32 xclk;
238 u32 fifo_width;
239 u32 fifo_depth;
240 };
241
242 struct aty128_crtc {
243 u32 gen_cntl;
244 u32 ext_cntl;
245 u32 h_total, h_sync_strt_wid;
246 u32 v_total, v_sync_strt_wid;
247 u32 pitch;
248 u32 offset, offset_cntl;
249 u32 xoffset, yoffset;
250 u32 vxres, vyres;
251 u32 bpp;
252 };
253
254 struct aty128_pll {
255 u32 post_divider;
256 u32 feedback_divider;
257 u32 vclk;
258 };
259
260 struct aty128_ddafifo {
261 u32 dda_config;
262 u32 dda_on_off;
263 };
264
265 /* register values for a specific mode */
266 struct aty128fb_par {
267 struct aty128_crtc crtc;
268 struct aty128_pll pll;
269 struct aty128_ddafifo fifo_reg;
270 u32 accel_flags;
271 };
272
273 struct fb_info_aty128 {
274 struct fb_info fb_info;
275 struct fb_info_aty128 *next;
276 struct aty128_constants constants; /* PLL and others */
277 u32 regbase_phys; /* physical mmio */
278 void *regbase; /* remapped mmio */
279 u32 frame_buffer_phys; /* physical fb memory */
280 u32 frame_buffer; /* remaped framebuffer */
281 u32 vram_size; /* onboard video ram */
282 int chip_gen;
283 const struct aty128_meminfo *mem; /* onboard mem info */
284 struct aty128fb_par default_par, current_par;
285 struct display disp;
286 struct { u8 red, green, blue, pad; } palette[256];
287 union {
288 #ifdef FBCON_HAS_CFB16
289 u16 cfb16[16];
290 #endif
291 #ifdef FBCON_HAS_CFB24
292 u32 cfb24[16];
293 #endif
294 #ifdef FBCON_HAS_CFB32
295 u32 cfb32[16];
296 #endif
297 } fbcon_cmap;
298 #ifdef CONFIG_PCI
299 struct pci_dev *pdev;
300 #endif
301 #ifdef CONFIG_MTRR
302 struct { int vram; int vram_valid; } mtrr;
303 #endif
304 int currcon;
305 int blitter_may_be_busy;
306 int fifo_slots; /* free slots in FIFO (64 max) */
307 };
308
309 static struct fb_info_aty128 *board_list = NULL;
310
311 #define round_div(n, d) ((n+(d/2))/d)
312
313 /*
314 * Interface used by the world
315 */
316
317 int aty128fb_setup(char *options);
318
319 static int aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con,
320 struct fb_info *info);
321 static int aty128fb_get_var(struct fb_var_screeninfo *var, int con,
322 struct fb_info *info);
323 static int aty128fb_set_var(struct fb_var_screeninfo *var, int con,
324 struct fb_info *info);
325 static int aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
326 struct fb_info *info);
327 static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
328 struct fb_info *info);
329 static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
330 struct fb_info *fb);
331 static int aty128fb_rasterimg(struct fb_info *info, int start);
332
333
334 /*
335 * Interface to the low level console driver
336 */
337
338 int aty128fb_init(void);
339 static int aty128fbcon_switch(int con, struct fb_info *fb);
340 static void aty128fbcon_blank(int blank, struct fb_info *fb);
341
342 /*
343 * Internal routines
344 */
345
346 static void aty128_encode_fix(struct fb_fix_screeninfo *fix,
347 struct aty128fb_par *par,
348 const struct fb_info_aty128 *info);
349 static void aty128_set_dispsw(struct display *disp,
350 struct fb_info_aty128 *info, int bpp, int accel);
351 static int aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
352 u_int *transp, struct fb_info *info);
353 static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
354 u_int transp, struct fb_info *info);
355 static void do_install_cmap(int con, struct fb_info *info);
356 static int aty128_encode_var(struct fb_var_screeninfo *var,
357 const struct aty128fb_par *par,
358 const struct fb_info_aty128 *info);
359 static int aty128_decode_var(struct fb_var_screeninfo *var,
360 struct aty128fb_par *par,
361 const struct fb_info_aty128 *info);
362 static int aty128_pci_register(struct pci_dev *pdev,
363 const struct aty128_chip_info *aci);
364 static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
365 *board_list, struct fb_info_aty128 *new_node);
366 #if !defined(CONFIG_PPC) && !defined(__sparc__)
367 static void __init aty128_get_pllinfo(struct fb_info_aty128 *info,
368 char *bios_seg);
369 static char __init *aty128find_ROM(struct fb_info_aty128 *info);
370 #endif
371 static void aty128_timings(struct fb_info_aty128 *info);
372 static void aty128_init_engine(const struct aty128fb_par *par,
373 struct fb_info_aty128 *info);
374 static void aty128_reset_engine(const struct fb_info_aty128 *info);
375 static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info);
376 static void do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
377 static void wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
378 static void wait_for_idle(struct fb_info_aty128 *info);
379 static u32 bpp_to_depth(u32 bpp);
380
381 #ifdef FBCON_HAS_CFB8
382 static struct display_switch fbcon_aty128_8;
383 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
384 int c, int yy, int xx);
385 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
386 const unsigned short *s, int count,
387 int yy, int xx);
388 #endif
389 #ifdef FBCON_HAS_CFB16
390 static struct display_switch fbcon_aty128_16;
391 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
392 int c, int yy, int xx);
393 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
394 const unsigned short *s, int count,
395 int yy, int xx);
396 #endif
397 #ifdef FBCON_HAS_CFB24
398 static struct display_switch fbcon_aty128_24;
399 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
400 int c, int yy, int xx);
401 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
402 const unsigned short *s, int count,
403 int yy, int xx);
404 #endif
405 #ifdef FBCON_HAS_CFB32
406 static struct display_switch fbcon_aty128_32;
407 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
408 int c, int yy, int xx);
409 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
410 const unsigned short *s, int count,
411 int yy, int xx);
412 #endif
413
414 static struct fb_ops aty128fb_ops = {
415 owner: THIS_MODULE,
416 fb_get_fix: aty128fb_get_fix,
417 fb_get_var: aty128fb_get_var,
418 fb_set_var: aty128fb_set_var,
419 fb_get_cmap: aty128fb_get_cmap,
420 fb_set_cmap: aty128fb_set_cmap,
421 fb_pan_display: aty128fb_pan_display,
422 fb_rasterimg: aty128fb_rasterimg,
423 };
424
425 #ifdef CONFIG_PMAC_BACKLIGHT
426 static int aty128_set_backlight_enable(int on, int level, void* data);
427 static int aty128_set_backlight_level(int level, void* data);
428
429 static struct backlight_controller aty128_backlight_controller = {
430 aty128_set_backlight_enable,
431 aty128_set_backlight_level
432 };
433 #endif /* CONFIG_PMAC_BACKLIGHT */
434
435 /*
436 * Functions to read from/write to the mmio registers
437 * - endian conversions may possibly be avoided by
438 * using the other register aperture. TODO.
439 */
440 static inline u32
441 _aty_ld_le32(volatile unsigned int regindex,
442 const struct fb_info_aty128 *info)
443 {
444 u32 val;
445
446 #if defined(__powerpc__)
447 asm("lwbrx %0,%1,%2;eieio" : "=r"(val) : "b"(regindex), "r"(info->regbase));
448 #else
449 val = readl (info->regbase + regindex);
450 #endif
451
452 return val;
453 }
454
455 static inline void
456 _aty_st_le32(volatile unsigned int regindex, u32 val,
457 const struct fb_info_aty128 *info)
458 {
459 #if defined(__powerpc__)
460 asm("stwbrx %0,%1,%2;eieio" : : "r"(val), "b"(regindex),
461 "r"(info->regbase) : "memory");
462 #else
463 writel (val, info->regbase + regindex);
464 #endif
465 }
466
467 static inline u8
468 _aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info)
469 {
470 return readb (info->regbase + regindex);
471 }
472
473 static inline void
474 _aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info)
475 {
476 writeb (val, info->regbase + regindex);
477 }
478
479 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
480 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info)
481 #define aty_ld_8(regindex) _aty_ld_8(regindex, info)
482 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, info)
483
484 /*
485 * Functions to read from/write to the pll registers
486 */
487
488 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
489 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
490
491
492 static u32
493 _aty_ld_pll(unsigned int pll_index,
494 const struct fb_info_aty128 *info)
495 {
496 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x1F);
497 return aty_ld_le32(CLOCK_CNTL_DATA);
498 }
499
500
501 static void
502 _aty_st_pll(unsigned int pll_index, u32 val,
503 const struct fb_info_aty128 *info)
504 {
505 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x1F) | PLL_WR_EN);
506 aty_st_le32(CLOCK_CNTL_DATA, val);
507 }
508
509
510 /* return true when the PLL has completed an atomic update */
511 static int
512 aty_pll_readupdate(const struct fb_info_aty128 *info)
513 {
514 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
515 }
516
517
518 static void
519 aty_pll_wait_readupdate(const struct fb_info_aty128 *info)
520 {
521 unsigned long timeout = jiffies + HZ/100; // should be more than enough
522 int reset = 1;
523
524 while (time_before(jiffies, timeout))
525 if (aty_pll_readupdate(info)) {
526 reset = 0;
527 break;
528 }
529
530 if (reset) /* reset engine?? */
531 printk(KERN_DEBUG "aty128fb: PLL write timeout!");
532 }
533
534
535 /* tell PLL to update */
536 static void
537 aty_pll_writeupdate(const struct fb_info_aty128 *info)
538 {
539 aty_pll_wait_readupdate(info);
540
541 aty_st_pll(PPLL_REF_DIV,
542 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
543 }
544
545
546 /* write to the scratch register to test r/w functionality */
547 static int __init
548 register_test(const struct fb_info_aty128 *info)
549 {
550 u32 val;
551 int flag = 0;
552
553 val = aty_ld_le32(BIOS_0_SCRATCH);
554
555 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
556 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
557 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
558
559 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
560 flag = 1;
561 }
562
563 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
564 return flag;
565 }
566
567
568 /*
569 * Accelerator engine functions
570 */
571 static void
572 do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
573 {
574 int i;
575
576 for (;;) {
577 for (i = 0; i < 2000000; i++) {
578 info->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
579 if (info->fifo_slots >= entries)
580 return;
581 }
582 aty128_reset_engine(info);
583 }
584 }
585
586
587 static void
588 wait_for_idle(struct fb_info_aty128 *info)
589 {
590 int i;
591
592 do_wait_for_fifo(64, info);
593
594 for (;;) {
595 for (i = 0; i < 2000000; i++) {
596 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
597 aty128_flush_pixel_cache(info);
598 info->blitter_may_be_busy = 0;
599 return;
600 }
601 }
602 aty128_reset_engine(info);
603 }
604 }
605
606
607 static void
608 wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
609 {
610 if (info->fifo_slots < entries)
611 do_wait_for_fifo(64, info);
612 info->fifo_slots -= entries;
613 }
614
615
616 static void
617 aty128_flush_pixel_cache(const struct fb_info_aty128 *info)
618 {
619 int i;
620 u32 tmp;
621
622 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
623 tmp &= ~(0x00ff);
624 tmp |= 0x00ff;
625 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
626
627 for (i = 0; i < 2000000; i++)
628 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
629 break;
630 }
631
632
633 static void
634 aty128_reset_engine(const struct fb_info_aty128 *info)
635 {
636 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
637
638 aty128_flush_pixel_cache(info);
639
640 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
641 mclk_cntl = aty_ld_pll(MCLK_CNTL);
642
643 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
644
645 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
646 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
647 aty_ld_le32(GEN_RESET_CNTL);
648 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
649 aty_ld_le32(GEN_RESET_CNTL);
650
651 aty_st_pll(MCLK_CNTL, mclk_cntl);
652 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
653 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
654
655 /* use old pio mode */
656 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
657
658 DBG("engine reset");
659 }
660
661
662 static void
663 aty128_init_engine(const struct aty128fb_par *par,
664 struct fb_info_aty128 *info)
665 {
666 u32 pitch_value;
667
668 wait_for_idle(info);
669
670 /* 3D scaler not spoken here */
671 wait_for_fifo(1, info);
672 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
673
674 aty128_reset_engine(info);
675
676 pitch_value = par->crtc.pitch;
677 if (par->crtc.bpp == 24) {
678 pitch_value = pitch_value * 3;
679 }
680
681 wait_for_fifo(4, info);
682 /* setup engine offset registers */
683 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
684
685 /* setup engine pitch registers */
686 aty_st_le32(DEFAULT_PITCH, pitch_value);
687
688 /* set the default scissor register to max dimensions */
689 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
690
691 /* set the drawing controls registers */
692 aty_st_le32(DP_GUI_MASTER_CNTL,
693 GMC_SRC_PITCH_OFFSET_DEFAULT |
694 GMC_DST_PITCH_OFFSET_DEFAULT |
695 GMC_SRC_CLIP_DEFAULT |
696 GMC_DST_CLIP_DEFAULT |
697 GMC_BRUSH_SOLIDCOLOR |
698 (bpp_to_depth(par->crtc.bpp) << 8) |
699 GMC_SRC_DSTCOLOR |
700 GMC_BYTE_ORDER_MSB_TO_LSB |
701 GMC_DP_CONVERSION_TEMP_6500 |
702 ROP3_PATCOPY |
703 GMC_DP_SRC_RECT |
704 GMC_3D_FCN_EN_CLR |
705 GMC_DST_CLR_CMP_FCN_CLEAR |
706 GMC_AUX_CLIP_CLEAR |
707 GMC_WRITE_MASK_SET);
708
709 wait_for_fifo(8, info);
710 /* clear the line drawing registers */
711 aty_st_le32(DST_BRES_ERR, 0);
712 aty_st_le32(DST_BRES_INC, 0);
713 aty_st_le32(DST_BRES_DEC, 0);
714
715 /* set brush color registers */
716 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
717 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
718
719 /* set source color registers */
720 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
721 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
722
723 /* default write mask */
724 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
725
726 /* Wait for all the writes to be completed before returning */
727 wait_for_idle(info);
728 }
729
730
731 /* convert bpp values to their register representation */
732 static u32
733 bpp_to_depth(u32 bpp)
734 {
735 if (bpp <= 8)
736 return DST_8BPP;
737 else if (bpp <= 16)
738 return DST_15BPP;
739 else if (bpp <= 24)
740 return DST_24BPP;
741 else if (bpp <= 32)
742 return DST_32BPP;
743
744 return -EINVAL;
745 }
746
747
748 /*
749 * CRTC programming
750 */
751
752 /* Program the CRTC registers */
753 static void
754 aty128_set_crtc(const struct aty128_crtc *crtc,
755 const struct fb_info_aty128 *info)
756 {
757 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
758 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
759 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
760 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
761 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
762 aty_st_le32(CRTC_PITCH, crtc->pitch);
763 aty_st_le32(CRTC_OFFSET, crtc->offset);
764 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
765 /* Disable ATOMIC updating. Is this the right place?
766 * -- BenH: Breaks on my G4
767 */
768 #if 0
769 aty_st_le32(PPLL_CNTL, aty_ld_le32(PPLL_CNTL) & ~(0x00030000));
770 #endif
771 }
772
773
774 static int
775 aty128_var_to_crtc(const struct fb_var_screeninfo *var,
776 struct aty128_crtc *crtc,
777 const struct fb_info_aty128 *info)
778 {
779 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
780 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
781 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
782 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
783 u32 depth, bytpp;
784 u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 };
785 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
786
787 /* input */
788 xres = var->xres;
789 yres = var->yres;
790 vxres = var->xres_virtual;
791 vyres = var->yres_virtual;
792 xoffset = var->xoffset;
793 yoffset = var->yoffset;
794 bpp = var->bits_per_pixel;
795 left = var->left_margin;
796 right = var->right_margin;
797 upper = var->upper_margin;
798 lower = var->lower_margin;
799 hslen = var->hsync_len;
800 vslen = var->vsync_len;
801 sync = var->sync;
802 vmode = var->vmode;
803
804 /* check for mode eligibility
805 * accept only non interlaced modes */
806 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
807 return -EINVAL;
808
809 /* convert (and round up) and validate */
810 xres = (xres + 7) & ~7;
811 xoffset = (xoffset + 7) & ~7;
812
813 if (vxres < xres + xoffset)
814 vxres = xres + xoffset;
815
816 if (vyres < yres + yoffset)
817 vyres = yres + yoffset;
818
819 /* convert bpp into ATI register depth */
820 depth = bpp_to_depth(bpp);
821
822 /* make sure we didn't get an invalid depth */
823 if (depth == -EINVAL) {
824 printk(KERN_ERR "aty128fb: Invalid depth\n");
825 return -EINVAL;
826 }
827
828 /* convert depth to bpp */
829 bytpp = mode_bytpp[depth];
830
831 /* make sure there is enough video ram for the mode */
832 if ((u32)(vxres * vyres * bytpp) > info->vram_size) {
833 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
834 return -EINVAL;
835 }
836
837 h_disp = (xres >> 3) - 1;
838 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
839
840 v_disp = yres - 1;
841 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
842
843 /* check to make sure h_total and v_total are in range */
844 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
845 printk(KERN_ERR "aty128fb: invalid width ranges\n");
846 return -EINVAL;
847 }
848
849 h_sync_wid = (hslen + 7) >> 3;
850 if (h_sync_wid == 0)
851 h_sync_wid = 1;
852 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
853 h_sync_wid = 0x3f;
854
855 h_sync_strt = h_disp + (right >> 3);
856
857 v_sync_wid = vslen;
858 if (v_sync_wid == 0)
859 v_sync_wid = 1;
860 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
861 v_sync_wid = 0x1f;
862
863 v_sync_strt = v_disp + lower;
864
865 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
866 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
867
868 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
869
870 crtc->gen_cntl = 0x3000000L | c_sync | (depth << 8);
871
872 crtc->h_total = h_total | (h_disp << 16);
873 crtc->v_total = v_total | (v_disp << 16);
874
875 crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) |
876 (h_sync_wid << 16) | (h_sync_pol << 23);
877 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
878 (v_sync_pol << 23);
879
880 crtc->pitch = vxres >> 3;
881
882 crtc->offset = 0;
883 crtc->offset_cntl = 0;
884
885 crtc->vxres = vxres;
886 crtc->vyres = vyres;
887 crtc->xoffset = xoffset;
888 crtc->yoffset = yoffset;
889 crtc->bpp = bpp;
890
891 return 0;
892 }
893
894
895 static int
896 aty128_bpp_to_var(int pix_width, struct fb_var_screeninfo *var)
897 {
898
899 /* fill in pixel info */
900 switch (pix_width) {
901 case CRTC_PIX_WIDTH_8BPP:
902 var->bits_per_pixel = 8;
903 var->red.offset = 0;
904 var->red.length = 8;
905 var->green.offset = 0;
906 var->green.length = 8;
907 var->blue.offset = 0;
908 var->blue.length = 8;
909 var->transp.offset = 0;
910 var->transp.length = 0;
911 break;
912 case CRTC_PIX_WIDTH_15BPP:
913 case CRTC_PIX_WIDTH_16BPP:
914 var->bits_per_pixel = 16;
915 var->red.offset = 10;
916 var->red.length = 5;
917 var->green.offset = 5;
918 var->green.length = 5;
919 var->blue.offset = 0;
920 var->blue.length = 5;
921 var->transp.offset = 0;
922 var->transp.length = 0;
923 break;
924 case CRTC_PIX_WIDTH_24BPP:
925 var->bits_per_pixel = 24;
926 var->red.offset = 16;
927 var->red.length = 8;
928 var->green.offset = 8;
929 var->green.length = 8;
930 var->blue.offset = 0;
931 var->blue.length = 8;
932 var->transp.offset = 0;
933 var->transp.length = 0;
934 break;
935 case CRTC_PIX_WIDTH_32BPP:
936 var->bits_per_pixel = 32;
937 var->red.offset = 16;
938 var->red.length = 8;
939 var->green.offset = 8;
940 var->green.length = 8;
941 var->blue.offset = 0;
942 var->blue.length = 8;
943 var->transp.offset = 24;
944 var->transp.length = 8;
945 break;
946 default:
947 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
948 return -EINVAL;
949 }
950
951 return 0;
952 }
953
954
955 static int
956 aty128_crtc_to_var(const struct aty128_crtc *crtc,
957 struct fb_var_screeninfo *var)
958 {
959 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
960 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
961 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
962 u32 pix_width;
963
964 /* fun with masking */
965 h_total = crtc->h_total & 0x1ff;
966 h_disp = (crtc->h_total >> 16) & 0xff;
967 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
968 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
969 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
970 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
971 v_total = crtc->v_total & 0x7ff;
972 v_disp = (crtc->v_total >> 16) & 0x7ff;
973 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
974 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
975 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
976 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
977 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
978
979 /* do conversions */
980 xres = (h_disp + 1) << 3;
981 yres = v_disp + 1;
982 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
983 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
984 hslen = h_sync_wid << 3;
985 upper = v_total - v_sync_strt - v_sync_wid;
986 lower = v_sync_strt - v_disp;
987 vslen = v_sync_wid;
988 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
989 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
990 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
991
992 aty128_bpp_to_var(pix_width, var);
993
994 var->xres = xres;
995 var->yres = yres;
996 var->xres_virtual = crtc->vxres;
997 var->yres_virtual = crtc->vyres;
998 var->xoffset = crtc->xoffset;
999 var->yoffset = crtc->yoffset;
1000 var->left_margin = left;
1001 var->right_margin = right;
1002 var->upper_margin = upper;
1003 var->lower_margin = lower;
1004 var->hsync_len = hslen;
1005 var->vsync_len = vslen;
1006 var->sync = sync;
1007 var->vmode = FB_VMODE_NONINTERLACED;
1008
1009 return 0;
1010 }
1011
1012 static void
1013 aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info)
1014 {
1015 u32 div3;
1016
1017 unsigned char post_conv[] = /* register values for post dividers */
1018 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1019
1020 /* select PPLL_DIV_3 */
1021 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1022
1023 /* reset PLL */
1024 aty_st_pll(PPLL_CNTL,
1025 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1026
1027 /* write the reference divider */
1028 aty_pll_wait_readupdate(info);
1029 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff);
1030 aty_pll_writeupdate(info);
1031
1032 div3 = aty_ld_pll(PPLL_DIV_3);
1033 div3 &= ~PPLL_FB3_DIV_MASK;
1034 div3 |= pll->feedback_divider;
1035 div3 &= ~PPLL_POST3_DIV_MASK;
1036 div3 |= post_conv[pll->post_divider] << 16;
1037
1038 /* write feedback and post dividers */
1039 aty_pll_wait_readupdate(info);
1040 aty_st_pll(PPLL_DIV_3, div3);
1041 aty_pll_writeupdate(info);
1042
1043 aty_pll_wait_readupdate(info);
1044 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1045 aty_pll_writeupdate(info);
1046
1047 /* clear the reset, just in case */
1048 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1049 }
1050
1051
1052 static int
1053 aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1054 const struct fb_info_aty128 *info)
1055 {
1056 const struct aty128_constants c = info->constants;
1057 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1058 u32 output_freq;
1059 u32 vclk; /* in .01 MHz */
1060 int i;
1061 u32 n, d;
1062
1063 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1064
1065 /* adjust pixel clock if necessary */
1066 if (vclk > c.ppll_max)
1067 vclk = c.ppll_max;
1068 if (vclk * 12 < c.ppll_min)
1069 vclk = c.ppll_min/12;
1070
1071 /* now, find an acceptable divider */
1072 for (i = 0; i < sizeof(post_dividers); i++) {
1073 output_freq = post_dividers[i] * vclk;
1074 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1075 break;
1076 }
1077
1078 /* calculate feedback divider */
1079 n = c.ref_divider * output_freq;
1080 d = c.dotclock;
1081
1082 pll->post_divider = post_dividers[i];
1083 pll->feedback_divider = round_div(n, d);
1084 pll->vclk = vclk;
1085
1086 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1087 "vclk_per: %d\n", pll->post_divider,
1088 pll->feedback_divider, vclk, output_freq,
1089 c.ref_divider, period_in_ps);
1090
1091 return 0;
1092 }
1093
1094
1095 static int
1096 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var,
1097 const struct fb_info_aty128 *info)
1098 {
1099 var->pixclock = 100000000 / pll->vclk;
1100
1101 return 0;
1102 }
1103
1104
1105 static void
1106 aty128_set_fifo(const struct aty128_ddafifo *dsp,
1107 const struct fb_info_aty128 *info)
1108 {
1109 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1110 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1111 }
1112
1113
1114 static int
1115 aty128_ddafifo(struct aty128_ddafifo *dsp,
1116 const struct aty128_pll *pll,
1117 u32 bpp,
1118 const struct fb_info_aty128 *info)
1119 {
1120 const struct aty128_meminfo *m = info->mem;
1121 u32 xclk = info->constants.xclk;
1122 u32 fifo_width = info->constants.fifo_width;
1123 u32 fifo_depth = info->constants.fifo_depth;
1124 s32 x, b, p, ron, roff;
1125 u32 n, d;
1126
1127 /* 15bpp is really 16bpp */
1128 if (bpp == 15)
1129 bpp = 16;
1130
1131 n = xclk * fifo_width;
1132 d = pll->vclk * bpp;
1133 x = round_div(n, d);
1134
1135 ron = 4 * m->MB +
1136 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1137 2 * m->Trp +
1138 m->Twr +
1139 m->CL +
1140 m->Tr2w +
1141 x;
1142
1143 DBG("x %x\n", x);
1144
1145 b = 0;
1146 while (x) {
1147 x >>= 1;
1148 b++;
1149 }
1150 p = b + 1;
1151
1152 ron <<= (11 - p);
1153
1154 n <<= (11 - p);
1155 x = round_div(n, d);
1156 roff = x * (fifo_depth - 4);
1157
1158 if ((ron + m->Rloop) >= roff) {
1159 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1160 return -EINVAL;
1161 }
1162
1163 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1164 p, m->Rloop, x, ron, roff);
1165
1166 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1167 dsp->dda_on_off = ron << 16 | roff;
1168
1169 return 0;
1170 }
1171
1172
1173 /*
1174 * This actually sets the video mode.
1175 */
1176 static void
1177 aty128_set_par(struct aty128fb_par *par,
1178 struct fb_info_aty128 *info)
1179 {
1180 u32 config;
1181
1182 info->current_par = *par;
1183
1184 if (info->blitter_may_be_busy)
1185 wait_for_idle(info);
1186
1187 /* clear all registers that may interfere with mode setting */
1188 aty_st_le32(OVR_CLR, 0);
1189 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1190 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1191 aty_st_le32(OV0_SCALE_CNTL, 0);
1192 aty_st_le32(MPP_TB_CONFIG, 0);
1193 aty_st_le32(MPP_GP_CONFIG, 0);
1194 aty_st_le32(SUBPIC_CNTL, 0);
1195 aty_st_le32(VIPH_CONTROL, 0);
1196 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1197 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1198 aty_st_le32(CAP0_TRIG_CNTL, 0);
1199 aty_st_le32(CAP1_TRIG_CNTL, 0);
1200
1201 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1202
1203 aty128_set_crtc(&par->crtc, info);
1204 aty128_set_pll(&par->pll, info);
1205 aty128_set_fifo(&par->fifo_reg, info);
1206
1207 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1208
1209 #if defined(__BIG_ENDIAN)
1210 if (par->crtc.bpp >= 24)
1211 config |= 2; /* make aperture do 32 byte swapping */
1212 else if (par->crtc.bpp > 8)
1213 config |= 1; /* make aperture do 16 byte swapping */
1214 #endif
1215
1216 aty_st_le32(CONFIG_CNTL, config);
1217 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1218
1219 if (par->accel_flags & FB_ACCELF_TEXT)
1220 aty128_init_engine(par, info);
1221
1222 #ifdef CONFIG_FB_COMPAT_XPMAC
1223 if (!console_fb_info || console_fb_info == &info->fb_info) {
1224 struct fb_var_screeninfo var;
1225 int cmode, vmode;
1226
1227 display_info.height = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1228 display_info.width = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1229 display_info.depth = par->crtc.bpp;
1230 display_info.pitch = (par->crtc.vxres * par->crtc.bpp) >> 3;
1231 aty128_encode_var(&var, par, info);
1232 if (mac_var_to_vmode(&var, &vmode, &cmode))
1233 display_info.mode = 0;
1234 else
1235 display_info.mode = vmode;
1236 strcpy(display_info.name, aty128fb_name);
1237 display_info.fb_address = info->frame_buffer_phys;
1238 display_info.cmap_adr_address = 0;
1239 display_info.cmap_data_address = 0;
1240 display_info.disp_reg_address = info->regbase_phys;
1241 }
1242 #endif /* CONFIG_FB_COMPAT_XPMAC */
1243 }
1244
1245 /*
1246 * encode/decode the User Defined Part of the Display
1247 */
1248
1249 static int
1250 aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par,
1251 const struct fb_info_aty128 *info)
1252 {
1253 int err;
1254
1255 if ((err = aty128_var_to_crtc(var, &par->crtc, info)))
1256 return err;
1257
1258 if ((err = aty128_var_to_pll(var->pixclock, &par->pll, info)))
1259 return err;
1260
1261 if ((err = aty128_ddafifo(&par->fifo_reg, &par->pll, par->crtc.bpp, info)))
1262 return err;
1263
1264 if (var->accel_flags & FB_ACCELF_TEXT)
1265 par->accel_flags = FB_ACCELF_TEXT;
1266 else
1267 par->accel_flags = 0;
1268
1269 return 0;
1270 }
1271
1272
1273 static int
1274 aty128_encode_var(struct fb_var_screeninfo *var,
1275 const struct aty128fb_par *par,
1276 const struct fb_info_aty128 *info)
1277 {
1278 int err;
1279
1280 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1281 return err;
1282
1283 if ((err = aty128_pll_to_var(&par->pll, var, info)))
1284 return err;
1285
1286 var->red.msb_right = 0;
1287 var->green.msb_right = 0;
1288 var->blue.msb_right = 0;
1289 var->transp.msb_right = 0;
1290
1291 var->nonstd = 0;
1292 var->activate = 0;
1293
1294 var->height = -1;
1295 var->width = -1;
1296 var->accel_flags = par->accel_flags;
1297
1298 return 0;
1299 }
1300
1301
1302 /*
1303 * Get the User Defined Part of the Display
1304 */
1305
1306 static int
1307 aty128fb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1308 {
1309 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1310
1311 if (con == -1)
1312 aty128_encode_var(var, &info->default_par, info);
1313 else
1314 *var = fb_display[con].var;
1315 return 0;
1316 }
1317
1318
1319 /*
1320 * Set the User Defined Part of the Display
1321 */
1322
1323 static int
1324 aty128fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1325 {
1326 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1327 struct aty128fb_par par;
1328 struct display *display;
1329 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel;
1330 int accel, err;
1331
1332 display = (con >= 0) ? &fb_display[con] : fb->disp;
1333
1334 /* basic (in)sanity checks */
1335 if (!var->xres)
1336 var->xres = 1;
1337 if (!var->yres)
1338 var->yres = 1;
1339 if (var->xres > var->xres_virtual)
1340 var->xres_virtual = var->xres;
1341 if (var->yres > var->yres_virtual)
1342 var->yres_virtual = var->yres;
1343
1344 switch (var->bits_per_pixel) {
1345 case 0 ... 8:
1346 var->bits_per_pixel = 8;
1347 break;
1348 case 9 ... 16:
1349 var->bits_per_pixel = 16;
1350 break;
1351 case 17 ... 24:
1352 var->bits_per_pixel = 24;
1353 break;
1354 case 25 ... 32:
1355 var->bits_per_pixel = 32;
1356 break;
1357 default:
1358 return -EINVAL;
1359 }
1360
1361 if ((err = aty128_decode_var(var, &par, info)))
1362 return err;
1363
1364 aty128_encode_var(var, &par, info);
1365
1366 if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
1367 return 0;
1368
1369 oldxres = display->var.xres;
1370 oldyres = display->var.yres;
1371 oldvxres = display->var.xres_virtual;
1372 oldvyres = display->var.yres_virtual;
1373 oldbpp = display->var.bits_per_pixel;
1374 oldaccel = display->var.accel_flags;
1375 display->var = *var;
1376 if (oldxres != var->xres || oldyres != var->yres ||
1377 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1378 oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1379
1380 struct fb_fix_screeninfo fix;
1381
1382 aty128_encode_fix(&fix, &par, info);
1383 display->screen_base = (char *)info->frame_buffer;
1384 display->visual = fix.visual;
1385 display->type = fix.type;
1386 display->type_aux = fix.type_aux;
1387 display->ypanstep = fix.ypanstep;
1388 display->ywrapstep = fix.ywrapstep;
1389 display->line_length = fix.line_length;
1390 display->can_soft_blank = 1;
1391 display->inverse = 0;
1392
1393 accel = var->accel_flags & FB_ACCELF_TEXT;
1394 aty128_set_dispsw(display, info, par.crtc.bpp, accel);
1395
1396 if (accel)
1397 display->scrollmode = SCROLL_YNOMOVE;
1398 else
1399 display->scrollmode = SCROLL_YREDRAW;
1400
1401 if (info->fb_info.changevar)
1402 (*info->fb_info.changevar)(con);
1403 }
1404
1405 if (!info->fb_info.display_fg || info->fb_info.display_fg->vc_num == con)
1406 aty128_set_par(&par, info);
1407
1408 if (oldbpp != var->bits_per_pixel) {
1409 if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1410 return err;
1411 do_install_cmap(con, &info->fb_info);
1412 }
1413
1414 return 0;
1415 }
1416
1417
1418 static void
1419 aty128_set_dispsw(struct display *disp,
1420 struct fb_info_aty128 *info, int bpp, int accel)
1421 {
1422 switch (bpp) {
1423 #ifdef FBCON_HAS_CFB8
1424 case 8:
1425 disp->dispsw = accel ? &fbcon_aty128_8 : &fbcon_cfb8;
1426 break;
1427 #endif
1428 #ifdef FBCON_HAS_CFB16
1429 case 15:
1430 case 16:
1431 disp->dispsw = accel ? &fbcon_aty128_16 : &fbcon_cfb16;
1432 disp->dispsw_data = info->fbcon_cmap.cfb16;
1433 break;
1434 #endif
1435 #ifdef FBCON_HAS_CFB24
1436 case 24:
1437 disp->dispsw = accel ? &fbcon_aty128_24 : &fbcon_cfb24;
1438 disp->dispsw_data = info->fbcon_cmap.cfb24;
1439 break;
1440 #endif
1441 #ifdef FBCON_HAS_CFB32
1442 case 32:
1443 disp->dispsw = accel ? &fbcon_aty128_32 : &fbcon_cfb32;
1444 disp->dispsw_data = info->fbcon_cmap.cfb32;
1445 break;
1446 #endif
1447 default:
1448 disp->dispsw = &fbcon_dummy;
1449 }
1450 }
1451
1452
1453 static void
1454 aty128_encode_fix(struct fb_fix_screeninfo *fix,
1455 struct aty128fb_par *par,
1456 const struct fb_info_aty128 *info)
1457 {
1458 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1459
1460 strcpy(fix->id, aty128fb_name);
1461
1462 fix->smem_start = (unsigned long)info->frame_buffer_phys;
1463 fix->mmio_start = (unsigned long)info->regbase_phys;
1464
1465 fix->smem_len = info->vram_size;
1466 fix->mmio_len = 0x1fff;
1467
1468 fix->type = FB_TYPE_PACKED_PIXELS;
1469 fix->type_aux = 0;
1470 fix->line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1471 fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1472 : FB_VISUAL_DIRECTCOLOR;
1473 fix->ywrapstep = 0;
1474 fix->xpanstep = 8;
1475 fix->ypanstep = 1;
1476
1477 fix->accel = FB_ACCEL_ATI_RAGE128;
1478
1479 return;
1480 }
1481
1482
1483 /*
1484 * Get the Fixed Part of the Display
1485 */
1486 static int
1487 aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *fb)
1488 {
1489 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1490 struct aty128fb_par par;
1491
1492 if (con == -1)
1493 par = info->default_par;
1494 else
1495 aty128_decode_var(&fb_display[con].var, &par, info);
1496
1497 aty128_encode_fix(fix, &par, info);
1498
1499 return 0;
1500 }
1501
1502
1503 /*
1504 * Pan or Wrap the Display
1505 *
1506 * Not supported (yet!)
1507 */
1508 static int
1509 aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
1510 struct fb_info *fb)
1511 {
1512 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1513 struct aty128fb_par *par = &info->current_par;
1514 u32 xoffset, yoffset;
1515 u32 offset;
1516 u32 xres, yres;
1517
1518 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1519 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1520
1521 xoffset = (var->xoffset +7) & ~7;
1522 yoffset = var->yoffset;
1523
1524 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1525 return -EINVAL;
1526
1527 par->crtc.xoffset = xoffset;
1528 par->crtc.yoffset = yoffset;
1529
1530 offset = ((yoffset * par->crtc.vxres + xoffset) * par->crtc.bpp) >> 6;
1531
1532 aty_st_le32(CRTC_OFFSET, offset);
1533
1534 return 0;
1535 }
1536
1537
1538 /*
1539 * Get the Colormap
1540 */
1541
1542 static int
1543 aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1544 struct fb_info *info)
1545 {
1546 #if 1
1547 fb_copy_cmap(&info->cmap, cmap, kspc ? 0 : 2);
1548 #else
1549 struct fb_info_aty128 fb = (struct fb_info_aty128 *)info;
1550
1551 if (con == fb->currcon) /* current console? */
1552 return fb_get_cmap(cmap, kspc, aty128_getcolreg, info);
1553 else if (fb_display[con].cmap.len) /* non default colormap? */
1554 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1555 else {
1556 int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 32;
1557 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
1558 }
1559 #endif
1560
1561 return 0;
1562 }
1563
1564 /*
1565 * Set the Colormap
1566 */
1567
1568 static int
1569 aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1570 struct fb_info *info)
1571 {
1572 int err;
1573 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1574 struct display *disp;
1575
1576 if (con >= 0)
1577 disp = &fb_display[con];
1578 else
1579 disp = info->disp;
1580
1581 if (!disp->cmap.len) { /* no colormap allocated? */
1582 int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32;
1583 if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
1584 return err;
1585 }
1586
1587 if (con == fb->currcon) /* current console? */
1588 return fb_set_cmap(cmap, kspc, aty128_setcolreg, info);
1589 else
1590 fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
1591
1592 return 0;
1593 }
1594
1595
1596 static int
1597 aty128fb_rasterimg(struct fb_info *info, int start)
1598 {
1599 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1600
1601 if (fb->blitter_may_be_busy)
1602 wait_for_idle(fb);
1603
1604 return 0;
1605 }
1606
1607
1608 #ifndef MODULE
1609 int __init
1610 aty128fb_setup(char *options)
1611 {
1612 char *this_opt;
1613
1614 if (!options || !*options)
1615 return 0;
1616
1617 for (this_opt = strtok(options, ","); this_opt;
1618 this_opt = strtok(NULL, ",")) {
1619 if (!strncmp(this_opt, "font:", 5)) {
1620 char *p;
1621 int i;
1622
1623 p = this_opt +5;
1624 for (i = 0; i < sizeof(fontname) - 1; i++)
1625 if (!*p || *p == ' ' || *p == ',')
1626 break;
1627 memcpy(fontname, this_opt + 5, i);
1628 fontname[i] = 0;
1629 } else if (!strncmp(this_opt, "noaccel", 7)) {
1630 noaccel = 1;
1631 }
1632 #ifdef CONFIG_MTRR
1633 else if(!strncmp(this_opt, "nomtrr", 6)) {
1634 mtrr = 0;
1635 }
1636 #endif
1637 #ifdef CONFIG_PPC
1638 /* vmode and cmode depreciated */
1639 else if (!strncmp(this_opt, "vmode:", 6)) {
1640 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1641 if (vmode > 0 && vmode <= VMODE_MAX)
1642 default_vmode = vmode;
1643 } else if (!strncmp(this_opt, "cmode:", 6)) {
1644 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1645 switch (cmode) {
1646 case 0:
1647 case 8:
1648 default_cmode = CMODE_8;
1649 break;
1650 case 15:
1651 case 16:
1652 default_cmode = CMODE_16;
1653 break;
1654 case 24:
1655 case 32:
1656 default_cmode = CMODE_32;
1657 break;
1658 }
1659 }
1660 #endif /* CONFIG_PPC */
1661 else
1662 mode_option = this_opt;
1663 }
1664 return 0;
1665 }
1666 #endif /* !MODULE */
1667
1668
1669 /*
1670 * Initialisation
1671 */
1672
1673 static int __init
1674 aty128_init(struct fb_info_aty128 *info, const char *name)
1675 {
1676 struct fb_var_screeninfo var;
1677 u32 dac;
1678 int j, k;
1679 u8 chip_rev;
1680 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1681 char *video_card = "Rage128";
1682
1683 if (!info->vram_size) /* may have already been probed */
1684 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1685
1686 /* Get the chip revision */
1687 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1688
1689 /* put a name with the face */
1690 while (aci->name && info->pdev->device != aci->device) { aci++; }
1691 video_card = (char *)aci->name;
1692 info->chip_gen = aci->chip_gen;
1693
1694 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1695
1696 if (info->vram_size % (1024 * 1024) == 0)
1697 printk("%dM %s\n", info->vram_size / (1024*1024), info->mem->name);
1698 else
1699 printk("%dk %s\n", info->vram_size / 1024, info->mem->name);
1700
1701 /* fill in info */
1702 strcpy(info->fb_info.modename, aty128fb_name);
1703 info->fb_info.node = -1;
1704 info->fb_info.fbops = &aty128fb_ops;
1705 info->fb_info.disp = &info->disp;
1706 strcpy(info->fb_info.fontname, fontname);
1707 info->fb_info.changevar = NULL;
1708 info->fb_info.switch_con = &aty128fbcon_switch;
1709 info->fb_info.updatevar = NULL;
1710 info->fb_info.blank = &aty128fbcon_blank;
1711 info->fb_info.flags = FBINFO_FLAG_DEFAULT;
1712
1713 #ifdef MODULE
1714 var = default_var;
1715 #else
1716 memset(&var, 0, sizeof(var));
1717 #ifdef CONFIG_PPC
1718 if (_machine == _MACH_Pmac) {
1719 if (mode_option) {
1720 if (!mac_find_mode(&var, &info->fb_info, mode_option, 8))
1721 var = default_var;
1722 } else {
1723 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1724 default_vmode = VMODE_1024_768_60;
1725
1726 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1727 default_cmode = CMODE_8;
1728
1729 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1730 var = default_var;
1731 }
1732 } else
1733 #endif /* CONFIG_PPC */
1734 {
1735 if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
1736 &defaultmode, 8) == 0)
1737 var = default_var;
1738 }
1739 #endif /* MODULE */
1740
1741 if (noaccel)
1742 var.accel_flags &= ~FB_ACCELF_TEXT;
1743 else
1744 var.accel_flags |= FB_ACCELF_TEXT;
1745
1746 if (aty128_decode_var(&var, &info->default_par, info)) {
1747 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1748 return 0;
1749 }
1750
1751 /* load up the palette with default colors */
1752 for (j = 0; j < 16; j++) {
1753 k = color_table[j];
1754 info->palette[j].red = default_red[k];
1755 info->palette[j].green = default_grn[k];
1756 info->palette[j].blue = default_blu[k];
1757 }
1758
1759 /* setup the DAC the way we like it */
1760 dac = aty_ld_le32(DAC_CNTL);
1761 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1762 dac |= DAC_MASK;
1763 aty_st_le32(DAC_CNTL, dac);
1764
1765 /* turn off bus mastering, just in case */
1766 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1767
1768 aty128fb_set_var(&var, -1, &info->fb_info);
1769 aty128_init_engine(&info->default_par, info);
1770
1771 board_list = aty128_board_list_add(board_list, info);
1772
1773 if (register_framebuffer(&info->fb_info) < 0)
1774 return 0;
1775
1776 #ifdef CONFIG_PMAC_BACKLIGHT
1777 /* Could be extended to Rage128Pro LVDS output too */
1778 if (info->chip_gen == rage_M3)
1779 register_backlight_controller(&aty128_backlight_controller, info, "ati");
1780 #endif /* CONFIG_PMAC_BACKLIGHT */
1781
1782 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1783 GET_FB_IDX(info->fb_info.node), aty128fb_name, name);
1784
1785 return 1; /* success! */
1786 }
1787
1788
1789 /* add a new card to the list ++ajoshi */
1790 static struct
1791 fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list,
1792 struct fb_info_aty128 *new_node)
1793 {
1794 struct fb_info_aty128 *i_p = board_list;
1795
1796 new_node->next = NULL;
1797 if(board_list == NULL)
1798 return new_node;
1799 while(i_p->next != NULL)
1800 i_p = i_p->next;
1801 i_p->next = new_node;
1802
1803 return board_list;
1804 }
1805
1806
1807 int __init
1808 aty128fb_init(void)
1809 {
1810 #ifdef CONFIG_PCI
1811 struct pci_dev *pdev = NULL;
1812 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1813
1814 while (aci->name != NULL) {
1815 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1816 while (pdev != NULL) {
1817 if (aty128_pci_register(pdev, aci) == 0)
1818 return 0;
1819 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1820 }
1821 aci++;
1822 }
1823 #endif
1824
1825 return 0;
1826 }
1827
1828
1829 #ifdef CONFIG_PCI
1830 /* register a card ++ajoshi */
1831 static int __init
1832 aty128_pci_register(struct pci_dev *pdev,
1833 const struct aty128_chip_info *aci)
1834 {
1835 struct fb_info_aty128 *info = NULL;
1836 u32 fb_addr, reg_addr;
1837 int err;
1838 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1839 char *bios_seg = NULL;
1840 #endif
1841
1842 /* Enable device in PCI config */
1843 if ((err = pci_enable_device(pdev))) {
1844 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
1845 err);
1846 goto err_out;
1847 }
1848
1849 fb_addr = pci_resource_start(pdev, 0);
1850 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
1851 "aty128fb FB")) {
1852 printk(KERN_ERR "aty128fb: cannot reserve frame "
1853 "buffer memory\n");
1854 goto err_free_fb;
1855 }
1856
1857 reg_addr = pci_resource_start(pdev, 2);
1858 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
1859 "aty128fb MMIO")) {
1860 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
1861 goto err_free_mmio;
1862 }
1863
1864 /* We have the resources. Now virtualize them */
1865 if (!(info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC))) {
1866 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
1867 goto err_unmap_out;
1868 }
1869 memset(info, 0, sizeof(struct fb_info_aty128));
1870
1871 /* Copy PCI device info into info->pdev */
1872 info->pdev = pdev;
1873
1874 info->currcon = -1;
1875
1876 /* Virtualize mmio region */
1877 info->regbase_phys = reg_addr;
1878 info->regbase = ioremap(reg_addr, 0x1FFF);
1879
1880 if (!info->regbase)
1881 goto err_free_info;
1882
1883 /* Grab memory size from the card */
1884 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1885
1886 /* Virtualize the framebuffer */
1887 info->frame_buffer_phys = fb_addr;
1888 info->frame_buffer = (u32)ioremap(fb_addr, info->vram_size);
1889
1890 if (!info->frame_buffer) {
1891 iounmap((void *)info->regbase);
1892 goto err_free_info;
1893 }
1894
1895 /* If we can't test scratch registers, something is seriously wrong */
1896 if (!register_test(info)) {
1897 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
1898 goto err_out;
1899 }
1900
1901 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1902 if (!(bios_seg = aty128find_ROM(info)))
1903 printk(KERN_INFO "aty128fb: Rage128 BIOS not located. "
1904 "Guessing...\n");
1905 else {
1906 printk(KERN_INFO "aty128fb: Rage128 BIOS located at "
1907 "segment %4.4X\n", (unsigned int)bios_seg);
1908 aty128_get_pllinfo(info, bios_seg);
1909 }
1910 #endif
1911 aty128_timings(info);
1912
1913 if (!aty128_init(info, "PCI"))
1914 goto err_out;
1915
1916 #ifdef CONFIG_MTRR
1917 if (mtrr) {
1918 info->mtrr.vram = mtrr_add(info->frame_buffer_phys,
1919 info->vram_size, MTRR_TYPE_WRCOMB, 1);
1920 info->mtrr.vram_valid = 1;
1921 /* let there be speed */
1922 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
1923 }
1924 #endif /* CONFIG_MTRR */
1925
1926 #ifdef CONFIG_FB_COMPAT_XPMAC
1927 if (!console_fb_info)
1928 console_fb_info = &info->fb_info;
1929 #endif
1930
1931 return 0;
1932
1933 err_out:
1934 iounmap((void *)info->frame_buffer);
1935 iounmap((void *)info->regbase);
1936 err_free_info:
1937 kfree(info);
1938 err_unmap_out:
1939 release_mem_region(pci_resource_start(pdev, 2),
1940 pci_resource_len(pdev, 2));
1941 err_free_mmio:
1942 release_mem_region(pci_resource_start(pdev, 0),
1943 pci_resource_len(pdev, 0));
1944 err_free_fb:
1945 release_mem_region(pci_resource_start(pdev, 1),
1946 pci_resource_len(pdev, 1));
1947 return -ENODEV;
1948 }
1949 #endif /* CONFIG_PCI */
1950
1951
1952 /* PPC and Sparc cannot read video ROM */
1953 #if !defined(CONFIG_PPC) && !defined(__sparc__)
1954 static char __init
1955 *aty128find_ROM(struct fb_info_aty128 *info)
1956 {
1957 u32 segstart;
1958 char *rom_base;
1959 char *rom;
1960 int stage;
1961 int i;
1962 char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */
1963 char R128_sig[] = "R128"; /* Rage128 ROM identifier */
1964
1965 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
1966 stage = 1;
1967
1968 rom_base = (char *)ioremap(segstart, 0x1000);
1969
1970 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
1971 stage = 2;
1972
1973 if (stage != 2) {
1974 iounmap(rom_base);
1975 continue;
1976 }
1977 rom = rom_base;
1978
1979 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
1980 if (aty_rom_sig[0] == *rom)
1981 if (strncmp(aty_rom_sig, rom,
1982 strlen(aty_rom_sig)) == 0)
1983 stage = 3;
1984 rom++;
1985 }
1986 if (stage != 3) {
1987 iounmap(rom_base);
1988 continue;
1989 }
1990 rom = rom_base;
1991
1992 /* ATI signature found. Let's see if it's a Rage128 */
1993 for (i = 0; (i < 512) && (stage != 4); i++) {
1994 if (R128_sig[0] == *rom)
1995 if (strncmp(R128_sig, rom,
1996 strlen(R128_sig)) == 0)
1997 stage = 4;
1998 rom++;
1999 }
2000 if (stage != 4) {
2001 iounmap(rom_base);
2002 continue;
2003 }
2004
2005 return rom_base;
2006 }
2007
2008 return NULL;
2009 }
2010
2011
2012 static void __init
2013 aty128_get_pllinfo(struct fb_info_aty128 *info, char *bios_seg)
2014 {
2015 void *bios_header;
2016 void *header_ptr;
2017 u16 bios_header_offset, pll_info_offset;
2018 PLL_BLOCK pll;
2019
2020 bios_header = bios_seg + 0x48L;
2021 header_ptr = bios_header;
2022
2023 bios_header_offset = readw(header_ptr);
2024 bios_header = bios_seg + bios_header_offset;
2025 bios_header += 0x30;
2026
2027 header_ptr = bios_header;
2028 pll_info_offset = readw(header_ptr);
2029 header_ptr = bios_seg + pll_info_offset;
2030
2031 memcpy_fromio(&pll, header_ptr, 50);
2032
2033 info->constants.ppll_max = pll.PCLK_max_freq;
2034 info->constants.ppll_min = pll.PCLK_min_freq;
2035 info->constants.xclk = (u32)pll.XCLK;
2036 info->constants.ref_divider = (u32)pll.PCLK_ref_divider;
2037 info->constants.dotclock = (u32)pll.PCLK_ref_freq;
2038
2039 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d dotclock %d\n",
2040 info->constants.ppll_max, info->constants.ppll_min,
2041 info->constants.xclk, info->constants.ref_divider,
2042 info->constants.dotclock);
2043
2044 }
2045 #endif /* !CONFIG_PPC */
2046
2047
2048 /* fill in known card constants if pll_block is not available */
2049 static void __init
2050 aty128_timings(struct fb_info_aty128 *info)
2051 {
2052 #ifdef CONFIG_PPC
2053 /* instead of a table lookup, assume OF has properly
2054 * setup the PLL registers and use their values
2055 * to set the XCLK values and reference divider values */
2056
2057 u32 x_mpll_ref_fb_div;
2058 u32 xclk_cntl;
2059 u32 Nx, M;
2060 unsigned PostDivSet[] =
2061 { 0, 1, 2, 4, 8, 3, 6, 12 };
2062 #endif
2063
2064 if (!info->constants.dotclock)
2065 info->constants.dotclock = 2950;
2066
2067 #ifdef CONFIG_PPC
2068 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
2069 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
2070 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
2071 M = x_mpll_ref_fb_div & 0x0000ff;
2072
2073 info->constants.xclk = round_div((2 * Nx *
2074 info->constants.dotclock), (M * PostDivSet[xclk_cntl]));
2075
2076 info->constants.ref_divider =
2077 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
2078 #endif
2079
2080 if (!info->constants.ref_divider) {
2081 info->constants.ref_divider = 0x3b;
2082
2083 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
2084 aty_pll_writeupdate(info);
2085 }
2086 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
2087 aty_pll_writeupdate(info);
2088
2089 /* from documentation */
2090 if (!info->constants.ppll_min)
2091 info->constants.ppll_min = 12500;
2092 if (!info->constants.ppll_max)
2093 info->constants.ppll_max = 25000; /* 23000 on some cards? */
2094 if (!info->constants.xclk)
2095 info->constants.xclk = 0x1d4d; /* same as mclk */
2096
2097 info->constants.fifo_width = 128;
2098 info->constants.fifo_depth = 32;
2099
2100 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
2101 case 0:
2102 info->mem = &sdr_128;
2103 break;
2104 case 1:
2105 info->mem = &sdr_sgram;
2106 break;
2107 case 2:
2108 info->mem = &ddr_sgram;
2109 break;
2110 default:
2111 info->mem = &sdr_sgram;
2112 }
2113 }
2114
2115
2116 static int
2117 aty128fbcon_switch(int con, struct fb_info *fb)
2118 {
2119 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2120 struct aty128fb_par par;
2121
2122 /* Do we have to save the colormap? */
2123 if (fb_display[info->currcon].cmap.len)
2124 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
2125 aty128_getcolreg, fb);
2126
2127 /* set the current console */
2128 info->currcon = con;
2129
2130 aty128_decode_var(&fb_display[con].var, &par, info);
2131 aty128_set_par(&par, info);
2132
2133 aty128_set_dispsw(&fb_display[con], info, par.crtc.bpp,
2134 par.accel_flags & FB_ACCELF_TEXT);
2135
2136 do_install_cmap(con, fb);
2137
2138 return 1;
2139 }
2140
2141
2142 /*
2143 * Blank the display.
2144 */
2145 static void
2146 aty128fbcon_blank(int blank, struct fb_info *fb)
2147 {
2148 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2149 u8 state = 0;
2150
2151 #ifdef CONFIG_PMAC_BACKLIGHT
2152 if ((_machine == _MACH_Pmac) && blank)
2153 set_backlight_enable(0);
2154 #endif /* CONFIG_PMAC_BACKLIGHT */
2155
2156 if (blank & VESA_VSYNC_SUSPEND)
2157 state |= 2;
2158 if (blank & VESA_HSYNC_SUSPEND)
2159 state |= 1;
2160 if (blank & VESA_POWERDOWN)
2161 state |= 4;
2162
2163 aty_st_8(CRTC_EXT_CNTL+1, state);
2164
2165 #ifdef CONFIG_PMAC_BACKLIGHT
2166 if ((_machine == _MACH_Pmac) && !blank)
2167 set_backlight_enable(1);
2168 #endif /* CONFIG_PMAC_BACKLIGHT */
2169 }
2170
2171
2172 /*
2173 * Read a single color register and split it into
2174 * colors/transparent. Return != 0 for invalid regno.
2175 */
2176 static int
2177 aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
2178 u_int *transp, struct fb_info *fb)
2179 {
2180 struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
2181
2182 if (regno > 255)
2183 return 1;
2184
2185 *red = (info->palette[regno].red<<8) | info->palette[regno].red;
2186 *green = (info->palette[regno].green<<8) | info->palette[regno].green;
2187 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
2188 *transp = 0;
2189
2190 return 0;
2191 }
2192
2193 /*
2194 * Set a single color register. The values supplied are already
2195 * rounded down to the hardware's capabilities (according to the
2196 * entries in the var structure). Return != 0 for invalid regno.
2197 */
2198 static int
2199 aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2200 u_int transp, struct fb_info *fb)
2201 {
2202 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2203 u32 col;
2204
2205 if (regno > 255)
2206 return 1;
2207
2208 red >>= 8;
2209 green >>= 8;
2210 blue >>= 8;
2211 info->palette[regno].red = red;
2212 info->palette[regno].green = green;
2213 info->palette[regno].blue = blue;
2214
2215 /* Note: For now, on M3, we set palette on both heads, which may
2216 * be useless. Can someone with a M3 check this ? */
2217
2218 /* initialize gamma ramp for hi-color+ */
2219
2220 if ((info->current_par.crtc.bpp > 8) && (regno == 0)) {
2221 int i;
2222
2223 if (info->chip_gen == rage_M3)
2224 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
2225
2226 for (i=16; i<256; i++) {
2227 aty_st_8(PALETTE_INDEX, i);
2228 col = (i << 16) | (i << 8) | i;
2229 aty_st_le32(PALETTE_DATA, col);
2230 }
2231
2232 if (info->chip_gen == rage_M3) {
2233 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
2234
2235 for (i=16; i<256; i++) {
2236 aty_st_8(PALETTE_INDEX, i);
2237 col = (i << 16) | (i << 8) | i;
2238 aty_st_le32(PALETTE_DATA, col);
2239 }
2240 }
2241 }
2242
2243 /* initialize palette */
2244
2245 if (info->chip_gen == rage_M3)
2246 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
2247
2248 if (info->current_par.crtc.bpp == 16)
2249 aty_st_8(PALETTE_INDEX, (regno << 3));
2250 else
2251 aty_st_8(PALETTE_INDEX, regno);
2252 col = (red << 16) | (green << 8) | blue;
2253 aty_st_le32(PALETTE_DATA, col);
2254 if (info->chip_gen == rage_M3) {
2255 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
2256 if (info->current_par.crtc.bpp == 16)
2257 aty_st_8(PALETTE_INDEX, (regno << 3));
2258 else
2259 aty_st_8(PALETTE_INDEX, regno);
2260 aty_st_le32(PALETTE_DATA, col);
2261 }
2262
2263 if (regno < 16)
2264 switch (info->current_par.crtc.bpp) {
2265 #ifdef FBCON_HAS_CFB16
2266 case 9 ... 16:
2267 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2268 regno;
2269 break;
2270 #endif
2271 #ifdef FBCON_HAS_CFB24
2272 case 17 ... 24:
2273 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
2274 regno;
2275 break;
2276 #endif
2277 #ifdef FBCON_HAS_CFB32
2278 case 25 ... 32: {
2279 u32 i;
2280
2281 i = (regno << 8) | regno;
2282 info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
2283 break;
2284 }
2285 #endif
2286 }
2287 return 0;
2288 }
2289
2290
2291 static void
2292 do_install_cmap(int con, struct fb_info *info)
2293 {
2294 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
2295
2296 if (con != fb->currcon)
2297 return;
2298
2299 if (fb_display[con].cmap.len)
2300 fb_set_cmap(&fb_display[con].cmap, 1, aty128_setcolreg, info);
2301 else {
2302 int size = (fb_display[con].var.bits_per_pixel <= 8) ? 256 : 16;
2303 fb_set_cmap(fb_default_cmap(size), 1, aty128_setcolreg, info);
2304 }
2305 }
2306
2307
2308 #ifdef CONFIG_PMAC_BACKLIGHT
2309 static int backlight_conv[] = {
2310 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2311 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2312 };
2313
2314 static int
2315 aty128_set_backlight_enable(int on, int level, void* data)
2316 {
2317 struct fb_info_aty128 *info = (struct fb_info_aty128 *)data;
2318 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2319
2320 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2321 if (on && level > BACKLIGHT_OFF) {
2322 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2323 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2324 } else {
2325 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2326 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2327 }
2328 aty_st_le32(LVDS_GEN_CNTL, reg);
2329
2330 return 0;
2331 }
2332
2333 static int
2334 aty128_set_backlight_level(int level, void* data)
2335 {
2336 return aty128_set_backlight_enable(1, level, data);
2337 }
2338 #endif /* CONFIG_PMAC_BACKLIGHT */
2339
2340 /*
2341 * Accelerated functions
2342 */
2343
2344 static inline void
2345 aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2346 u_int width, u_int height,
2347 struct fb_info_aty128 *info)
2348 {
2349 u32 save_dp_datatype, save_dp_cntl, bppval;
2350
2351 if (!width || !height)
2352 return;
2353
2354 bppval = bpp_to_depth(info->current_par.crtc.bpp);
2355 if (bppval == DST_24BPP) {
2356 srcx *= 3;
2357 dstx *= 3;
2358 width *= 3;
2359 } else if (bppval == -EINVAL) {
2360 printk("aty128fb: invalid depth\n");
2361 return;
2362 }
2363
2364 wait_for_fifo(2, info);
2365 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2366 save_dp_cntl = aty_ld_le32(DP_CNTL);
2367
2368 wait_for_fifo(6, info);
2369 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2370 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2371 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2372 aty_st_le32(DP_DATATYPE, save_dp_datatype | bppval | SRC_DSTCOLOR);
2373
2374 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2375 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2376
2377 info->blitter_may_be_busy = 1;
2378
2379 wait_for_fifo(2, info);
2380 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2381 aty_st_le32(DP_CNTL, save_dp_cntl);
2382 }
2383
2384
2385 /*
2386 * Text mode accelerated functions
2387 */
2388
2389 static void
2390 fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2391 int height, int width)
2392 {
2393 sx *= fontwidth(p);
2394 sy *= fontheight(p);
2395 dx *= fontwidth(p);
2396 dy *= fontheight(p);
2397 width *= fontwidth(p);
2398 height *= fontheight(p);
2399
2400 aty128_rectcopy(sx, sy, dx, dy, width, height,
2401 (struct fb_info_aty128 *)p->fb_info);
2402 }
2403
2404
2405 #ifdef FBCON_HAS_CFB8
2406 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
2407 int c, int yy, int xx)
2408 {
2409 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2410
2411 if (fb->blitter_may_be_busy)
2412 wait_for_idle(fb);
2413
2414 fbcon_cfb8_putc(conp, p, c, yy, xx);
2415 }
2416
2417
2418 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
2419 const unsigned short *s, int count,
2420 int yy, int xx)
2421 {
2422 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2423
2424 if (fb->blitter_may_be_busy)
2425 wait_for_idle(fb);
2426
2427 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
2428 }
2429
2430
2431 static void fbcon_aty8_clear_margins(struct vc_data *conp,
2432 struct display *p, int bottom_only)
2433 {
2434 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2435
2436 if (fb->blitter_may_be_busy)
2437 wait_for_idle(fb);
2438
2439 fbcon_cfb8_clear_margins(conp, p, bottom_only);
2440 }
2441
2442 static struct display_switch fbcon_aty128_8 = {
2443 setup: fbcon_cfb8_setup,
2444 bmove: fbcon_aty128_bmove,
2445 clear: fbcon_cfb8_clear,
2446 putc: fbcon_aty8_putc,
2447 putcs: fbcon_aty8_putcs,
2448 revc: fbcon_cfb8_revc,
2449 clear_margins: fbcon_aty8_clear_margins,
2450 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2451 };
2452 #endif
2453 #ifdef FBCON_HAS_CFB16
2454 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
2455 int c, int yy, int xx)
2456 {
2457 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2458
2459 if (fb->blitter_may_be_busy)
2460 wait_for_idle(fb);
2461
2462 fbcon_cfb16_putc(conp, p, c, yy, xx);
2463 }
2464
2465
2466 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
2467 const unsigned short *s, int count,
2468 int yy, int xx)
2469 {
2470 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2471
2472 if (fb->blitter_may_be_busy)
2473 wait_for_idle(fb);
2474
2475 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
2476 }
2477
2478
2479 static void fbcon_aty16_clear_margins(struct vc_data *conp,
2480 struct display *p, int bottom_only)
2481 {
2482 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2483
2484 if (fb->blitter_may_be_busy)
2485 wait_for_idle(fb);
2486
2487 fbcon_cfb16_clear_margins(conp, p, bottom_only);
2488 }
2489
2490 static struct display_switch fbcon_aty128_16 = {
2491 setup: fbcon_cfb16_setup,
2492 bmove: fbcon_aty128_bmove,
2493 clear: fbcon_cfb16_clear,
2494 putc: fbcon_aty16_putc,
2495 putcs: fbcon_aty16_putcs,
2496 revc: fbcon_cfb16_revc,
2497 clear_margins: fbcon_aty16_clear_margins,
2498 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2499 };
2500 #endif
2501 #ifdef FBCON_HAS_CFB24
2502 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
2503 int c, int yy, int xx)
2504 {
2505 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2506
2507 if (fb->blitter_may_be_busy)
2508 wait_for_idle(fb);
2509
2510 fbcon_cfb24_putc(conp, p, c, yy, xx);
2511 }
2512
2513
2514 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
2515 const unsigned short *s, int count,
2516 int yy, int xx)
2517 {
2518 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2519
2520 if (fb->blitter_may_be_busy)
2521 wait_for_idle(fb);
2522
2523 fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
2524 }
2525
2526
2527 static void fbcon_aty24_clear_margins(struct vc_data *conp,
2528 struct display *p, int bottom_only)
2529 {
2530 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2531
2532 if (fb->blitter_may_be_busy)
2533 wait_for_idle(fb);
2534
2535 fbcon_cfb24_clear_margins(conp, p, bottom_only);
2536 }
2537
2538 static struct display_switch fbcon_aty128_24 = {
2539 setup: fbcon_cfb24_setup,
2540 bmove: fbcon_aty128_bmove,
2541 clear: fbcon_cfb24_clear,
2542 putc: fbcon_aty24_putc,
2543 putcs: fbcon_aty24_putcs,
2544 revc: fbcon_cfb24_revc,
2545 clear_margins: fbcon_aty24_clear_margins,
2546 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2547 };
2548 #endif
2549 #ifdef FBCON_HAS_CFB32
2550 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
2551 int c, int yy, int xx)
2552 {
2553 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2554
2555 if (fb->blitter_may_be_busy)
2556 wait_for_idle(fb);
2557
2558 fbcon_cfb32_putc(conp, p, c, yy, xx);
2559 }
2560
2561
2562 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
2563 const unsigned short *s, int count,
2564 int yy, int xx)
2565 {
2566 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2567
2568 if (fb->blitter_may_be_busy)
2569 wait_for_idle(fb);
2570
2571 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2572 }
2573
2574
2575 static void fbcon_aty32_clear_margins(struct vc_data *conp,
2576 struct display *p, int bottom_only)
2577 {
2578 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2579
2580 if (fb->blitter_may_be_busy)
2581 wait_for_idle(fb);
2582
2583 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2584 }
2585
2586 static struct display_switch fbcon_aty128_32 = {
2587 setup: fbcon_cfb32_setup,
2588 bmove: fbcon_aty128_bmove,
2589 clear: fbcon_cfb32_clear,
2590 putc: fbcon_aty32_putc,
2591 putcs: fbcon_aty32_putcs,
2592 revc: fbcon_cfb32_revc,
2593 clear_margins: fbcon_aty32_clear_margins,
2594 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2595 };
2596 #endif
2597
2598 #ifdef MODULE
2599 MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>");
2600 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2601
2602 int __init
2603 init_module(void)
2604 {
2605 aty128fb_init();
2606 return 0;
2607 }
2608
2609 void __exit
2610 cleanup_module(void)
2611 {
2612 struct fb_info_aty128 *info = board_list;
2613
2614 while (board_list) {
2615 info = board_list;
2616 board_list = board_list->next;
2617
2618 unregister_framebuffer(&info->fb_info);
2619 #ifdef CONFIG_MTRR
2620 if (info->mtrr.vram_valid)
2621 mtrr_del(info->mtrr.vram, info->frame_buffer_phys,
2622 info->vram_size);
2623 #endif /* CONFIG_MTRR */
2624 iounmap(info->regbase);
2625 iounmap(&info->frame_buffer);
2626
2627 release_mem_region(pci_resource_start(info->pdev, 0),
2628 pci_resource_len(info->pdev, 0));
2629 release_mem_region(pci_resource_start(info->pdev, 1),
2630 pci_resource_len(info->pdev, 1));
2631 release_mem_region(pci_resource_start(info->pdev, 2),
2632 pci_resource_len(info->pdev, 2));
2633
2634 kfree(info);
2635 }
2636 }
2637 #endif /* MODULE */
2638
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