1 /*
2 * linux/drivers/video/cyber2000fb.h
3 *
4 * Copyright (C) 1998-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Integraphics Cyber2000 frame buffer device
11 */
12 #include <linux/config.h>
13
14 #define cyber2000_outb(dat,reg) writeb(dat, CyberRegs + reg)
15 #define cyber2000_outw(dat,reg) writew(dat, CyberRegs + reg)
16 #define cyber2000_outl(dat,reg) writel(dat, CyberRegs + reg)
17
18 #define cyber2000_inb(reg) readb(CyberRegs + reg)
19 #define cyber2000_inw(reg) readw(CyberRegs + reg)
20 #define cyber2000_inl(reg) readl(CyberRegs + reg)
21
22 /*
23 * Internal CyberPro sizes and offsets.
24 */
25 #define MMIO_OFFSET 0x00800000
26 #define MMIO_SIZE 0x000c0000
27
28 #define NR_PALETTE 256
29
30 #if defined(DEBUG) && defined(CONFIG_DEBUG_LL)
31 static void debug_printf(char *fmt, ...)
32 {
33 char buffer[128];
34 va_list ap;
35
36 va_start(ap, fmt);
37 vsprintf(buffer, fmt, ap);
38 va_end(ap);
39
40 printascii(buffer);
41 }
42 #else
43 #define debug_printf(x...) do { } while (0)
44 #endif
45
46 static inline void cyber2000_crtcw(int reg, int val)
47 {
48 cyber2000_outb(reg, 0x3d4);
49 cyber2000_outb(val, 0x3d5);
50 }
51
52 static inline void cyber2000_grphw(int reg, int val)
53 {
54 cyber2000_outb(reg, 0x3ce);
55 cyber2000_outb(val, 0x3cf);
56 }
57
58 static inline unsigned int cyber2000_grphr(int reg)
59 {
60 cyber2000_outb(reg, 0x3ce);
61 return cyber2000_inb(0x3cf);
62 }
63
64 static inline void cyber2000_attrw(int reg, int val)
65 {
66 cyber2000_inb(0x3da);
67 cyber2000_outb(reg, 0x3c0);
68 cyber2000_inb(0x3c1);
69 cyber2000_outb(val, 0x3c0);
70 }
71
72 static inline void cyber2000_seqw(int reg, int val)
73 {
74 cyber2000_outb(reg, 0x3c4);
75 cyber2000_outb(val, 0x3c5);
76 }
77
78 #define PIXFORMAT_8BPP 0
79 #define PIXFORMAT_16BPP 1
80 #define PIXFORMAT_24BPP 2
81
82 #define VISUALID_256 1
83 #define VISUALID_64K 2
84 #define VISUALID_16M 4
85 #define VISUALID_32K 6
86
87 #define FUNC_CTL 0x3c
88 #define FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */
89
90 #define BIU_BM_CONTROL 0x3e
91 #define BIU_BM_CONTROL_ENABLE 0x01 /* enable bus-master */
92 #define BIU_BM_CONTROL_BURST 0x02 /* enable burst */
93 #define BIU_BM_CONTROL_BACK2BACK 0x04 /* enable back to back */
94
95 #define X_V2_VID_MEM_START 0x40
96 #define X_V2_VID_SRC_WIDTH 0x43
97 #define X_V2_X_START 0x45
98 #define X_V2_X_END 0x47
99 #define X_V2_Y_START 0x49
100 #define X_V2_Y_END 0x4b
101 #define X_V2_VID_SRC_WIN_WIDTH 0x4d
102
103 #define Y_V2_DDA_X_INC 0x43
104 #define Y_V2_DDA_Y_INC 0x47
105 #define Y_V2_VID_FIFO_CTL 0x49
106 #define Y_V2_VID_FMT 0x4b
107 #define Y_V2_VID_DISP_CTL1 0x4c
108 #define Y_V2_VID_FIFO_CTL1 0x4d
109
110 #define J_X2_VID_MEM_START 0x40
111 #define J_X2_VID_SRC_WIDTH 0x43
112 #define J_X2_X_START 0x47
113 #define J_X2_X_END 0x49
114 #define J_X2_Y_START 0x4b
115 #define J_X2_Y_END 0x4d
116 #define J_X2_VID_SRC_WIN_WIDTH 0x4f
117
118 #define K_X2_DDA_X_INIT 0x40
119 #define K_X2_DDA_X_INC 0x42
120 #define K_X2_DDA_Y_INIT 0x44
121 #define K_X2_DDA_Y_INC 0x46
122 #define K_X2_VID_FMT 0x48
123 #define K_X2_VID_DISP_CTL1 0x49
124
125 #define K_CAP_X2_CTL1 0x49
126
127 #define CAP_X_START 0x60
128 #define CAP_X_END 0x62
129 #define CAP_Y_START 0x64
130 #define CAP_Y_END 0x66
131 #define CAP_DDA_X_INIT 0x68
132 #define CAP_DDA_X_INC 0x6a
133 #define CAP_DDA_Y_INIT 0x6c
134 #define CAP_DDA_Y_INC 0x6e
135
136 #define MEM_CTL1 0x71
137
138 #define MEM_CTL2 0x72
139 #define MEM_CTL2_SIZE_2MB 0x01
140 #define MEM_CTL2_SIZE_4MB 0x02
141 #define MEM_CTL2_SIZE_MASK 0x03
142 #define MEM_CTL2_64BIT 0x04
143
144 #define EXT_FIFO_CTL 0x74
145
146 #define CAP_PIP_X_START 0x80
147 #define CAP_PIP_X_END 0x82
148 #define CAP_PIP_Y_START 0x84
149 #define CAP_PIP_Y_END 0x86
150
151 #define CAP_NEW_CTL1 0x88
152
153 #define CAP_NEW_CTL2 0x89
154
155 #define BM_CTRL0 0x9c
156 #define BM_CTRL1 0x9d
157
158 #define CAP_MODE1 0xa4
159 #define CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
160 #define CAP_MODE1_CCIR656 0x02 /* CCIR656 mode */
161 #define CAP_MODE1_IGNOREVGT 0x04 /* ignore VGT */
162 #define CAP_MODE1_ALTFIFO 0x10 /* use alternate FIFO for capture */
163 #define CAP_MODE1_SWAPUV 0x20 /* swap UV bytes */
164 #define CAP_MODE1_MIRRORY 0x40 /* mirror vertically */
165 #define CAP_MODE1_MIRRORX 0x80 /* mirror horizontally */
166
167 #define DCLK_MULT 0xb0
168 #define DCLK_DIV 0xb1
169 #define MCLK_MULT 0xb2
170 #define MCLK_DIV 0xb3
171
172 #define CAP_MODE2 0xa5
173
174 #define Y_TV_CTL 0xae
175
176 #define EXT_MEM_START 0xc0 /* ext start address 21 bits */
177 #define HOR_PHASE_SHIFT 0xc2 /* high 3 bits */
178 #define EXT_SRC_WIDTH 0xc3 /* ext offset phase 10 bits */
179 #define EXT_SRC_HEIGHT 0xc4 /* high 6 bits */
180 #define EXT_X_START 0xc5 /* ext->screen, 16 bits */
181 #define EXT_X_END 0xc7 /* ext->screen, 16 bits */
182 #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
183 #define EXT_Y_END 0xcb /* ext->screen, 16 bits */
184 #define EXT_SRC_WIN_WIDTH 0xcd /* 8 bits */
185 #define EXT_COLOUR_COMPARE 0xce /* 24 bits */
186 #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
187 #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
188 #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
189 #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
190
191 #define EXT_VID_FIFO_CTL 0xd9
192
193 #define EXT_VID_FMT 0xdb
194 #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
195 #define EXT_VID_FMT_RGB555 0x01
196 #define EXT_VID_FMT_RGB565 0x02
197 #define EXT_VID_FMT_RGB888_24 0x03
198 #define EXT_VID_FMT_RGB888_32 0x04
199 #define EXT_VID_FMT_DUP_PIX_ZOON 0x08 /* duplicate pixel zoom */
200 #define EXT_VID_FMT_MOD_3RD_PIX 0x20 /* modify 3rd duplicated pixel */
201 #define EXT_VID_FMT_DBL_H_PIX 0x40 /* double horiz pixels */
202 #define EXT_VID_FMT_UV128 0x80 /* UV data offset by 128 */
203
204 #define EXT_VID_DISP_CTL1 0xdc
205 #define EXT_VID_DISP_CTL1_INTRAM 0x01 /* video pixels go to internal RAM */
206 #define EXT_VID_DISP_CTL1_IGNORE_CCOMP 0x02 /* ignore colour compare registers */
207 #define EXT_VID_DISP_CTL1_NOCLIP 0x04 /* do not clip to 16235,16240 */
208 #define EXT_VID_DISP_CTL1_UV_AVG 0x08 /* U/V data is averaged */
209 #define EXT_VID_DISP_CTL1_Y128 0x10 /* Y data offset by 128 */
210 #define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20 /* vertical interpolation off */
211 #define EXT_VID_DISP_CTL1_FULL_WIN 0x40 /* video out window full */
212 #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */
213
214 #define EXT_VID_FIFO_CTL1 0xdd
215
216 #define VFAC_CTL1 0xe8
217 #define VFAC_CTL1_CAPTURE 0x01 /* capture enable */
218 #define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */
219 #define VFAC_CTL1_FREEZE_CAPTURE 0x04 /* freeze capture */
220 #define VFAC_CTL1_FREEZE_CAPTURE_SYNC 0x08 /* sync freeze capture */
221 #define VFAC_CTL1_VALIDFRAME_SRC 0x10 /* select valid frame source */
222 #define VFAC_CTL1_PHILIPS 0x40 /* select Philips mode */
223 #define VFAC_CTL1_MODVINTERPOLCLK 0x80 /* modify vertical interpolation clocl */
224
225 #define VFAC_CTL2 0xe9
226 #define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */
227 #define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */
228 #define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */
229 #define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */
230 #define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */
231 #define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */
232 #define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */
233 #define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */
234
235 #define VFAC_CTL3 0xea
236 #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
237
238 #define CAP_MEM_START 0xeb /* 18 bits */
239 #define CAP_MAP_WIDTH 0xed /* high 6 bits */
240 #define CAP_PITCH 0xee /* 8 bits */
241
242 #define CAP_CTL_MISC 0xef
243 #define CAP_CTL_MISC_HDIV 0x01
244 #define CAP_CTL_MISC_HDIV4 0x02
245 #define CAP_CTL_MISC_ODDEVEN 0x04
246 #define CAP_CTL_MISC_HSYNCDIV2 0x08
247 #define CAP_CTL_MISC_SYNCTZHIGH 0x10
248 #define CAP_CTL_MISC_SYNCTZOR 0x20
249 #define CAP_CTL_MISC_DISPUSED 0x80
250
251 #define REG_BANK 0xfa
252 #define REG_BANK_X 0x00
253 #define REG_BANK_Y 0x01
254 #define REG_BANK_W 0x02
255 #define REG_BANK_T 0x03
256 #define REG_BANK_J 0x04
257 #define REG_BANK_K 0x05
258
259 /*
260 * Bus-master
261 */
262 #define BM_VID_ADDR_LOW 0xbc040
263 #define BM_VID_ADDR_HIGH 0xbc044
264 #define BM_ADDRESS_LOW 0xbc080
265 #define BM_ADDRESS_HIGH 0xbc084
266 #define BM_LENGTH 0xbc088
267 #define BM_CONTROL 0xbc08c
268 #define BM_CONTROL_ENABLE 0x01 /* enable transfer */
269 #define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */
270 #define BM_CONTROL_INIT 0x04 /* initialise status & count */
271 #define BM_COUNT 0xbc090 /* read-only */
272
273 /*
274 * Graphics Co-processor
275 */
276 #define CO_CMD_L_PATTERN_FGCOL 0x8000
277 #define CO_CMD_L_INC_LEFT 0x0004
278 #define CO_CMD_L_INC_UP 0x0002
279
280 #define CO_CMD_H_SRC_PIXMAP 0x2000
281 #define CO_CMD_H_BLITTER 0x0800
282
283 #define CO_REG_CONTROL 0xbf011
284 #define CO_REG_SRC_WIDTH 0xbf018
285 #define CO_REG_PIX_FORMAT 0xbf01c
286 #define CO_REG_FORE_MIX 0xbf048
287 #define CO_REG_FOREGROUND 0xbf058
288 #define CO_REG_WIDTH 0xbf060
289 #define CO_REG_HEIGHT 0xbf062
290 #define CO_REG_X_PHASE 0xbf078
291 #define CO_REG_CMD_L 0xbf07c
292 #define CO_REG_CMD_H 0xbf07e
293 #define CO_REG_SRC_PTR 0xbf170
294 #define CO_REG_DEST_PTR 0xbf178
295 #define CO_REG_DEST_WIDTH 0xbf218
296
297 /*
298 * Private structure
299 */
300 struct cfb_info;
301
302 struct cyberpro_info {
303 struct pci_dev *dev;
304 unsigned char *regs;
305 char *fb;
306 char dev_name[32];
307 unsigned int fb_size;
308
309 /*
310 * The following is a pointer to be passed into the
311 * functions below. The modules outside the main
312 * cyber2000fb.c driver have no knowledge as to what
313 * is within this structure.
314 */
315 struct cfb_info *info;
316
317 /*
318 * Use these to enable the BM or TV registers. In an SMP
319 * environment, these two function pointers should only be
320 * called from the module_init() or module_exit()
321 * functions.
322 */
323 void (*enable_extregs)(struct cfb_info *);
324 void (*disable_extregs)(struct cfb_info *);
325 };
326
327 /*
328 * Note! Writing to the Cyber20x0 registers from an interrupt
329 * routine is definitely a bad idea atm.
330 */
331 int cyber2000fb_attach(struct cyberpro_info *info, int idx);
332 void cyber2000fb_detach(int idx);
333
334
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