1 /*
2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
3 *
4 * This file is derived from the powermac console "imstt" driver:
5 * Copyright (C) 1997 Sigurdur Asgeirsson
6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
7 * Modified by Danilo Beuche 1998
8 * Some register values added by Damien Doligez, INRIA Rocquencourt
9 *
10 * This file was written by Ryan Nielsen (ran@krazynet.com)
11 * Most of the frame buffer device stuff was copied from atyfb.c
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file COPYING in the main directory of this archive for
15 * more details.
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/mm.h>
24 #include <linux/tty.h>
25 #include <linux/malloc.h>
26 #include <linux/vmalloc.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/fb.h>
30 #include <linux/console.h>
31 #include <linux/selection.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36
37 #if defined(CONFIG_PPC)
38 #include <linux/nvram.h>
39 #include <asm/prom.h>
40 #include <asm/pci-bridge.h>
41 #include <video/macmodes.h>
42 #endif
43
44 #include <video/fbcon.h>
45 #include <video/fbcon-cfb8.h>
46 #include <video/fbcon-cfb16.h>
47 #include <video/fbcon-cfb24.h>
48 #include <video/fbcon-cfb32.h>
49
50 #ifndef __powerpc__
51 #define eieio() /* Enforce In-order Execution of I/O */
52 #endif
53
54 /* TwinTurbo (Cosmo) registers */
55 enum {
56 S1SA = 0, /* 0x00 */
57 S2SA = 1, /* 0x04 */
58 SP = 2, /* 0x08 */
59 DSA = 3, /* 0x0C */
60 CNT = 4, /* 0x10 */
61 DP_OCTL = 5, /* 0x14 */
62 CLR = 6, /* 0x18 */
63 BI = 8, /* 0x20 */
64 MBC = 9, /* 0x24 */
65 BLTCTL = 10, /* 0x28 */
66
67 /* Scan Timing Generator Registers */
68 HES = 12, /* 0x30 */
69 HEB = 13, /* 0x34 */
70 HSB = 14, /* 0x38 */
71 HT = 15, /* 0x3C */
72 VES = 16, /* 0x40 */
73 VEB = 17, /* 0x44 */
74 VSB = 18, /* 0x48 */
75 VT = 19, /* 0x4C */
76 HCIV = 20, /* 0x50 */
77 VCIV = 21, /* 0x54 */
78 TCDR = 22, /* 0x58 */
79 VIL = 23, /* 0x5C */
80 STGCTL = 24, /* 0x60 */
81
82 /* Screen Refresh Generator Registers */
83 SSR = 25, /* 0x64 */
84 HRIR = 26, /* 0x68 */
85 SPR = 27, /* 0x6C */
86 CMR = 28, /* 0x70 */
87 SRGCTL = 29, /* 0x74 */
88
89 /* RAM Refresh Generator Registers */
90 RRCIV = 30, /* 0x78 */
91 RRSC = 31, /* 0x7C */
92 RRCR = 34, /* 0x88 */
93
94 /* System Registers */
95 GIOE = 32, /* 0x80 */
96 GIO = 33, /* 0x84 */
97 SCR = 35, /* 0x8C */
98 SSTATUS = 36, /* 0x90 */
99 PRC = 37, /* 0x94 */
100
101 #if 0
102 /* PCI Registers */
103 DVID = 0x00000000L,
104 SC = 0x00000004L,
105 CCR = 0x00000008L,
106 OG = 0x0000000CL,
107 BARM = 0x00000010L,
108 BARER = 0x00000030L,
109 #endif
110 };
111
112 /* IBM 624 RAMDAC Direct Registers */
113 enum {
114 PADDRW = 0x00,
115 PDATA = 0x04,
116 PPMASK = 0x08,
117 PADDRR = 0x0c,
118 PIDXLO = 0x10,
119 PIDXHI = 0x14,
120 PIDXDATA= 0x18,
121 PIDXCTL = 0x1c
122 };
123
124 /* IBM 624 RAMDAC Indirect Registers */
125 enum {
126 CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
127 SYNCCTL = 0x03, /* (0x00) Sync Control */
128 HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
129 PWRMNGMT = 0x05, /* (0x00) Power Management */
130 DACOP = 0x06, /* (0x02) DAC Operation */
131 PALETCTL = 0x07, /* (0x00) Palette Control */
132 SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
133 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
134 BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
135 BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
136 BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
137 BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
138 PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
139 PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
140 SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
141 SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
142 SYSCLKP = 0x17, /* () System Clock P */
143 SYSCLKC = 0x18, /* () System Clock C */
144 /*
145 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
146 * c is charge pump bias which depends on the VCO frequency
147 */
148 PIXM0 = 0x20, /* () Pixel M 0 */
149 PIXN0 = 0x21, /* () Pixel N 0 */
150 PIXP0 = 0x22, /* () Pixel P 0 */
151 PIXC0 = 0x23, /* () Pixel C 0 */
152 CURSCTL = 0x30, /* (0x00) Cursor Control */
153 CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
154 CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
155 CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
156 CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
157 CURSHOTX = 0x35, /* () Cursor Hot Spot X */
158 CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
159 CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
160 CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
161 CURS1R = 0x40, /* () Cursor 1 Red */
162 CURS1G = 0x41, /* () Cursor 1 Green */
163 CURS1B = 0x42, /* () Cursor 1 Blue */
164 CURS2R = 0x43, /* () Cursor 2 Red */
165 CURS2G = 0x44, /* () Cursor 2 Green */
166 CURS2B = 0x45, /* () Cursor 2 Blue */
167 CURS3R = 0x46, /* () Cursor 3 Red */
168 CURS3G = 0x47, /* () Cursor 3 Green */
169 CURS3B = 0x48, /* () Cursor 3 Blue */
170 BORDR = 0x60, /* () Border Color Red */
171 BORDG = 0x61, /* () Border Color Green */
172 BORDB = 0x62, /* () Border Color Blue */
173 MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
174 MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
175 MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
176 KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
177 };
178
179 /* TI TVP 3030 RAMDAC Direct Registers */
180 enum {
181 TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Adress/Index */
182 TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
183 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
184 TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Adress */
185 TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
186 TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
187 /* 6 reserved */
188 TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
189 /* 8 reserved */
190 TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
191 TVPIDATA = 0x28, /* 10 Index Data */
192 TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
193 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
194 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
195 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
196 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
197 };
198
199 /* TI TVP 3030 RAMDAC Indirect Registers */
200 enum {
201 TVPIRREV = 0x01, /* Silicon Revision [RO] */
202 TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
203 TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
204 TVPIRLAC = 0x0f, /* Latch Control (0x06) */
205 TVPIRTCC = 0x18, /* True Color Control (0x80) */
206 TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
207 TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
208 TVPIRPPG = 0x1c, /* Palette Page (0x00) */
209 TVPIRGEC = 0x1d, /* General Control (0x00) */
210 TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
211 TVPIRPLA = 0x2c, /* PLL Address */
212 TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
213 TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
214 TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
215 TVPIRCKL = 0x30, /* Color-Key Overlay Low */
216 TVPIRCKH = 0x31, /* Color-Key Overlay High */
217 TVPIRCRL = 0x32, /* Color-Key Red Low */
218 TVPIRCRH = 0x33, /* Color-Key Red High */
219 TVPIRCGL = 0x34, /* Color-Key Green Low */
220 TVPIRCGH = 0x35, /* Color-Key Green High */
221 TVPIRCBL = 0x36, /* Color-Key Blue Low */
222 TVPIRCBH = 0x37, /* Color-Key Blue High */
223 TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
224 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
225 TVPIRSEN = 0x3a, /* Sense Test (0x00) */
226 TVPIRTMD = 0x3b, /* Test Mode Data */
227 TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
228 TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
229 TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
230 TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
231 TVPIRRES = 0xff /* Software Reset [WO] */
232 };
233
234 struct initvalues {
235 __u8 addr, value;
236 };
237
238 static struct initvalues ibm_initregs[] __initdata = {
239 { CLKCTL, 0x21 },
240 { SYNCCTL, 0x00 },
241 { HSYNCPOS, 0x00 },
242 { PWRMNGMT, 0x00 },
243 { DACOP, 0x02 },
244 { PALETCTL, 0x00 },
245 { SYSCLKCTL, 0x01 },
246
247 /*
248 * Note that colors in X are correct only if all video data is
249 * passed through the palette in the DAC. That is, "indirect
250 * color" must be configured. This is the case for the IBM DAC
251 * used in the 2MB and 4MB cards, at least.
252 */
253 { BPP8, 0x00 },
254 { BPP16, 0x01 },
255 { BPP24, 0x00 },
256 { BPP32, 0x00 },
257
258 { PIXCTL1, 0x05 },
259 { PIXCTL2, 0x00 },
260 { SYSCLKN, 0x08 },
261 { SYSCLKM, 0x4f },
262 { SYSCLKP, 0x00 },
263 { SYSCLKC, 0x00 },
264 { CURSCTL, 0x00 },
265 { CURSACCTL, 0x01 },
266 { CURSACATTR, 0xa8 },
267 { CURS1R, 0xff },
268 { CURS1G, 0xff },
269 { CURS1B, 0xff },
270 { CURS2R, 0xff },
271 { CURS2G, 0xff },
272 { CURS2B, 0xff },
273 { CURS3R, 0xff },
274 { CURS3G, 0xff },
275 { CURS3B, 0xff },
276 { BORDR, 0xff },
277 { BORDG, 0xff },
278 { BORDB, 0xff },
279 { MISCTL1, 0x01 },
280 { MISCTL2, 0x45 },
281 { MISCTL3, 0x00 },
282 { KEYCTL, 0x00 }
283 };
284
285 static struct initvalues tvp_initregs[] __initdata = {
286 { TVPIRICC, 0x00 },
287 { TVPIRBRC, 0xe4 },
288 { TVPIRLAC, 0x06 },
289 { TVPIRTCC, 0x80 },
290 { TVPIRMXC, 0x4d },
291 { TVPIRCLS, 0x05 },
292 { TVPIRPPG, 0x00 },
293 { TVPIRGEC, 0x00 },
294 { TVPIRMIC, 0x08 },
295 { TVPIRCKL, 0xff },
296 { TVPIRCKH, 0xff },
297 { TVPIRCRL, 0xff },
298 { TVPIRCRH, 0xff },
299 { TVPIRCGL, 0xff },
300 { TVPIRCGH, 0xff },
301 { TVPIRCBL, 0xff },
302 { TVPIRCBH, 0xff },
303 { TVPIRCKC, 0x00 },
304 { TVPIRPLA, 0x00 },
305 { TVPIRPPD, 0xc0 },
306 { TVPIRPPD, 0xd5 },
307 { TVPIRPPD, 0xea },
308 { TVPIRPLA, 0x00 },
309 { TVPIRMPD, 0xb9 },
310 { TVPIRMPD, 0x3a },
311 { TVPIRMPD, 0xb1 },
312 { TVPIRPLA, 0x00 },
313 { TVPIRLPD, 0xc1 },
314 { TVPIRLPD, 0x3d },
315 { TVPIRLPD, 0xf3 },
316 };
317
318 struct imstt_regvals {
319 __u32 pitch;
320 __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
321 __u8 pclk_m, pclk_n, pclk_p;
322 /* Values of the tvp which change depending on colormode x resolution */
323 __u8 mlc[3]; /* Memory Loop Config 0x39 */
324 __u8 lckl_p[3]; /* P value of LCKL PLL */
325 };
326
327 struct imstt_cursor {
328 struct timer_list timer;
329 int enable;
330 int on;
331 int vbl_cnt;
332 int blink_rate;
333 __u16 x, y, width, height;
334 };
335
336 struct fb_info_imstt {
337 struct fb_info info;
338 struct fb_fix_screeninfo fix;
339 struct display disp;
340 struct display_switch dispsw;
341 union {
342 #ifdef FBCON_HAS_CFB16
343 __u16 cfb16[16];
344 #endif
345 #ifdef FBCON_HAS_CFB24
346 __u32 cfb24[16];
347 #endif
348 #ifdef FBCON_HAS_CFB32
349 __u32 cfb32[16];
350 #endif
351 } fbcon_cmap;
352 struct {
353 __u8 red, green, blue;
354 } palette[256];
355 struct imstt_regvals init;
356 struct imstt_cursor cursor;
357 unsigned long frame_buffer_phys;
358 unsigned long board_size;
359 __u8 *frame_buffer;
360 unsigned long dc_regs_phys;
361 __u32 *dc_regs;
362 unsigned long cmap_regs_phys;
363 __u8 *cmap_regs;
364 __u32 total_vram;
365 __u32 ramdac;
366 };
367
368 enum {
369 IBM = 0,
370 TVP = 1
371 };
372
373 #define USE_NV_MODES 1
374 #define INIT_BPP 8
375 #define INIT_XRES 640
376 #define INIT_YRES 480
377 #define CURSOR_BLINK_RATE 20
378 #define CURSOR_DRAW_DELAY 2
379
380 static int currcon = 0;
381 static char fontname[40] __initdata = { 0 };
382 static char curblink __initdata = 1;
383 static char noaccel __initdata = 0;
384 #if defined(CONFIG_PPC)
385 static signed char init_vmode __initdata = -1, init_cmode __initdata = -1;
386 #endif
387 static struct fb_info_imstt *fb_info_imstt_p[FB_MAX] = { 0, 0, 0, 0, 0, 0, 0, 0 };
388
389 static struct imstt_regvals tvp_reg_init_2 = {
390 512,
391 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
392 0xec, 0x2a, 0xf3,
393 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
394 };
395
396 static struct imstt_regvals tvp_reg_init_6 = {
397 640,
398 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
399 0xef, 0x2e, 0xb2,
400 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
401 };
402
403 static struct imstt_regvals tvp_reg_init_12 = {
404 800,
405 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
406 0xf6, 0x2e, 0xf2,
407 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
408 };
409
410 static struct imstt_regvals tvp_reg_init_13 = {
411 832,
412 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
413 0xfe, 0x3e, 0xf1,
414 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
415 };
416
417 static struct imstt_regvals tvp_reg_init_17 = {
418 1024,
419 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
420 0xfc, 0x3a, 0xf1,
421 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
422 };
423
424 static struct imstt_regvals tvp_reg_init_18 = {
425 1152,
426 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
427 0xfd, 0x3a, 0xf1,
428 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
429 };
430
431 static struct imstt_regvals tvp_reg_init_19 = {
432 1280,
433 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
434 0xf7, 0x36, 0xf0,
435 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
436 };
437
438 static struct imstt_regvals tvp_reg_init_20 = {
439 1280,
440 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
441 0xf0, 0x2d, 0xf0,
442 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
443 };
444
445 static __u32
446 getclkMHz (struct fb_info_imstt *p)
447 {
448 __u32 clk_m, clk_n, clk_p;
449
450 clk_m = p->init.pclk_m;
451 clk_n = p->init.pclk_n;
452 clk_p = p->init.pclk_p;
453
454 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
455 }
456
457 static void
458 setclkMHz (struct fb_info_imstt *p, __u32 MHz)
459 {
460 __u32 clk_m, clk_n, clk_p, x, stage, spilled;
461
462 clk_m = clk_n = clk_p = 0;
463 stage = spilled = 0;
464 for (;;) {
465 switch (stage) {
466 case 0:
467 clk_m++;
468 break;
469 case 1:
470 clk_n++;
471 break;
472 }
473 x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
474 if (x == MHz)
475 break;
476 if (x > MHz) {
477 spilled = 1;
478 stage = 1;
479 } else if (spilled && x < MHz) {
480 stage = 0;
481 }
482 }
483
484 p->init.pclk_m = clk_m;
485 p->init.pclk_n = clk_n;
486 p->init.pclk_p = clk_p;
487 }
488
489 static struct imstt_regvals *
490 compute_imstt_regvals_ibm (struct fb_info_imstt *p, int xres, int yres)
491 {
492 struct imstt_regvals *init = &p->init;
493 __u32 MHz, hes, heb, veb, htp, vtp;
494
495 switch (xres) {
496 case 640:
497 hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
498 MHz = 30 /* .25 */ ;
499 break;
500 case 832:
501 hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
502 MHz = 57 /* .27_ */ ;
503 break;
504 case 1024:
505 hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
506 MHz = 80;
507 break;
508 case 1152:
509 hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
510 MHz = 101 /* .6_ */ ;
511 break;
512 case 1280:
513 hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
514 MHz = yres == 960 ? 126 : 135;
515 break;
516 case 1600:
517 hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
518 MHz = 200;
519 break;
520 default:
521 return 0;
522 }
523
524 setclkMHz(p, MHz);
525
526 init->hes = hes;
527 init->heb = heb;
528 init->hsb = init->heb + (xres >> 3);
529 init->ht = init->hsb + htp;
530 init->ves = 0x0003;
531 init->veb = veb;
532 init->vsb = init->veb + yres;
533 init->vt = init->vsb + vtp;
534 init->vil = init->vsb;
535
536 init->pitch = xres;
537
538 return init;
539 }
540
541 static struct imstt_regvals *
542 compute_imstt_regvals_tvp (struct fb_info_imstt *p, int xres, int yres)
543 {
544 struct imstt_regvals *init;
545
546 switch (xres) {
547 case 512:
548 init = &tvp_reg_init_2;
549 break;
550 case 640:
551 init = &tvp_reg_init_6;
552 break;
553 case 800:
554 init = &tvp_reg_init_12;
555 break;
556 case 832:
557 init = &tvp_reg_init_13;
558 break;
559 case 1024:
560 init = &tvp_reg_init_17;
561 break;
562 case 1152:
563 init = &tvp_reg_init_18;
564 break;
565 case 1280:
566 init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
567 break;
568 default:
569 return 0;
570 }
571 p->init = *init;
572
573 return init;
574 }
575
576 static struct imstt_regvals *
577 compute_imstt_regvals (struct fb_info_imstt *p, u_int xres, u_int yres)
578 {
579 if (p->ramdac == IBM)
580 return compute_imstt_regvals_ibm(p, xres, yres);
581 else
582 return compute_imstt_regvals_tvp(p, xres, yres);
583 }
584
585 static void
586 set_imstt_regvals_ibm (struct fb_info_imstt *p, u_int bpp)
587 {
588 struct imstt_regvals *init = &p->init;
589 __u8 pformat = (bpp >> 3) + 2;
590
591 p->cmap_regs[PIDXHI] = 0; eieio();
592 p->cmap_regs[PIDXLO] = PIXM0; eieio();
593 p->cmap_regs[PIDXDATA] = init->pclk_m; eieio();
594 p->cmap_regs[PIDXLO] = PIXN0; eieio();
595 p->cmap_regs[PIDXDATA] = init->pclk_n; eieio();
596 p->cmap_regs[PIDXLO] = PIXP0; eieio();
597 p->cmap_regs[PIDXDATA] = init->pclk_p; eieio();
598 p->cmap_regs[PIDXLO] = PIXC0; eieio();
599 p->cmap_regs[PIDXDATA] = 0x02; eieio();
600
601 p->cmap_regs[PIDXLO] = PIXFMT; eieio();
602 p->cmap_regs[PIDXDATA] = pformat; eieio();
603 }
604
605 static void
606 set_imstt_regvals_tvp (struct fb_info_imstt *p, u_int bpp)
607 {
608 struct imstt_regvals *init = &p->init;
609 __u8 tcc, mxc, lckl_n, mic;
610 __u8 mlc, lckl_p;
611
612 switch (bpp) {
613 case 8:
614 tcc = 0x80;
615 mxc = 0x4d;
616 lckl_n = 0xc1;
617 mlc = init->mlc[0];
618 lckl_p = init->lckl_p[0];
619 break;
620 case 16:
621 tcc = 0x44;
622 mxc = 0x55;
623 lckl_n = 0xe1;
624 mlc = init->mlc[1];
625 lckl_p = init->lckl_p[1];
626 break;
627 case 24:
628 tcc = 0x5e;
629 mxc = 0x5d;
630 lckl_n = 0xf1;
631 mlc = init->mlc[2];
632 lckl_p = init->lckl_p[2];
633 break;
634 case 32:
635 tcc = 0x46;
636 mxc = 0x5d;
637 lckl_n = 0xf1;
638 mlc = init->mlc[2];
639 lckl_p = init->lckl_p[2];
640 break;
641 }
642 mic = 0x08;
643
644 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
645 p->cmap_regs[TVPIDATA] = 0x00; eieio();
646 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
647 p->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
648 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
649 p->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
650 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
651 p->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
652
653 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
654 p->cmap_regs[TVPIDATA] = tcc; eieio();
655 p->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
656 p->cmap_regs[TVPIDATA] = mxc; eieio();
657 p->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
658 p->cmap_regs[TVPIDATA] = mic; eieio();
659
660 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
661 p->cmap_regs[TVPIDATA] = 0x00; eieio();
662 p->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
663 p->cmap_regs[TVPIDATA] = lckl_n; eieio();
664
665 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
666 p->cmap_regs[TVPIDATA] = 0x15; eieio();
667 p->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
668 p->cmap_regs[TVPIDATA] = mlc; eieio();
669
670 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
671 p->cmap_regs[TVPIDATA] = 0x2a; eieio();
672 p->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
673 p->cmap_regs[TVPIDATA] = lckl_p; eieio();
674 }
675
676 static void
677 set_imstt_regvals (struct fb_info_imstt *p, u_int bpp)
678 {
679 struct imstt_regvals *init = &p->init;
680 __u32 ctl, pitch, byteswap, scr;
681
682 if (p->ramdac == IBM)
683 set_imstt_regvals_ibm(p, bpp);
684 else
685 set_imstt_regvals_tvp(p, bpp);
686
687 /*
688 * From what I (jsk) can gather poking around with MacsBug,
689 * bits 8 and 9 in the SCR register control endianness
690 * correction (byte swapping). These bits must be set according
691 * to the color depth as follows:
692 * Color depth Bit 9 Bit 8
693 * ========== ===== =====
694 * 8bpp 0 0
695 * 16bpp 0 1
696 * 32bpp 1 1
697 */
698 switch (bpp) {
699 case 8:
700 ctl = 0x17b1;
701 pitch = init->pitch >> 2;
702 byteswap = 0x000;
703 break;
704 case 16:
705 ctl = 0x17b3;
706 pitch = init->pitch >> 1;
707 byteswap = 0x100;
708 break;
709 case 24:
710 ctl = 0x17b9;
711 pitch = init->pitch - (p->init.pitch >> 2);
712 byteswap = 0x200;
713 break;
714 case 32:
715 ctl = 0x17b5;
716 pitch = init->pitch;
717 byteswap = 0x300;
718 break;
719 }
720 if (p->ramdac == TVP)
721 ctl -= 0x30;
722
723 out_le32(&p->dc_regs[HES], init->hes);
724 out_le32(&p->dc_regs[HEB], init->heb);
725 out_le32(&p->dc_regs[HSB], init->hsb);
726 out_le32(&p->dc_regs[HT], init->ht);
727 out_le32(&p->dc_regs[VES], init->ves);
728 out_le32(&p->dc_regs[VEB], init->veb);
729 out_le32(&p->dc_regs[VSB], init->vsb);
730 out_le32(&p->dc_regs[VT], init->vt);
731 out_le32(&p->dc_regs[VIL], init->vil);
732 out_le32(&p->dc_regs[HCIV], 1);
733 out_le32(&p->dc_regs[VCIV], 1);
734 out_le32(&p->dc_regs[TCDR], 4);
735 out_le32(&p->dc_regs[RRCIV], 1);
736 out_le32(&p->dc_regs[RRSC], 0x980);
737 out_le32(&p->dc_regs[RRCR], 0x11);
738
739 if (p->ramdac == IBM) {
740 out_le32(&p->dc_regs[HRIR], 0x0100);
741 out_le32(&p->dc_regs[CMR], 0x00ff);
742 out_le32(&p->dc_regs[SRGCTL], 0x0073);
743 } else {
744 out_le32(&p->dc_regs[HRIR], 0x0200);
745 out_le32(&p->dc_regs[CMR], 0x01ff);
746 out_le32(&p->dc_regs[SRGCTL], 0x0003);
747 }
748
749 switch (p->total_vram) {
750 case 0x200000:
751 scr = 0x059d | byteswap;
752 break;
753 /* case 0x400000:
754 case 0x800000: */
755 default:
756 pitch >>= 1;
757 scr = 0x150dd | byteswap;
758 break;
759 }
760
761 out_le32(&p->dc_regs[SCR], scr);
762 out_le32(&p->dc_regs[SPR], pitch);
763 out_le32(&p->dc_regs[STGCTL], ctl);
764 }
765
766 static inline void
767 set_offset (struct display *disp, struct fb_info_imstt *p)
768 {
769 __u32 off = disp->var.yoffset * (disp->line_length >> 3)
770 + ((disp->var.xoffset * (disp->var.bits_per_pixel >> 3)) >> 3);
771 out_le32(&p->dc_regs[SSR], off);
772 }
773
774 static inline void
775 set_555 (struct fb_info_imstt *p)
776 {
777 if (p->ramdac == IBM) {
778 p->cmap_regs[PIDXHI] = 0; eieio();
779 p->cmap_regs[PIDXLO] = BPP16; eieio();
780 p->cmap_regs[PIDXDATA] = 0x01; eieio();
781 } else {
782 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
783 p->cmap_regs[TVPIDATA] = 0x44; eieio();
784 }
785 }
786
787 static inline void
788 set_565 (struct fb_info_imstt *p)
789 {
790 if (p->ramdac == IBM) {
791 p->cmap_regs[PIDXHI] = 0; eieio();
792 p->cmap_regs[PIDXLO] = BPP16; eieio();
793 p->cmap_regs[PIDXDATA] = 0x03; eieio();
794 } else {
795 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
796 p->cmap_regs[TVPIDATA] = 0x45; eieio();
797 }
798 }
799
800 static void
801 imstt_set_cursor (struct fb_info_imstt *p, int on)
802 {
803 struct imstt_cursor *c = &p->cursor;
804
805 if (p->ramdac == IBM) {
806 p->cmap_regs[PIDXHI] = 0; eieio();
807 if (!on) {
808 p->cmap_regs[PIDXLO] = CURSCTL; eieio();
809 p->cmap_regs[PIDXDATA] = 0x00; eieio();
810 } else {
811 p->cmap_regs[PIDXLO] = CURSXHI; eieio();
812 p->cmap_regs[PIDXDATA] = c->x >> 8; eieio();
813 p->cmap_regs[PIDXLO] = CURSXLO; eieio();
814 p->cmap_regs[PIDXDATA] = c->x & 0xff; eieio();
815 p->cmap_regs[PIDXLO] = CURSYHI; eieio();
816 p->cmap_regs[PIDXDATA] = c->y >> 8; eieio();
817 p->cmap_regs[PIDXLO] = CURSYLO; eieio();
818 p->cmap_regs[PIDXDATA] = c->y & 0xff; eieio();
819 p->cmap_regs[PIDXLO] = CURSCTL; eieio();
820 p->cmap_regs[PIDXDATA] = 0x02; eieio();
821 }
822 } else {
823 if (!on) {
824 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
825 p->cmap_regs[TVPIDATA] = 0x00; eieio();
826 } else {
827 __u16 x = c->x + 0x40, y = c->y + 0x40;
828
829 p->cmap_regs[TVPCXPOH] = x >> 8; eieio();
830 p->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
831 p->cmap_regs[TVPCYPOH] = y >> 8; eieio();
832 p->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
833 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
834 p->cmap_regs[TVPIDATA] = 0x02; eieio();
835 }
836 }
837 }
838
839 static void
840 imsttfbcon_cursor (struct display *disp, int mode, int x, int y)
841 {
842 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
843 struct imstt_cursor *c = &p->cursor;
844
845 x *= fontwidth(disp);
846 y *= fontheight(disp);
847
848 if (c->x == x && c->y == y && (mode == CM_ERASE) == !c->enable)
849 return;
850
851 c->enable = 0;
852 if (c->on)
853 imstt_set_cursor(p, 0);
854 c->x = x - disp->var.xoffset;
855 c->y = y - disp->var.yoffset;
856
857 switch (mode) {
858 case CM_ERASE:
859 c->on = 0;
860 break;
861 case CM_DRAW:
862 case CM_MOVE:
863 if (c->on)
864 imstt_set_cursor(p, c->on);
865 else
866 c->vbl_cnt = CURSOR_DRAW_DELAY;
867 c->enable = 1;
868 break;
869 }
870 }
871
872 static int
873 imsttfbcon_set_font (struct display *disp, int width, int height)
874 {
875 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
876 struct imstt_cursor *c = &p->cursor;
877 u_int x, y;
878 __u8 fgc;
879
880 if (width > 32 || height > 32)
881 return -EINVAL;
882
883 c->height = height;
884 c->width = width;
885
886 fgc = ~attr_bgcol_ec(disp, disp->conp);
887
888 if (p->ramdac == IBM) {
889 p->cmap_regs[PIDXHI] = 1; eieio();
890 for (x = 0; x < 0x100; x++) {
891 p->cmap_regs[PIDXLO] = x; eieio();
892 p->cmap_regs[PIDXDATA] = 0x00; eieio();
893 }
894 p->cmap_regs[PIDXHI] = 1; eieio();
895 for (y = 0; y < height; y++)
896 for (x = 0; x < width >> 2; x++) {
897 p->cmap_regs[PIDXLO] = x + y * 8; eieio();
898 p->cmap_regs[PIDXDATA] = 0xff; eieio();
899 }
900 p->cmap_regs[PIDXHI] = 0; eieio();
901 p->cmap_regs[PIDXLO] = CURS1R; eieio();
902 p->cmap_regs[PIDXDATA] = fgc; eieio();
903 p->cmap_regs[PIDXLO] = CURS1G; eieio();
904 p->cmap_regs[PIDXDATA] = fgc; eieio();
905 p->cmap_regs[PIDXLO] = CURS1B; eieio();
906 p->cmap_regs[PIDXDATA] = fgc; eieio();
907 p->cmap_regs[PIDXLO] = CURS2R; eieio();
908 p->cmap_regs[PIDXDATA] = fgc; eieio();
909 p->cmap_regs[PIDXLO] = CURS2G; eieio();
910 p->cmap_regs[PIDXDATA] = fgc; eieio();
911 p->cmap_regs[PIDXLO] = CURS2B; eieio();
912 p->cmap_regs[PIDXDATA] = fgc; eieio();
913 p->cmap_regs[PIDXLO] = CURS3R; eieio();
914 p->cmap_regs[PIDXDATA] = fgc; eieio();
915 p->cmap_regs[PIDXLO] = CURS3G; eieio();
916 p->cmap_regs[PIDXDATA] = fgc; eieio();
917 p->cmap_regs[PIDXLO] = CURS3B; eieio();
918 p->cmap_regs[PIDXDATA] = fgc; eieio();
919 } else {
920 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
921 p->cmap_regs[TVPIDATA] &= 0x03; eieio();
922 p->cmap_regs[TVPADDRW] = 0; eieio();
923 for (x = 0; x < 0x200; x++) {
924 p->cmap_regs[TVPCRDAT] = 0x00; eieio();
925 }
926 for (x = 0; x < 0x200; x++) {
927 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
928 }
929 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
930 p->cmap_regs[TVPIDATA] &= 0x03; eieio();
931 for (y = 0; y < height; y++)
932 for (x = 0; x < width >> 3; x++) {
933 p->cmap_regs[TVPADDRW] = x + y * 8; eieio();
934 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
935 }
936 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
937 p->cmap_regs[TVPIDATA] |= 0x08; eieio();
938 for (y = 0; y < height; y++)
939 for (x = 0; x < width >> 3; x++) {
940 p->cmap_regs[TVPADDRW] = x + y * 8; eieio();
941 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
942 }
943 p->cmap_regs[TVPCADRW] = 0x00; eieio();
944 for (x = 0; x < 12; x++) {
945 p->cmap_regs[TVPCDATA] = fgc; eieio();
946 }
947 }
948
949 return 1;
950 }
951
952 static void
953 imstt_cursor_timer_handler (unsigned long dev_addr)
954 {
955 struct fb_info_imstt *p = (struct fb_info_imstt *)dev_addr;
956 struct imstt_cursor *c = &p->cursor;
957
958 if (!c->enable)
959 goto out;
960
961 if (c->vbl_cnt && --c->vbl_cnt == 0) {
962 c->on ^= 1;
963 imstt_set_cursor(p, c->on);
964 c->vbl_cnt = c->blink_rate;
965 }
966
967 out:
968 c->timer.expires = jiffies + (HZ / 50);
969 add_timer(&c->timer);
970 }
971
972 static void __init
973 imstt_cursor_init (struct fb_info_imstt *p)
974 {
975 struct imstt_cursor *c = &p->cursor;
976
977 imsttfbcon_set_font(&p->disp, fontwidth(&p->disp), fontheight(&p->disp));
978
979 c->enable = 1;
980 c->on = 1;
981 c->x = c->y = 0;
982 c->blink_rate = 0;
983 c->vbl_cnt = CURSOR_DRAW_DELAY;
984
985 if (curblink) {
986 c->blink_rate = CURSOR_BLINK_RATE;
987 init_timer(&c->timer);
988 c->timer.expires = jiffies + (HZ / 50);
989 c->timer.data = (unsigned long)p;
990 c->timer.function = imstt_cursor_timer_handler;
991 add_timer(&c->timer);
992 }
993 }
994
995 static void
996 imsttfbcon_bmove (struct display *disp, int sy, int sx, int dy, int dx, int height, int width)
997 {
998 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
999 __u32 Bpp, line_pitch,
1000 fb_offset_old, fb_offset_new,
1001 sp, dp_octl, cnt, bltctl;
1002
1003 Bpp = disp->var.bits_per_pixel >> 3,
1004
1005 sy *= fontheight(disp);
1006 sx *= fontwidth(disp);
1007 sx *= Bpp;
1008 dy *= fontheight(disp);
1009 dx *= fontwidth(disp);
1010 dx *= Bpp;
1011 height *= fontheight(disp);
1012 height--;
1013 width *= fontwidth(disp);
1014 width *= Bpp;
1015 width--;
1016
1017 line_pitch = disp->line_length;
1018 bltctl = 0x05;
1019 sp = line_pitch << 16;
1020 cnt = height << 16;
1021
1022 if (sy < dy) {
1023 sy += height;
1024 dy += height;
1025 sp |= -(line_pitch) & 0xffff;
1026 dp_octl = -(line_pitch) & 0xffff;
1027 } else {
1028 sp |= line_pitch;
1029 dp_octl = line_pitch;
1030 }
1031 if (sx < dx) {
1032 sx += width;
1033 dx += width;
1034 bltctl |= 0x80;
1035 cnt |= -(width) & 0xffff;
1036 } else {
1037 cnt |= width;
1038 }
1039 fb_offset_old = sy * line_pitch + sx;
1040 fb_offset_new = dy * line_pitch + dx;
1041
1042 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1043 out_le32(&p->dc_regs[S1SA], fb_offset_old);
1044 out_le32(&p->dc_regs[SP], sp);
1045 out_le32(&p->dc_regs[DSA], fb_offset_new);
1046 out_le32(&p->dc_regs[CNT], cnt);
1047 out_le32(&p->dc_regs[DP_OCTL], dp_octl);
1048 out_le32(&p->dc_regs[BLTCTL], bltctl);
1049 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1050 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1051 }
1052
1053 static void
1054 imsttfbcon_clear (struct vc_data *conp, struct display *disp,
1055 int sy, int sx, int height, int width)
1056 {
1057 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
1058 __u32 Bpp, line_pitch, bgc;
1059
1060 bgc = attr_bgcol_ec(disp, conp);
1061 bgc |= (bgc << 8);
1062 bgc |= (bgc << 16);
1063
1064 Bpp = disp->var.bits_per_pixel >> 3,
1065 line_pitch = disp->line_length;
1066
1067 sy *= fontheight(disp);
1068 sy *= line_pitch;
1069 sx *= fontwidth(disp);
1070 sx *= Bpp;
1071 height *= fontheight(disp);
1072 height--;
1073 width *= fontwidth(disp);
1074 width *= Bpp;
1075 width--;
1076
1077 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1078 out_le32(&p->dc_regs[DSA], sy + sx);
1079 out_le32(&p->dc_regs[CNT], (height << 16) | width);
1080 out_le32(&p->dc_regs[DP_OCTL], line_pitch);
1081 out_le32(&p->dc_regs[BI], 0xffffffff);
1082 out_le32(&p->dc_regs[MBC], 0xffffffff);
1083 out_le32(&p->dc_regs[CLR], bgc);
1084 out_le32(&p->dc_regs[BLTCTL], 0x840); /* 0x200000 */
1085 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1086 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1087 }
1088
1089 static void
1090 imsttfbcon_revc (struct display *disp, int sx, int sy)
1091 {
1092 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
1093 __u32 Bpp, line_pitch, height, width;
1094
1095 Bpp = disp->var.bits_per_pixel >> 3,
1096 line_pitch = disp->line_length;
1097
1098 height = fontheight(disp);
1099 width = fontwidth(disp) * Bpp;
1100 sy *= height;
1101 sy *= line_pitch;
1102 sx *= width;
1103 height--;
1104 width--;
1105
1106 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1107 out_le32(&p->dc_regs[DSA], sy + sx);
1108 out_le32(&p->dc_regs[S1SA], sy + sx);
1109 out_le32(&p->dc_regs[CNT], (height << 16) | width);
1110 out_le32(&p->dc_regs[DP_OCTL], line_pitch);
1111 out_le32(&p->dc_regs[SP], line_pitch);
1112 out_le32(&p->dc_regs[BLTCTL], 0x40005);
1113 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1114 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1115 }
1116
1117 #ifdef FBCON_HAS_CFB8
1118 static struct display_switch fbcon_imstt8 = {
1119 setup: fbcon_cfb8_setup,
1120 bmove: imsttfbcon_bmove,
1121 clear: imsttfbcon_clear,
1122 putc: fbcon_cfb8_putc,
1123 putcs: fbcon_cfb8_putcs,
1124 revc: imsttfbcon_revc,
1125 cursor: imsttfbcon_cursor,
1126 set_font: imsttfbcon_set_font,
1127 clear_margins: fbcon_cfb8_clear_margins,
1128 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1129 };
1130 #endif
1131 #ifdef FBCON_HAS_CFB16
1132 static struct display_switch fbcon_imstt16 = {
1133 setup: fbcon_cfb16_setup,
1134 bmove: imsttfbcon_bmove,
1135 clear: imsttfbcon_clear,
1136 putc: fbcon_cfb16_putc,
1137 putcs: fbcon_cfb16_putcs,
1138 revc: imsttfbcon_revc,
1139 cursor: imsttfbcon_cursor,
1140 set_font: imsttfbcon_set_font,
1141 clear_margins: fbcon_cfb16_clear_margins,
1142 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1143 };
1144 #endif
1145 #ifdef FBCON_HAS_CFB24
1146 static struct display_switch fbcon_imstt24 = {
1147 setup: fbcon_cfb24_setup,
1148 bmove: imsttfbcon_bmove,
1149 clear: imsttfbcon_clear,
1150 putc: fbcon_cfb24_putc,
1151 putcs: fbcon_cfb24_putcs,
1152 revc: imsttfbcon_revc,
1153 cursor: imsttfbcon_cursor,
1154 set_font: imsttfbcon_set_font,
1155 clear_margins: fbcon_cfb24_clear_margins,
1156 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1157 };
1158 #endif
1159 #ifdef FBCON_HAS_CFB32
1160 static struct display_switch fbcon_imstt32 = {
1161 setup: fbcon_cfb32_setup,
1162 bmove: imsttfbcon_bmove,
1163 clear: imsttfbcon_clear,
1164 putc: fbcon_cfb32_putc,
1165 putcs: fbcon_cfb32_putcs,
1166 revc: imsttfbcon_revc,
1167 cursor: imsttfbcon_cursor,
1168 set_font: imsttfbcon_set_font,
1169 clear_margins: fbcon_cfb32_clear_margins,
1170 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1171 };
1172 #endif
1173
1174 #ifdef CONFIG_FB_COMPAT_XPMAC
1175 #include <asm/vc_ioctl.h>
1176
1177 extern struct vc_mode display_info;
1178 extern struct fb_info *console_fb_info;
1179
1180 static void
1181 set_display_info (struct display *disp)
1182 {
1183 display_info.width = disp->var.xres;
1184 display_info.height = disp->var.yres;
1185 display_info.depth = disp->var.bits_per_pixel;
1186 display_info.pitch = disp->line_length;
1187
1188 switch (disp->var.xres) {
1189 case 512:
1190 display_info.mode = 2;
1191 break;
1192 case 640:
1193 display_info.mode = 6;
1194 break;
1195 case 800:
1196 display_info.mode = 12;
1197 break;
1198 case 832:
1199 display_info.mode = 13;
1200 break;
1201 case 1024:
1202 display_info.mode = 17;
1203 break;
1204 case 1152:
1205 display_info.mode = 18;
1206 break;
1207 case 1280:
1208 display_info.mode = disp->var.yres == 960 ? 19 : 20;
1209 break;
1210 default:
1211 display_info.mode = 0;
1212 }
1213 }
1214 #endif
1215
1216 static int
1217 imsttfb_getcolreg (u_int regno, u_int *red, u_int *green,
1218 u_int *blue, u_int *transp, struct fb_info *info)
1219 {
1220 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1221
1222 if (regno > 255)
1223 return 1;
1224 *red = (p->palette[regno].red << 8) | p->palette[regno].red;
1225 *green = (p->palette[regno].green << 8) | p->palette[regno].green;
1226 *blue = (p->palette[regno].blue << 8) | p->palette[regno].blue;
1227 *transp = 0;
1228
1229 return 0;
1230 }
1231
1232 static int
1233 imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
1234 u_int transp, struct fb_info *info)
1235 {
1236 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1237 u_int bpp = fb_display[currcon].var.bits_per_pixel;
1238 u_int i;
1239
1240 if (regno > 255)
1241 return 1;
1242
1243 red >>= 8;
1244 green >>= 8;
1245 blue >>= 8;
1246
1247 p->palette[regno].red = red;
1248 p->palette[regno].green = green;
1249 p->palette[regno].blue = blue;
1250
1251 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
1252 if (0 && bpp == 16) /* screws up X */
1253 p->cmap_regs[PADDRW] = regno << 3;
1254 else
1255 p->cmap_regs[PADDRW] = regno;
1256 eieio();
1257
1258 p->cmap_regs[PDATA] = red; eieio();
1259 p->cmap_regs[PDATA] = green; eieio();
1260 p->cmap_regs[PDATA] = blue; eieio();
1261
1262 if (regno < 16)
1263 switch (bpp) {
1264 #ifdef FBCON_HAS_CFB16
1265 case 16:
1266 p->fbcon_cmap.cfb16[regno] = (regno << (fb_display[currcon].var.green.length == 5 ? 10 : 11)) | (regno << 5) | regno;
1267 break;
1268 #endif
1269 #ifdef FBCON_HAS_CFB24
1270 case 24:
1271 p->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
1272 break;
1273 #endif
1274 #ifdef FBCON_HAS_CFB32
1275 case 32:
1276 i = (regno << 8) | regno;
1277 p->fbcon_cmap.cfb32[regno] = (i << 16) | i;
1278 break;
1279 #endif
1280 }
1281
1282 return 0;
1283 }
1284
1285 static void
1286 do_install_cmap (int con, struct fb_info *info)
1287 {
1288 if (fb_display[con].cmap.len)
1289 fb_set_cmap(&fb_display[con].cmap, 1, imsttfb_setcolreg, info);
1290 else {
1291 u_int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1292 fb_set_cmap(fb_default_cmap(size), 1, imsttfb_setcolreg, info);
1293 }
1294 }
1295
1296 static int
1297 imsttfb_get_fix (struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
1298 {
1299 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1300 struct fb_var_screeninfo *var = &fb_display[con].var;
1301
1302 *fix = p->fix;
1303 fix->visual = var->bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1304 : FB_VISUAL_DIRECTCOLOR;
1305 fix->line_length = var->xres * (var->bits_per_pixel >> 3);
1306
1307 return 0;
1308 }
1309
1310 static int
1311 imsttfb_get_var (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1312 {
1313 *var = fb_display[con].var;
1314
1315 return 0;
1316 }
1317
1318 static void
1319 set_dispsw (struct display *disp, struct fb_info_imstt *p)
1320 {
1321 u_int accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1322
1323 if (disp->conp && disp->conp->vc_sw && disp->conp->vc_sw->con_cursor)
1324 disp->conp->vc_sw->con_cursor(disp->conp, CM_ERASE);
1325
1326 p->dispsw = fbcon_dummy;
1327 disp->dispsw = &p->dispsw;
1328 disp->dispsw_data = 0;
1329 switch (disp->var.bits_per_pixel) {
1330 case 8:
1331 disp->var.red.offset = 0;
1332 disp->var.red.length = 8;
1333 disp->var.green.offset = 0;
1334 disp->var.green.length = 8;
1335 disp->var.blue.offset = 0;
1336 disp->var.blue.length = 8;
1337 disp->var.transp.offset = 0;
1338 disp->var.transp.length = 0;
1339 #ifdef FBCON_HAS_CFB8
1340 p->dispsw = accel ? fbcon_imstt8 : fbcon_cfb8;
1341 #endif
1342 break;
1343 case 16: /* RGB 555 or 565 */
1344 if (disp->var.green.length != 6)
1345 disp->var.red.offset = 10;
1346 disp->var.red.length = 5;
1347 disp->var.green.offset = 5;
1348 if (disp->var.green.length != 6)
1349 disp->var.green.length = 5;
1350 disp->var.blue.offset = 0;
1351 disp->var.blue.length = 5;
1352 disp->var.transp.offset = 0;
1353 disp->var.transp.length = 0;
1354 #ifdef FBCON_HAS_CFB16
1355 p->dispsw = accel ? fbcon_imstt16 : fbcon_cfb16;
1356 disp->dispsw_data = p->fbcon_cmap.cfb16;
1357 #endif
1358 break;
1359 case 24: /* RGB 888 */
1360 disp->var.red.offset = 16;
1361 disp->var.red.length = 8;
1362 disp->var.green.offset = 8;
1363 disp->var.green.length = 8;
1364 disp->var.blue.offset = 0;
1365 disp->var.blue.length = 8;
1366 disp->var.transp.offset = 0;
1367 disp->var.transp.length = 0;
1368 #ifdef FBCON_HAS_CFB24
1369 p->dispsw = accel ? fbcon_imstt24 : fbcon_cfb24;
1370 disp->dispsw_data = p->fbcon_cmap.cfb24;
1371 #endif
1372 break;
1373 case 32: /* RGBA 8888 */
1374 disp->var.red.offset = 16;
1375 disp->var.red.length = 8;
1376 disp->var.green.offset = 8;
1377 disp->var.green.length = 8;
1378 disp->var.blue.offset = 0;
1379 disp->var.blue.length = 8;
1380 disp->var.transp.offset = 24;
1381 disp->var.transp.length = 8;
1382 #ifdef FBCON_HAS_CFB32
1383 p->dispsw = accel ? fbcon_imstt32 : fbcon_cfb32;
1384 disp->dispsw_data = p->fbcon_cmap.cfb32;
1385 #endif
1386 break;
1387 }
1388
1389 if (accel && p->ramdac != IBM) {
1390 p->dispsw.cursor = 0;
1391 p->dispsw.set_font = 0;
1392 }
1393
1394 #ifdef CONFIG_FB_COMPAT_XPMAC
1395 set_display_info(disp);
1396 #endif
1397 }
1398
1399 static void
1400 set_disp (struct display *disp, struct fb_info_imstt *p)
1401 {
1402 u_int accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1403
1404 disp->fb_info = &p->info;
1405
1406 set_dispsw(disp, p);
1407
1408 disp->visual = disp->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1409 : FB_VISUAL_DIRECTCOLOR;
1410 disp->screen_base = (__u8 *)p->frame_buffer;
1411 disp->visual = p->fix.visual;
1412 disp->type = p->fix.type;
1413 disp->type_aux = p->fix.type_aux;
1414 disp->line_length = disp->var.xres * (disp->var.bits_per_pixel >> 3);
1415 disp->can_soft_blank = 1;
1416 disp->inverse = 0;
1417 disp->ypanstep = 1;
1418 disp->ywrapstep = 0;
1419 if (accel) {
1420 disp->scrollmode = SCROLL_YNOMOVE;
1421 if (disp->var.yres == disp->var.yres_virtual) {
1422 __u32 vram = (p->total_vram - (PAGE_SIZE << 2));
1423 disp->var.yres_virtual = ((vram << 3) / disp->var.bits_per_pixel) / disp->var.xres_virtual;
1424 if (disp->var.yres_virtual < disp->var.yres)
1425 disp->var.yres_virtual = disp->var.yres;
1426 }
1427 } else {
1428 disp->scrollmode = SCROLL_YREDRAW;
1429 }
1430
1431 disp->var.activate = 0;
1432 disp->var.red.msb_right = 0;
1433 disp->var.green.msb_right = 0;
1434 disp->var.blue.msb_right = 0;
1435 disp->var.transp.msb_right = 0;
1436 disp->var.height = -1;
1437 disp->var.width = -1;
1438 disp->var.vmode = FB_VMODE_NONINTERLACED;
1439 disp->var.left_margin = disp->var.right_margin = 16;
1440 disp->var.upper_margin = disp->var.lower_margin = 16;
1441 disp->var.hsync_len = disp->var.vsync_len = 8;
1442 }
1443
1444 static int
1445 imsttfb_set_var (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1446 {
1447 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1448 struct display *disp;
1449 u_int oldbpp, oldxres, oldyres, oldgreenlen, oldaccel;
1450
1451 disp = &fb_display[con];
1452
1453 if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
1454 && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
1455 || var->xres_virtual < var->xres || var->yres_virtual < var->yres
1456 || var->nonstd
1457 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1458 return -EINVAL;
1459
1460 if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > p->total_vram
1461 || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > p->total_vram)
1462 return -EINVAL;
1463
1464 if (!((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW))
1465 return 0;
1466
1467 if (!compute_imstt_regvals(p, var->xres, var->yres))
1468 return -EINVAL;
1469
1470 oldbpp = disp->var.bits_per_pixel;
1471 oldxres = disp->var.xres;
1472 oldyres = disp->var.yres;
1473 oldgreenlen = disp->var.green.length;
1474 oldaccel = disp->var.accel_flags;
1475
1476 disp->var.bits_per_pixel = var->bits_per_pixel;
1477 disp->var.xres = var->xres;
1478 disp->var.yres = var->yres;
1479 disp->var.xres_virtual = var->xres_virtual;
1480 disp->var.yres_virtual = var->yres_virtual;
1481 disp->var.green.length = var->green.length;
1482 disp->var.accel_flags = var->accel_flags;
1483
1484 set_disp(disp, p);
1485
1486 if (info->changevar)
1487 (*info->changevar)(con);
1488
1489 if (con == currcon) {
1490 if (oldgreenlen != disp->var.green.length) {
1491 if (disp->var.green.length == 6)
1492 set_565(p);
1493 else
1494 set_555(p);
1495 }
1496 if (oldxres != disp->var.xres || oldyres != disp->var.yres || oldbpp != disp->var.bits_per_pixel)
1497 set_imstt_regvals(p, disp->var.bits_per_pixel);
1498
1499 }
1500 disp->var.pixclock = 1000000 / getclkMHz(p);
1501
1502 if (oldbpp != disp->var.bits_per_pixel) {
1503 int err = fb_alloc_cmap(&disp->cmap, 0, 0);
1504 if (err)
1505 return err;
1506 do_install_cmap(con, info);
1507 }
1508 *var = disp->var;
1509
1510 return 0;
1511 }
1512
1513 static int
1514 imsttfb_pan_display (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1515 {
1516 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1517 struct display *disp = &fb_display[con];
1518
1519 if (var->xoffset + disp->var.xres > disp->var.xres_virtual
1520 || var->yoffset + disp->var.yres > disp->var.yres_virtual)
1521 return -EINVAL;
1522
1523 disp->var.xoffset = var->xoffset;
1524 disp->var.yoffset = var->yoffset;
1525 if (con == currcon)
1526 set_offset(disp, p);
1527
1528 return 0;
1529 }
1530
1531 static int
1532 imsttfb_get_cmap (struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
1533 {
1534 if (con == currcon) /* current console? */
1535 return fb_get_cmap(cmap, kspc, imsttfb_getcolreg, info);
1536 else if (fb_display[con].cmap.len) /* non default colormap? */
1537 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1538 else {
1539 u_int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1540 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
1541 }
1542
1543 return 0;
1544 }
1545
1546 static int
1547 imsttfb_set_cmap (struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
1548 {
1549 int err;
1550
1551 if (!fb_display[con].cmap.len) { /* no colormap allocated? */
1552 int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1553 if ((err = fb_alloc_cmap(&fb_display[con].cmap, size, 0)))
1554 return err;
1555 }
1556 if (con == currcon) /* current console? */
1557 return fb_set_cmap(cmap, kspc, imsttfb_setcolreg, info);
1558 else
1559 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
1560
1561 return 0;
1562 }
1563
1564 #define FBIMSTT_SETREG 0x545401
1565 #define FBIMSTT_GETREG 0x545402
1566 #define FBIMSTT_SETCMAPREG 0x545403
1567 #define FBIMSTT_GETCMAPREG 0x545404
1568 #define FBIMSTT_SETIDXREG 0x545405
1569 #define FBIMSTT_GETIDXREG 0x545406
1570
1571 static int
1572 imsttfb_ioctl (struct inode *inode, struct file *file, u_int cmd,
1573 u_long arg, int con, struct fb_info *info)
1574 {
1575 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1576 __u8 idx[2];
1577 __u32 reg[2];
1578
1579 switch (cmd) {
1580 case FBIMSTT_SETREG:
1581 if (copy_from_user(reg, (void *)arg, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1582 return -EFAULT;
1583 out_le32(&p->dc_regs[reg[0]], reg[1]);
1584 return 0;
1585 case FBIMSTT_GETREG:
1586 if (copy_from_user(reg, (void *)arg, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1587 return -EFAULT;
1588 reg[1] = in_le32(&p->dc_regs[reg[0]]);
1589 if (copy_to_user((void *)(arg + 4), ®[1], 4))
1590 return -EFAULT;
1591 return 0;
1592 case FBIMSTT_SETCMAPREG:
1593 if (copy_from_user(reg, (void *)arg, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1594 return -EFAULT;
1595 out_le32(&((u_int *)p->cmap_regs)[reg[0]], reg[1]);
1596 return 0;
1597 case FBIMSTT_GETCMAPREG:
1598 if (copy_from_user(reg, (void *)arg, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1599 return -EFAULT;
1600 reg[1] = in_le32(&((u_int *)p->cmap_regs)[reg[0]]);
1601 if (copy_to_user((void *)(arg + 4), ®[1], 4))
1602 return -EFAULT;
1603 return 0;
1604 case FBIMSTT_SETIDXREG:
1605 if (copy_from_user(idx, (void *)arg, 2))
1606 return -EFAULT;
1607 p->cmap_regs[PIDXHI] = 0; eieio();
1608 p->cmap_regs[PIDXLO] = idx[0]; eieio();
1609 p->cmap_regs[PIDXDATA] = idx[1]; eieio();
1610 return 0;
1611 case FBIMSTT_GETIDXREG:
1612 if (copy_from_user(idx, (void *)arg, 1))
1613 return -EFAULT;
1614 p->cmap_regs[PIDXHI] = 0; eieio();
1615 p->cmap_regs[PIDXLO] = idx[0]; eieio();
1616 idx[1] = p->cmap_regs[PIDXDATA];
1617 if (copy_to_user((void *)(arg + 1), &idx[1], 1))
1618 return -EFAULT;
1619 return 0;
1620 default:
1621 return -ENOIOCTLCMD;
1622 }
1623 }
1624
1625 static struct fb_ops imsttfb_ops = {
1626 owner: THIS_MODULE,
1627 fb_get_fix: imsttfb_get_fix,
1628 fb_get_var: imsttfb_get_var,
1629 fb_set_var: imsttfb_set_var,
1630 fb_get_cmap: imsttfb_get_cmap,
1631 fb_set_cmap: imsttfb_set_cmap,
1632 fb_pan_display: imsttfb_pan_display,
1633 fb_ioctl: imsttfb_ioctl,
1634 };
1635
1636 static int
1637 imsttfbcon_switch (int con, struct fb_info *info)
1638 {
1639 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1640 struct display *old = &fb_display[currcon], *new = &fb_display[con];
1641
1642 if (old->cmap.len)
1643 fb_get_cmap(&old->cmap, 1, imsttfb_getcolreg, info);
1644
1645 if (old->conp && old->conp->vc_sw && old->conp->vc_sw->con_cursor)
1646 old->conp->vc_sw->con_cursor(old->conp, CM_ERASE);
1647
1648 currcon = con;
1649
1650 if (old->var.xres != new->var.xres
1651 || old->var.yres != new->var.yres
1652 || old->var.bits_per_pixel != new->var.bits_per_pixel
1653 || old->var.green.length != new->var.green.length
1654 || old->var.accel_flags != new->var.accel_flags) {
1655 set_dispsw(new, p);
1656 if (!compute_imstt_regvals(p, new->var.xres, new->var.yres))
1657 return -1;
1658 if (new->var.bits_per_pixel == 16) {
1659 if (new->var.green.length == 6)
1660 set_565(p);
1661 else
1662 set_555(p);
1663 }
1664 set_imstt_regvals(p, new->var.bits_per_pixel);
1665 }
1666 set_offset(new, p);
1667
1668 imsttfbcon_set_font(new, fontwidth(new), fontheight(new));
1669
1670 do_install_cmap(con, info);
1671
1672 return 0;
1673 }
1674
1675 static int
1676 imsttfbcon_updatevar (int con, struct fb_info *info)
1677 {
1678 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1679 struct display *disp = &fb_display[con];
1680
1681 if (con != currcon)
1682 goto out;
1683
1684 if (p->ramdac == IBM)
1685 imsttfbcon_cursor(disp, CM_ERASE, p->cursor.x, p->cursor.y);
1686
1687 set_offset(disp, p);
1688
1689 out:
1690 return 0;
1691 }
1692
1693 static void
1694 imsttfbcon_blank (int blank, struct fb_info *info)
1695 {
1696 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1697 __u32 ctrl;
1698
1699 ctrl = in_le32(&p->dc_regs[STGCTL]);
1700 if (blank > 0) {
1701 switch (blank - 1) {
1702 case VESA_NO_BLANKING:
1703 case VESA_POWERDOWN:
1704 ctrl &= ~0x00000380;
1705 if (p->ramdac == IBM) {
1706 p->cmap_regs[PIDXHI] = 0; eieio();
1707 p->cmap_regs[PIDXLO] = MISCTL2; eieio();
1708 p->cmap_regs[PIDXDATA] = 0x55; eieio();
1709 p->cmap_regs[PIDXLO] = MISCTL1; eieio();
1710 p->cmap_regs[PIDXDATA] = 0x11; eieio();
1711 p->cmap_regs[PIDXLO] = SYNCCTL; eieio();
1712 p->cmap_regs[PIDXDATA] = 0x0f; eieio();
1713 p->cmap_regs[PIDXLO] = PWRMNGMT;eieio();
1714 p->cmap_regs[PIDXDATA] = 0x1f; eieio();
1715 p->cmap_regs[PIDXLO] = CLKCTL; eieio();
1716 p->cmap_regs[PIDXDATA] = 0xc0;
1717 }
1718 break;
1719 case VESA_VSYNC_SUSPEND:
1720 ctrl &= ~0x00000020;
1721 break;
1722 case VESA_HSYNC_SUSPEND:
1723 ctrl &= ~0x00000010;
1724 break;
1725 }
1726 } else {
1727 if (p->ramdac == IBM) {
1728 ctrl |= 0x000017b0;
1729 p->cmap_regs[PIDXHI] = 0; eieio();
1730 p->cmap_regs[PIDXLO] = CLKCTL; eieio();
1731 p->cmap_regs[PIDXDATA] = 0x01; eieio();
1732 p->cmap_regs[PIDXLO] = PWRMNGMT;eieio();
1733 p->cmap_regs[PIDXDATA] = 0x00; eieio();
1734 p->cmap_regs[PIDXLO] = SYNCCTL; eieio();
1735 p->cmap_regs[PIDXDATA] = 0x00; eieio();
1736 p->cmap_regs[PIDXLO] = MISCTL1; eieio();
1737 p->cmap_regs[PIDXDATA] = 0x01; eieio();
1738 p->cmap_regs[PIDXLO] = MISCTL2; eieio();
1739 p->cmap_regs[PIDXDATA] = 0x45; eieio();
1740 } else
1741 ctrl |= 0x00001780;
1742 }
1743 out_le32(&p->dc_regs[STGCTL], ctrl);
1744 }
1745
1746 static void __init
1747 init_imstt(struct fb_info_imstt *p)
1748 {
1749 __u32 i, tmp;
1750 __u32 *ip, *end;
1751
1752 tmp = in_le32(&p->dc_regs[PRC]);
1753 if (p->ramdac == IBM)
1754 p->total_vram = (tmp & 0x0004) ? 0x400000 : 0x200000;
1755 else
1756 p->total_vram = 0x800000;
1757
1758 ip = (__u32 *)p->frame_buffer;
1759 end = (__u32 *)(p->frame_buffer + p->total_vram);
1760 while (ip < end)
1761 *ip++ = 0;
1762
1763 /* initialize the card */
1764 tmp = in_le32(&p->dc_regs[STGCTL]);
1765 out_le32(&p->dc_regs[STGCTL], tmp & ~0x1);
1766 out_le32(&p->dc_regs[SSR], 0);
1767
1768 /* set default values for DAC registers */
1769 if (p->ramdac == IBM) {
1770 p->cmap_regs[PPMASK] = 0xff; eieio();
1771 p->cmap_regs[PIDXHI] = 0; eieio();
1772 for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) {
1773 p->cmap_regs[PIDXLO] = ibm_initregs[i].addr; eieio();
1774 p->cmap_regs[PIDXDATA] = ibm_initregs[i].value; eieio();
1775 }
1776 } else {
1777 for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) {
1778 p->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; eieio();
1779 p->cmap_regs[TVPIDATA] = tvp_initregs[i].value; eieio();
1780 }
1781 }
1782
1783 #if USE_NV_MODES && defined(CONFIG_PPC)
1784 {
1785 int vmode = init_vmode, cmode = init_cmode;
1786
1787 if (vmode == -1) {
1788 vmode = nvram_read_byte(NV_VMODE);
1789 if (vmode <= 0 || vmode > VMODE_MAX)
1790 vmode = VMODE_640_480_67;
1791 }
1792 if (cmode == -1) {
1793 cmode = nvram_read_byte(NV_CMODE);
1794 if (cmode < CMODE_8 || cmode > CMODE_32)
1795 cmode = CMODE_8;
1796 }
1797 if (mac_vmode_to_var(vmode, cmode, &p->disp.var)) {
1798 p->disp.var.xres = p->disp.var.xres_virtual = INIT_XRES;
1799 p->disp.var.yres = p->disp.var.yres_virtual = INIT_YRES;
1800 p->disp.var.bits_per_pixel = INIT_BPP;
1801 }
1802 }
1803 #else
1804 p->disp.var.xres = p->disp.var.xres_virtual = INIT_XRES;
1805 p->disp.var.yres = p->disp.var.yres_virtual = INIT_YRES;
1806 p->disp.var.bits_per_pixel = INIT_BPP;
1807 #endif
1808
1809 if ((p->disp.var.xres * p->disp.var.yres) * (p->disp.var.bits_per_pixel >> 3) > p->total_vram
1810 || !(compute_imstt_regvals(p, p->disp.var.xres, p->disp.var.yres))) {
1811 printk("imsttfb: %ux%ux%u not supported\n", p->disp.var.xres, p->disp.var.yres, p->disp.var.bits_per_pixel);
1812 kfree(p);
1813 return;
1814 }
1815
1816 sprintf(p->fix.id, "IMS TT (%s)", p->ramdac == IBM ? "IBM" : "TVP");
1817 p->fix.smem_start = p->frame_buffer_phys;
1818 p->fix.smem_len = p->total_vram;
1819 p->fix.mmio_start = p->dc_regs_phys;
1820 p->fix.mmio_len = 0x1000;
1821 p->fix.accel = FB_ACCEL_IMS_TWINTURBO;
1822 p->fix.type = FB_TYPE_PACKED_PIXELS;
1823 p->fix.visual = p->disp.var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1824 : FB_VISUAL_DIRECTCOLOR;
1825 p->fix.line_length = p->disp.var.xres * (p->disp.var.bits_per_pixel >> 3);
1826 p->fix.xpanstep = 8;
1827 p->fix.ypanstep = 1;
1828 p->fix.ywrapstep = 0;
1829
1830 p->disp.var.accel_flags = noaccel ? 0 : FB_ACCELF_TEXT;
1831 set_disp(&p->disp, p);
1832
1833 if (!noaccel && p->ramdac == IBM)
1834 imstt_cursor_init(p);
1835 if (p->disp.var.green.length == 6)
1836 set_565(p);
1837 else
1838 set_555(p);
1839 set_imstt_regvals(p, p->disp.var.bits_per_pixel);
1840
1841 p->disp.var.pixclock = 1000000 / getclkMHz(p);
1842
1843 strcpy(p->info.modename, p->fix.id);
1844 strcpy(p->info.fontname, fontname);
1845 p->info.node = -1;
1846 p->info.fbops = &imsttfb_ops;
1847 p->info.disp = &p->disp;
1848 p->info.changevar = 0;
1849 p->info.switch_con = &imsttfbcon_switch;
1850 p->info.updatevar = &imsttfbcon_updatevar;
1851 p->info.blank = &imsttfbcon_blank;
1852 p->info.flags = FBINFO_FLAG_DEFAULT;
1853
1854 for (i = 0; i < 16; i++) {
1855 u_int j = color_table[i];
1856 p->palette[i].red = default_red[j];
1857 p->palette[i].green = default_grn[j];
1858 p->palette[i].blue = default_blu[j];
1859 }
1860
1861 if (register_framebuffer(&p->info) < 0) {
1862 kfree(p);
1863 return;
1864 }
1865
1866 i = GET_FB_IDX(p->info.node);
1867 tmp = (in_le32(&p->dc_regs[SSTATUS]) & 0x0f00) >> 8;
1868 printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1869 i, p->fix.id, p->total_vram >> 20, tmp);
1870
1871 fb_info_imstt_p[i] = p;
1872 #ifdef CONFIG_FB_COMPAT_XPMAC
1873 strncpy(display_info.name, "IMS,tt128mb", sizeof(display_info.name));
1874 display_info.fb_address = p->frame_buffer_phys;
1875 display_info.cmap_adr_address = p->cmap_regs_phys + PADDRW;
1876 display_info.cmap_data_address = p->cmap_regs_phys + PDATA;
1877 display_info.disp_reg_address = p->dc_regs_phys;
1878 if (!console_fb_info)
1879 console_fb_info = &p->info;
1880 #endif /* CONFIG_FB_COMPAT_XPMAC */
1881 }
1882
1883 int __init
1884 imsttfb_init(void)
1885 {
1886 int i;
1887 struct pci_dev *pdev = NULL;
1888 struct fb_info_imstt *p;
1889 unsigned long addr, size;
1890 __u16 cmd;
1891
1892 while ((pdev = pci_find_device(PCI_VENDOR_ID_IMS, PCI_ANY_ID, pdev))) {
1893 if ((pdev->class >> 16) != PCI_BASE_CLASS_DISPLAY)
1894 continue;
1895 if (pci_enable_device(pdev))
1896 continue;
1897
1898 addr = pci_resource_start (pdev, 0);
1899 size = pci_resource_len (pdev, 0);
1900 if (!addr)
1901 continue;
1902
1903 p = kmalloc(sizeof(struct fb_info_imstt), GFP_ATOMIC);
1904 if (!p)
1905 continue;
1906 memset(p, 0, sizeof(struct fb_info_imstt));
1907
1908 if (!request_mem_region(addr, size, "imsttfb")) {
1909 kfree(p);
1910 continue;
1911 }
1912 printk("imsttfb: device=%04x\n", pdev->device);
1913
1914 switch (pdev->device) {
1915 case 0x9128: /* IMS,tt128mbA */
1916 p->ramdac = IBM;
1917 break;
1918 case 0x9135: /* IMS,tt3d */
1919 default:
1920 p->ramdac = TVP;
1921 break;
1922 }
1923
1924 p->frame_buffer_phys = addr;
1925 p->board_size = size;
1926 p->frame_buffer = (__u8 *)ioremap(addr, p->ramdac == IBM ? 0x400000 : 0x800000);
1927 p->dc_regs_phys = addr + 0x800000;
1928 p->dc_regs = (__u32 *)ioremap(addr + 0x800000, 0x1000);
1929 p->cmap_regs_phys = addr + 0x840000;
1930 p->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1931
1932 init_imstt(p);
1933 }
1934 for (i = 0; i < FB_MAX; i++) {
1935 if (fb_info_imstt_p[i])
1936 return 0;
1937 }
1938 return -ENXIO;
1939 }
1940
1941 #ifndef MODULE
1942 int __init
1943 imsttfb_setup(char *options)
1944 {
1945 char *this_opt;
1946
1947 if (!options || !*options)
1948 return 0;
1949
1950 for (this_opt = strtok(options, ","); this_opt;
1951 this_opt = strtok(NULL, ",")) {
1952 if (!strncmp(this_opt, "font:", 5)) {
1953 char *p;
1954 int i;
1955
1956 p = this_opt + 5;
1957 for (i = 0; i < sizeof(fontname) - 1; i++)
1958 if (!*p || *p == ' ' || *p == ',')
1959 break;
1960 memcpy(fontname, this_opt + 5, i);
1961 fontname[i] = 0;
1962 } else if (!strncmp(this_opt, "noblink", 7)) {
1963 curblink = 0;
1964 } else if (!strncmp(this_opt, "noaccel", 7)) {
1965 noaccel = 1;
1966 }
1967 #if defined(CONFIG_PPC)
1968 else if (!strncmp(this_opt, "vmode:", 6)) {
1969 int vmode = simple_strtoul(this_opt+6, NULL, 0);
1970 if (vmode > 0 && vmode <= VMODE_MAX)
1971 init_vmode = vmode;
1972 } else if (!strncmp(this_opt, "cmode:", 6)) {
1973 int cmode = simple_strtoul(this_opt+6, NULL, 0);
1974 switch (cmode) {
1975 case CMODE_8:
1976 case 8:
1977 init_cmode = CMODE_8;
1978 break;
1979 case CMODE_16:
1980 case 15:
1981 case 16:
1982 init_cmode = CMODE_16;
1983 break;
1984 case CMODE_32:
1985 case 24:
1986 case 32:
1987 init_cmode = CMODE_32;
1988 break;
1989 }
1990 }
1991 #endif
1992 }
1993 return 0;
1994 }
1995
1996 #else /* MODULE */
1997
1998 int __init
1999 init_module (void)
2000 {
2001
2002 return imsttfb_init();
2003 }
2004
2005 void
2006 cleanup_module (void)
2007 {
2008 struct fb_info_imstt *p;
2009 __u32 i;
2010
2011 for (i = 0; i < FB_MAX; i++) {
2012 p = fb_info_imstt_p[i];
2013 if (!p)
2014 continue;
2015 iounmap(p->cmap_regs);
2016 iounmap(p->dc_regs);
2017 iounmap(p->frame_buffer);
2018 kfree(p);
2019 release_mem_region(p->frame_buffer_phys, p->board_size);
2020 }
2021 }
2022
2023 #include "macmodes.c"
2024 #endif /* MODULE */
2025
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