1 /*
2 * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
5 *
6 * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive for
10 * more details.
11 */
12
13 #ifndef TGAFB_H
14 #define TGAFB_H
15
16 /*
17 * TGA hardware description (minimal)
18 */
19
20 #define TGA_TYPE_8PLANE 0
21 #define TGA_TYPE_24PLANE 1
22 #define TGA_TYPE_24PLUSZ 3
23
24 /*
25 * Offsets within Memory Space
26 */
27
28 #define TGA_ROM_OFFSET 0x0000000
29 #define TGA_REGS_OFFSET 0x0100000
30 #define TGA_8PLANE_FB_OFFSET 0x0200000
31 #define TGA_24PLANE_FB_OFFSET 0x0804000
32 #define TGA_24PLUSZ_FB_OFFSET 0x1004000
33
34 #define TGA_PLANEMASK_REG 0x0028
35 #define TGA_MODE_REG 0x0030
36 #define TGA_RASTEROP_REG 0x0034
37 #define TGA_PIXELSHIFT_REG 0x0038
38 #define TGA_DEEP_REG 0x0050
39 #define TGA_PIXELMASK_REG 0x005c
40 #define TGA_CURSOR_BASE_REG 0x0060
41 #define TGA_HORIZ_REG 0x0064
42 #define TGA_VERT_REG 0x0068
43 #define TGA_BASE_ADDR_REG 0x006c
44 #define TGA_VALID_REG 0x0070
45 #define TGA_CURSOR_XY_REG 0x0074
46 #define TGA_INTR_STAT_REG 0x007c
47 #define TGA_RAMDAC_SETUP_REG 0x00c0
48 #define TGA_BLOCK_COLOR0_REG 0x0140
49 #define TGA_BLOCK_COLOR1_REG 0x0144
50 #define TGA_CLOCK_REG 0x01e8
51 #define TGA_RAMDAC_REG 0x01f0
52 #define TGA_CMD_STAT_REG 0x01f8
53
54
55 /*
56 * useful defines for managing the registers
57 */
58
59 #define TGA_HORIZ_ODD 0x80000000
60 #define TGA_HORIZ_POLARITY 0x40000000
61 #define TGA_HORIZ_ACT_MSB 0x30000000
62 #define TGA_HORIZ_BP 0x0fe00000
63 #define TGA_HORIZ_SYNC 0x001fc000
64 #define TGA_HORIZ_FP 0x00007c00
65 #define TGA_HORIZ_ACT_LSB 0x000001ff
66
67 #define TGA_VERT_SE 0x80000000
68 #define TGA_VERT_POLARITY 0x40000000
69 #define TGA_VERT_RESERVED 0x30000000
70 #define TGA_VERT_BP 0x0fc00000
71 #define TGA_VERT_SYNC 0x003f0000
72 #define TGA_VERT_FP 0x0000f800
73 #define TGA_VERT_ACTIVE 0x000007ff
74
75 #define TGA_VALID_VIDEO 0x01
76 #define TGA_VALID_BLANK 0x02
77 #define TGA_VALID_CURSOR 0x04
78
79
80 /*
81 * useful defines for managing the ICS1562 PLL clock
82 */
83
84 #define TGA_PLL_BASE_FREQ 14318 /* .18 */
85 #define TGA_PLL_MAX_FREQ 230000
86
87
88 /*
89 * useful defines for managing the BT485 on the 8-plane TGA
90 */
91
92 #define BT485_READ_BIT 0x01
93 #define BT485_WRITE_BIT 0x00
94
95 #define BT485_ADDR_PAL_WRITE 0x00
96 #define BT485_DATA_PAL 0x02
97 #define BT485_PIXEL_MASK 0x04
98 #define BT485_ADDR_PAL_READ 0x06
99 #define BT485_ADDR_CUR_WRITE 0x08
100 #define BT485_DATA_CUR 0x0a
101 #define BT485_CMD_0 0x0c
102 #define BT485_ADDR_CUR_READ 0x0e
103 #define BT485_CMD_1 0x10
104 #define BT485_CMD_2 0x12
105 #define BT485_STATUS 0x14
106 #define BT485_CMD_3 0x14
107 #define BT485_CUR_RAM 0x16
108 #define BT485_CUR_LOW_X 0x18
109 #define BT485_CUR_HIGH_X 0x1a
110 #define BT485_CUR_LOW_Y 0x1c
111 #define BT485_CUR_HIGH_Y 0x1e
112
113
114 /*
115 * useful defines for managing the BT463 on the 24-plane TGAs
116 */
117
118 #define BT463_ADDR_LO 0x0
119 #define BT463_ADDR_HI 0x1
120 #define BT463_REG_ACC 0x2
121 #define BT463_PALETTE 0x3
122
123 #define BT463_CUR_CLR_0 0x0100
124 #define BT463_CUR_CLR_1 0x0101
125
126 #define BT463_CMD_REG_0 0x0201
127 #define BT463_CMD_REG_1 0x0202
128 #define BT463_CMD_REG_2 0x0203
129
130 #define BT463_READ_MASK_0 0x0205
131 #define BT463_READ_MASK_1 0x0206
132 #define BT463_READ_MASK_2 0x0207
133 #define BT463_READ_MASK_3 0x0208
134
135 #define BT463_BLINK_MASK_0 0x0209
136 #define BT463_BLINK_MASK_1 0x020a
137 #define BT463_BLINK_MASK_2 0x020b
138 #define BT463_BLINK_MASK_3 0x020c
139
140 #define BT463_WINDOW_TYPE_BASE 0x0300
141
142
143 /*
144 * Macros for reading/writing TGA and RAMDAC registers
145 */
146
147 #define TGA_WRITE_REG(v,r) \
148 { writel((v), fb_info.tga_regs_base+(r)); mb(); }
149
150 #define TGA_READ_REG(r) readl(fb_info.tga_regs_base+(r))
151
152 #define BT485_WRITE(v,r) \
153 TGA_WRITE_REG((r),TGA_RAMDAC_SETUP_REG); \
154 TGA_WRITE_REG(((v)&0xff)|((r)<<8),TGA_RAMDAC_REG);
155
156 #define BT463_LOAD_ADDR(a) \
157 TGA_WRITE_REG(BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG); \
158 TGA_WRITE_REG((BT463_ADDR_LO<<10)|((a)&0xff), TGA_RAMDAC_REG); \
159 TGA_WRITE_REG(BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG); \
160 TGA_WRITE_REG((BT463_ADDR_HI<<10)|(((a)>>8)&0xff), TGA_RAMDAC_REG);
161
162 #define BT463_WRITE(m,a,v) \
163 BT463_LOAD_ADDR((a)); \
164 TGA_WRITE_REG(((m)<<2),TGA_RAMDAC_SETUP_REG); \
165 TGA_WRITE_REG(((m)<<10)|((v)&0xff),TGA_RAMDAC_REG);
166
167
168 /*
169 * This structure describes the board.
170 */
171
172 struct tgafb_info {
173 /* Use the generic framebuffer ops */
174 struct fb_info_gen gen;
175
176 /* Device dependent information */
177 u8 tga_type; /* TGA_TYPE_XXX */
178 u8 tga_chip_rev; /* dc21030 revision */
179 u64 tga_mem_base;
180 u64 tga_fb_base;
181 u64 tga_regs_base;
182 struct fb_var_screeninfo default_var; /* default video mode */
183 };
184
185
186 /*
187 * This structure uniquely defines a video mode.
188 */
189
190 struct tgafb_par {
191 u32 xres, yres; /* resolution in pixels */
192 u32 htimings; /* horizontal timing register */
193 u32 vtimings; /* vertical timing register */
194 u32 pll_freq; /* pixclock in mhz */
195 u32 bits_per_pixel; /* bits per pixel */
196 u32 sync_on_green; /* set if sync is on green */
197 };
198
199 #endif /* TGAFB_H */
200
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