1 #ifndef _ALPHA_BYTEORDER_H
2 #define _ALPHA_BYTEORDER_H
3
4 #include <asm/types.h>
5
6 #ifdef __GNUC__
7
8 static __inline __u32 __attribute__((__const)) __arch__swab32(__u32 x)
9 {
10 /*
11 * Unfortunately, we can't use the 6 instruction sequence
12 * on ev6 since the latency of the UNPKBW is 3, which is
13 * pretty hard to hide. Just in case a future implementation
14 * has a lower latency, here's the sequence (also by Mike Burrows)
15 *
16 * UNPKBW a0, v0 v0: 00AA00BB00CC00DD
17 * SLL v0, 24, a0 a0: BB00CC00DD000000
18 * BIS v0, a0, a0 a0: BBAACCBBDDCC00DD
19 * EXTWL a0, 6, v0 v0: 000000000000BBAA
20 * ZAP a0, 0xf3, a0 a0: 00000000DDCC0000
21 * ADDL a0, v0, v0 v0: ssssssssDDCCBBAA
22 */
23
24 __u64 t0, t1, t2, t3;
25
26 __asm__("inslh %1, 7, %0" /* t0 : 0000000000AABBCC */
27 : "=r"(t0) : "r"(x));
28 __asm__("inswl %1, 3, %0" /* t1 : 000000CCDD000000 */
29 : "=r"(t1) : "r"(x));
30
31 t1 |= t0; /* t1 : 000000CCDDAABBCC */
32 t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */
33 t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */
34 t3 = t2 & 0x00FF00FF; /* t3 : 0000000000CC00AA */
35 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */
36
37 return t1;
38 }
39
40 #define __arch__swab32 __arch__swab32
41
42 #endif /* __GNUC__ */
43
44 #define __BYTEORDER_HAS_U64__
45
46 #include <linux/byteorder/little_endian.h>
47
48 #endif /* _ALPHA_BYTEORDER_H */
49
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