1 #ifndef __ALPHA_IRONGATE__H__
2 #define __ALPHA_IRONGATE__H__
3
4 #include <linux/types.h>
5 #include <asm/compiler.h>
6
7 /*
8 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
9 * which provides memory controller and PCI access for NAUTILUS-based
10 * EV6 (21264) systems.
11 *
12 * This file is based on:
13 *
14 * IronGate management library, (c) 1999 Alpha Processor, Inc.
15 * Copyright (C) 1999 Alpha Processor, Inc.,
16 * (David Daniel, Stig Telfer, Soohoon Lee)
17 */
18
19 /*
20 * The 21264 supports, and internally recognizes, a 44-bit physical
21 * address space that is divided equally between memory address space
22 * and I/O address space. Memory address space resides in the lower
23 * half of the physical address space (PA[43]=0) and I/O address space
24 * resides in the upper half of the physical address space (PA[43]=1).
25 */
26
27 /*
28 * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
29 * through the routines given is 32-bit.
30 *
31 * The first 0x40 bytes are standard as per the PCI spec.
32 */
33
34 typedef volatile __u32 igcsr32;
35
36 typedef struct {
37 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
38 igcsr32 stat_cmd; /* 0x04 - status, command */
39 igcsr32 class; /* 0x08 - class code, rev ID */
40 igcsr32 latency; /* 0x0C - header type, PCI latency */
41 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
42 igcsr32 bar1; /* 0x14 - BAR1 - GART */
43 igcsr32 bar2; /* 0x18 - Power Management reg block */
44
45 igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
46
47 igcsr32 capptr; /* 0x34 - Capabilities pointer */
48
49 igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
50
51 igcsr32 bacsr10; /* 0x40 - base address chip selects */
52 igcsr32 bacsr32; /* 0x44 - base address chip selects */
53 igcsr32 bacsr54; /* 0x48 - base address chip selects */
54
55 igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
56
57 igcsr32 drammap; /* 0x50 - address mapping control */
58 igcsr32 dramtm; /* 0x54 - timing, driver strength */
59 igcsr32 dramms; /* 0x58 - ECC, mode/status */
60
61 igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
62
63 igcsr32 biu0; /* 0x60 - bus interface unit */
64 igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
65
66 igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
67
68 igcsr32 mro; /* 0x70 - memory request optimiser */
69
70 igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
71
72 igcsr32 whami; /* 0x80 - who am I */
73 igcsr32 pciarb; /* 0x84 - PCI arbitration control */
74 igcsr32 pcicfg; /* 0x88 - PCI config status */
75
76 igcsr32 rsrvd6[5]; /* 0x8C-0x9F reserved */
77
78 /* AGP (bus 1) control registers */
79 igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
80 igcsr32 agpstat; /* 0xA4 - AGP status register */
81 igcsr32 agpcmd; /* 0xA8 - AGP control register */
82 igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
83 igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
84 } Irongate0;
85
86
87 typedef struct {
88
89 igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
90 igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
91 igcsr32 class; /* 0x08 - subclass, baseclass etc */
92 igcsr32 htype; /* 0x0C - header type (at 0x0E) */
93 igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
94 igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
95 igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
96 igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
97 igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
98 igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
99 igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
100 igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
101 igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
102
103 } Irongate1;
104
105
106 /*
107 * Memory spaces:
108 */
109
110 /* Irongate is consistent with a subset of the Tsunami memory map */
111 #ifdef USE_48_BIT_KSEG
112 #define IRONGATE_BIAS 0x80000000000UL
113 #else
114 #define IRONGATE_BIAS 0x10000000000UL
115 #endif
116
117
118 #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
119 #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
120 #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
121 #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
122
123 /*
124 * PCI Configuration space accesses are formed like so:
125 *
126 * 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
127 * : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
128 * ---bus numer--- -device-- -fun- ---register----
129 */
130
131 #define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \
132 ((dev)<<11) | \
133 ((fun)<<8) | \
134 (reg) )
135
136 #define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0))
137 #define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0))
138
139 /*
140 * Data structure for handling IRONGATE machine checks:
141 * This is the standard OSF logout frame
142 */
143
144 #define SCB_Q_SYSERR 0x620 /* OSF definitions */
145 #define SCB_Q_PROCERR 0x630
146 #define SCB_Q_SYSMCHK 0x660
147 #define SCB_Q_PROCMCHK 0x670
148
149 struct el_IRONGATE_sysdata_mcheck {
150 __u32 FrameSize; /* Bytes, including this field */
151 __u32 FrameFlags; /* <31> = Retry, <30> = Second Error */
152 __u32 CpuOffset; /* Offset to CPU-specific into */
153 __u32 SystemOffset; /* Offset to system-specific info */
154 __u32 MCHK_Code;
155 __u32 MCHK_Frame_Rev;
156 __u64 I_STAT;
157 __u64 DC_STAT;
158 __u64 C_ADDR;
159 __u64 DC1_SYNDROME;
160 __u64 DC0_SYNDROME;
161 __u64 C_STAT;
162 __u64 C_STS;
163 __u64 RESERVED0;
164 __u64 EXC_ADDR;
165 __u64 IER_CM;
166 __u64 ISUM;
167 __u64 MM_STAT;
168 __u64 PAL_BASE;
169 __u64 I_CTL;
170 __u64 PCTX;
171 };
172
173
174 #ifdef __KERNEL__
175
176 #ifndef __EXTERN_INLINE
177 #define __EXTERN_INLINE extern inline
178 #define __IO_EXTERN_INLINE
179 #endif
180
181 /*
182 * I/O functions:
183 *
184 * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
185 * K7 can only use linear accesses to get at PCI memory and I/O spaces.
186 */
187
188 #define vucp volatile unsigned char *
189 #define vusp volatile unsigned short *
190 #define vuip volatile unsigned int *
191 #define vulp volatile unsigned long *
192
193 __EXTERN_INLINE unsigned int irongate_inb(unsigned long addr)
194 {
195 return __kernel_ldbu(*(vucp)(addr + IRONGATE_IO));
196 }
197
198 __EXTERN_INLINE void irongate_outb(unsigned char b, unsigned long addr)
199 {
200 __kernel_stb(b, *(vucp)(addr + IRONGATE_IO));
201 mb();
202 }
203
204 __EXTERN_INLINE unsigned int irongate_inw(unsigned long addr)
205 {
206 return __kernel_ldwu(*(vusp)(addr + IRONGATE_IO));
207 }
208
209 __EXTERN_INLINE void irongate_outw(unsigned short b, unsigned long addr)
210 {
211 __kernel_stw(b, *(vusp)(addr + IRONGATE_IO));
212 mb();
213 }
214
215 __EXTERN_INLINE unsigned int irongate_inl(unsigned long addr)
216 {
217 return *(vuip)(addr + IRONGATE_IO);
218 }
219
220 __EXTERN_INLINE void irongate_outl(unsigned int b, unsigned long addr)
221 {
222 *(vuip)(addr + IRONGATE_IO) = b;
223 mb();
224 }
225
226 /*
227 * Memory functions. All accesses are done through linear space.
228 */
229
230 __EXTERN_INLINE unsigned long irongate_readb(unsigned long addr)
231 {
232 return __kernel_ldbu(*(vucp)addr);
233 }
234
235 __EXTERN_INLINE unsigned long irongate_readw(unsigned long addr)
236 {
237 return __kernel_ldwu(*(vusp)addr);
238 }
239
240 __EXTERN_INLINE unsigned long irongate_readl(unsigned long addr)
241 {
242 return *(vuip)addr;
243 }
244
245 __EXTERN_INLINE unsigned long irongate_readq(unsigned long addr)
246 {
247 return *(vulp)addr;
248 }
249
250 __EXTERN_INLINE void irongate_writeb(unsigned char b, unsigned long addr)
251 {
252 __kernel_stb(b, *(vucp)addr);
253 }
254
255 __EXTERN_INLINE void irongate_writew(unsigned short b, unsigned long addr)
256 {
257 __kernel_stw(b, *(vusp)addr);
258 }
259
260 __EXTERN_INLINE void irongate_writel(unsigned int b, unsigned long addr)
261 {
262 *(vuip)addr = b;
263 }
264
265 __EXTERN_INLINE void irongate_writeq(unsigned long b, unsigned long addr)
266 {
267 *(vulp)addr = b;
268 }
269
270 __EXTERN_INLINE unsigned long irongate_ioremap(unsigned long addr)
271 {
272 return addr + IRONGATE_MEM;
273 }
274
275 __EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
276 {
277 return addr >= IRONGATE_MEM;
278 }
279
280 #undef vucp
281 #undef vusp
282 #undef vuip
283 #undef vulp
284
285 #ifdef __WANT_IO_DEF
286
287 #define __inb(p) irongate_inb((unsigned long)(p))
288 #define __inw(p) irongate_inw((unsigned long)(p))
289 #define __inl(p) irongate_inl((unsigned long)(p))
290 #define __outb(x,p) irongate_outb((x),(unsigned long)(p))
291 #define __outw(x,p) irongate_outw((x),(unsigned long)(p))
292 #define __outl(x,p) irongate_outl((x),(unsigned long)(p))
293 #define __readb(a) irongate_readb((unsigned long)(a))
294 #define __readw(a) irongate_readw((unsigned long)(a))
295 #define __readl(a) irongate_readl((unsigned long)(a))
296 #define __readq(a) irongate_readq((unsigned long)(a))
297 #define __writeb(x,a) irongate_writeb((x),(unsigned long)(a))
298 #define __writew(x,a) irongate_writew((x),(unsigned long)(a))
299 #define __writel(x,a) irongate_writel((x),(unsigned long)(a))
300 #define __writeq(x,a) irongate_writeq((x),(unsigned long)(a))
301 #define __ioremap(a) irongate_ioremap((unsigned long)(a))
302 #define __is_ioaddr(a) irongate_is_ioaddr((unsigned long)(a))
303
304 #define inb(p) __inb(p)
305 #define inw(p) __inw(p)
306 #define inl(p) __inl(p)
307 #define outb(x,p) __outb((x),(p))
308 #define outw(x,p) __outw((x),(p))
309 #define outl(x,p) __outl((x),(p))
310 #define __raw_readb(a) __readb(a)
311 #define __raw_readw(a) __readw(a)
312 #define __raw_readl(a) __readl(a)
313 #define __raw_readq(a) __readq(a)
314 #define __raw_writeb(v,a) __writeb((v),(a))
315 #define __raw_writew(v,a) __writew((v),(a))
316 #define __raw_writel(v,a) __writel((v),(a))
317 #define __raw_writeq(v,a) __writeq((v),(a))
318
319 #endif /* __WANT_IO_DEF */
320
321 #ifdef __IO_EXTERN_INLINE
322 #undef __EXTERN_INLINE
323 #undef __IO_EXTERN_INLINE
324 #endif
325
326 #endif /* __KERNEL__ */
327
328 #endif /* __ALPHA_IRONGATE__H__ */
329
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.