1 #ifndef __ALPHA_MCPCIA__H__
2 #define __ALPHA_MCPCIA__H__
3
4 /* Define to experiment with fitting everything into one 128MB HAE window.
5 One window per bus, that is. */
6 #define MCPCIA_ONE_HAE_WINDOW 1
7
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <asm/compiler.h>
11
12 /*
13 * MCPCIA is the internal name for a core logic chipset which provides
14 * PCI access for the RAWHIDE family of systems.
15 *
16 * This file is based on:
17 *
18 * RAWHIDE System Programmer's Manual
19 * 16-May-96
20 * Rev. 1.4
21 *
22 */
23
24 /*------------------------------------------------------------------------**
25 ** **
26 ** I/O procedures **
27 ** **
28 ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
29 ** inportbxt: 8 bits only **
30 ** inport: alias of inportw **
31 ** outport: alias of outportw **
32 ** **
33 ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
34 ** inmembxt: 8 bits only **
35 ** inmem: alias of inmemw **
36 ** outmem: alias of outmemw **
37 ** **
38 **------------------------------------------------------------------------*/
39
40
41 /* MCPCIA ADDRESS BIT DEFINITIONS
42 *
43 * 3333 3333 3322 2222 2222 1111 1111 11
44 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
45 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
46 * 1 000
47 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
48 * | |\|
49 * | Byte Enable --+ |
50 * | Transfer Length --+
51 * +-- IO space, not cached
52 *
53 * Byte Transfer
54 * Enable Length Transfer Byte Address
55 * adr<6:5> adr<4:3> Length Enable Adder
56 * ---------------------------------------------
57 * 00 00 Byte 1110 0x000
58 * 01 00 Byte 1101 0x020
59 * 10 00 Byte 1011 0x040
60 * 11 00 Byte 0111 0x060
61 *
62 * 00 01 Word 1100 0x008
63 * 01 01 Word 1001 0x028 <= Not supported in this code.
64 * 10 01 Word 0011 0x048
65 *
66 * 00 10 Tribyte 1000 0x010
67 * 01 10 Tribyte 0001 0x030
68 *
69 * 10 11 Longword 0000 0x058
70 *
71 * Note that byte enables are asserted low.
72 *
73 */
74
75 #define MCPCIA_MID(m) ((unsigned long)(m) << 33)
76
77 /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
78 Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
79 #define MCPCIA_HOSE2MID(h) ((h) + 4)
80
81 #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
82
83 /*
84 * Memory spaces:
85 */
86 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
87 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
88 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
89 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
90 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
91 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
92 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
93 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
94
95 /*
96 * General Registers
97 */
98 #define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
99 #define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
100 #define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
101 #define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
102 #define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
103 #define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
104 #define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
105 #define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
106
107 /*
108 * Interrupt Control registers
109 */
110 #define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
111 #define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
112 #define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
113 #define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
114 #define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
115 #define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
116 #define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
117 #define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
118 #define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
119
120 /*
121 * Performance Monitor registers
122 */
123 #define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
124 #define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
125
126 /*
127 * Diagnostic Registers
128 */
129 #define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
130 #define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
131
132 /*
133 * Error registers
134 */
135 #define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
136 #define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
137 #define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
138 #define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
139 #define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
140 #define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
141 #define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
142 #define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
143 #define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
144 #define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
145
146 /*
147 * PCI Address Translation Registers.
148 */
149 #define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
150 #define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
151
152 #define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
153 #define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
154 #define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
155
156 #define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
157 #define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
158 #define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
159
160 #define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
161 #define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
162 #define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
163
164 #define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
165 #define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
166 #define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
167
168 /* Hack! Only words for bus 0. */
169
170 #if !MCPCIA_ONE_HAE_WINDOW
171 #define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
172 #endif
173 #define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
174
175 /*
176 * The canonical non-remaped I/O and MEM addresses have these values
177 * subtracted out. This is arranged so that folks manipulating ISA
178 * devices can use their familiar numbers and have them map to bus 0.
179 */
180
181 #define MCPCIA_IO_BIAS MCPCIA_IO(4)
182 #define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
183
184
185 /*
186 * Data structure for handling MCPCIA machine checks:
187 */
188 struct el_MCPCIA_uncorrected_frame_mcheck {
189 struct el_common header;
190 struct el_common_EV5_uncorrectable_mcheck procdata;
191 };
192
193
194 #ifdef __KERNEL__
195
196 #ifndef __EXTERN_INLINE
197 #define __EXTERN_INLINE extern inline
198 #define __IO_EXTERN_INLINE
199 #endif
200
201 /*
202 * I/O functions:
203 *
204 * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
205 * and EV56 (21164a) processors, can use either a sparse address mapping
206 * scheme, or the so-called byte-word PCI address space, to get at PCI memory
207 * and I/O.
208 *
209 * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
210 */
211
212 #define vucp volatile unsigned char *
213 #define vusp volatile unsigned short *
214 #define vip volatile int *
215 #define vuip volatile unsigned int *
216 #define vulp volatile unsigned long *
217
218 __EXTERN_INLINE unsigned int mcpcia_inb(unsigned long in_addr)
219 {
220 unsigned long addr, hose, result;
221
222 addr = in_addr & 0xffffUL;
223 hose = in_addr & ~0xffffUL;
224
225 /* ??? I wish I could get rid of this. But there's no ioremap
226 equivalent for I/O space. PCI I/O can be forced into the
227 correct hose's I/O region, but that doesn't take care of
228 legacy ISA crap. */
229 hose += MCPCIA_IO_BIAS;
230
231 result = *(vip) ((addr << 5) + hose + 0x00);
232 return __kernel_extbl(result, addr & 3);
233 }
234
235 __EXTERN_INLINE void mcpcia_outb(unsigned char b, unsigned long in_addr)
236 {
237 unsigned long addr, hose, w;
238
239 addr = in_addr & 0xffffUL;
240 hose = in_addr & ~0xffffUL;
241 hose += MCPCIA_IO_BIAS;
242
243 w = __kernel_insbl(b, addr & 3);
244 *(vuip) ((addr << 5) + hose + 0x00) = w;
245 mb();
246 }
247
248 __EXTERN_INLINE unsigned int mcpcia_inw(unsigned long in_addr)
249 {
250 unsigned long addr, hose, result;
251
252 addr = in_addr & 0xffffUL;
253 hose = in_addr & ~0xffffUL;
254 hose += MCPCIA_IO_BIAS;
255
256 result = *(vip) ((addr << 5) + hose + 0x08);
257 return __kernel_extwl(result, addr & 3);
258 }
259
260 __EXTERN_INLINE void mcpcia_outw(unsigned short b, unsigned long in_addr)
261 {
262 unsigned long addr, hose, w;
263
264 addr = in_addr & 0xffffUL;
265 hose = in_addr & ~0xffffUL;
266 hose += MCPCIA_IO_BIAS;
267
268 w = __kernel_inswl(b, addr & 3);
269 *(vuip) ((addr << 5) + hose + 0x08) = w;
270 mb();
271 }
272
273 __EXTERN_INLINE unsigned int mcpcia_inl(unsigned long in_addr)
274 {
275 unsigned long addr, hose;
276
277 addr = in_addr & 0xffffUL;
278 hose = in_addr & ~0xffffUL;
279 hose += MCPCIA_IO_BIAS;
280
281 return *(vuip) ((addr << 5) + hose + 0x18);
282 }
283
284 __EXTERN_INLINE void mcpcia_outl(unsigned int b, unsigned long in_addr)
285 {
286 unsigned long addr, hose;
287
288 addr = in_addr & 0xffffUL;
289 hose = in_addr & ~0xffffUL;
290 hose += MCPCIA_IO_BIAS;
291
292 *(vuip) ((addr << 5) + hose + 0x18) = b;
293 mb();
294 }
295
296
297 /*
298 * Memory functions. 64-bit and 32-bit accesses are done through
299 * dense memory space, everything else through sparse space.
300 *
301 * For reading and writing 8 and 16 bit quantities we need to
302 * go through one of the three sparse address mapping regions
303 * and use the HAE_MEM CSR to provide some bits of the address.
304 * The following few routines use only sparse address region 1
305 * which gives 1Gbyte of accessible space which relates exactly
306 * to the amount of PCI memory mapping *into* system address space.
307 * See p 6-17 of the specification but it looks something like this:
308 *
309 * 21164 Address:
310 *
311 * 3 2 1
312 * 9876543210987654321098765432109876543210
313 * 1ZZZZ0.PCI.QW.Address............BBLL
314 *
315 * ZZ = SBZ
316 * BB = Byte offset
317 * LL = Transfer length
318 *
319 * PCI Address:
320 *
321 * 3 2 1
322 * 10987654321098765432109876543210
323 * HHH....PCI.QW.Address........ 00
324 *
325 * HHH = 31:29 HAE_MEM CSR
326 *
327 */
328
329 __EXTERN_INLINE unsigned long mcpcia_ioremap(unsigned long addr)
330 {
331 return addr + MCPCIA_MEM_BIAS;
332 }
333
334 __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
335 {
336 return addr >= MCPCIA_SPARSE(0);
337 }
338
339 __EXTERN_INLINE unsigned long mcpcia_readb(unsigned long in_addr)
340 {
341 unsigned long addr = in_addr & 0xffffffffUL;
342 unsigned long hose = in_addr & ~0xffffffffUL;
343 unsigned long result, work;
344
345 #if !MCPCIA_ONE_HAE_WINDOW
346 unsigned long msb;
347 msb = addr & ~MCPCIA_MEM_MASK;
348 set_hae(msb);
349 #endif
350 addr = addr & MCPCIA_MEM_MASK;
351
352 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
353 work = ((addr << 5) + hose + 0x00);
354 result = *(vip) work;
355 return __kernel_extbl(result, addr & 3);
356 }
357
358 __EXTERN_INLINE unsigned long mcpcia_readw(unsigned long in_addr)
359 {
360 unsigned long addr = in_addr & 0xffffffffUL;
361 unsigned long hose = in_addr & ~0xffffffffUL;
362 unsigned long result, work;
363
364 #if !MCPCIA_ONE_HAE_WINDOW
365 unsigned long msb;
366 msb = addr & ~MCPCIA_MEM_MASK;
367 set_hae(msb);
368 #endif
369 addr = addr & MCPCIA_MEM_MASK;
370
371 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
372 work = ((addr << 5) + hose + 0x08);
373 result = *(vip) work;
374 return __kernel_extwl(result, addr & 3);
375 }
376
377 __EXTERN_INLINE void mcpcia_writeb(unsigned char b, unsigned long in_addr)
378 {
379 unsigned long addr = in_addr & 0xffffffffUL;
380 unsigned long hose = in_addr & ~0xffffffffUL;
381 unsigned long w;
382
383 #if !MCPCIA_ONE_HAE_WINDOW
384 unsigned long msb;
385 msb = addr & ~MCPCIA_MEM_MASK;
386 set_hae(msb);
387 #endif
388 addr = addr & MCPCIA_MEM_MASK;
389
390 w = __kernel_insbl(b, in_addr & 3);
391 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
392 *(vuip) ((addr << 5) + hose + 0x00) = w;
393 }
394
395 __EXTERN_INLINE void mcpcia_writew(unsigned short b, unsigned long in_addr)
396 {
397 unsigned long addr = in_addr & 0xffffffffUL;
398 unsigned long hose = in_addr & ~0xffffffffUL;
399 unsigned long w;
400
401 #if !MCPCIA_ONE_HAE_WINDOW
402 unsigned long msb;
403 msb = addr & ~MCPCIA_MEM_MASK;
404 set_hae(msb);
405 #endif
406 addr = addr & MCPCIA_MEM_MASK;
407
408 w = __kernel_inswl(b, in_addr & 3);
409 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
410 *(vuip) ((addr << 5) + hose + 0x08) = w;
411 }
412
413 __EXTERN_INLINE unsigned long mcpcia_readl(unsigned long addr)
414 {
415 return *(vuip)addr;
416 }
417
418 __EXTERN_INLINE unsigned long mcpcia_readq(unsigned long addr)
419 {
420 return *(vulp)addr;
421 }
422
423 __EXTERN_INLINE void mcpcia_writel(unsigned int b, unsigned long addr)
424 {
425 *(vuip)addr = b;
426 }
427
428 __EXTERN_INLINE void mcpcia_writeq(unsigned long b, unsigned long addr)
429 {
430 *(vulp)addr = b;
431 }
432
433 #undef vucp
434 #undef vusp
435 #undef vip
436 #undef vuip
437 #undef vulp
438
439 #ifdef __WANT_IO_DEF
440
441 #define __inb(p) mcpcia_inb((unsigned long)(p))
442 #define __inw(p) mcpcia_inw((unsigned long)(p))
443 #define __inl(p) mcpcia_inl((unsigned long)(p))
444 #define __outb(x,p) mcpcia_outb((x),(unsigned long)(p))
445 #define __outw(x,p) mcpcia_outw((x),(unsigned long)(p))
446 #define __outl(x,p) mcpcia_outl((x),(unsigned long)(p))
447 #define __readb(a) mcpcia_readb((unsigned long)(a))
448 #define __readw(a) mcpcia_readw((unsigned long)(a))
449 #define __readl(a) mcpcia_readl((unsigned long)(a))
450 #define __readq(a) mcpcia_readq((unsigned long)(a))
451 #define __writeb(x,a) mcpcia_writeb((x),(unsigned long)(a))
452 #define __writew(x,a) mcpcia_writew((x),(unsigned long)(a))
453 #define __writel(x,a) mcpcia_writel((x),(unsigned long)(a))
454 #define __writeq(x,a) mcpcia_writeq((x),(unsigned long)(a))
455 #define __ioremap(a) mcpcia_ioremap((unsigned long)(a))
456 #define __is_ioaddr(a) mcpcia_is_ioaddr((unsigned long)(a))
457
458 #define __raw_readl(a) __readl(a)
459 #define __raw_readq(a) __readq(a)
460 #define __raw_writel(v,a) __writel((v),(a))
461 #define __raw_writeq(v,a) __writeq((v),(a))
462
463 #endif /* __WANT_IO_DEF */
464
465 #ifdef __IO_EXTERN_INLINE
466 #undef __EXTERN_INLINE
467 #undef __IO_EXTERN_INLINE
468 #endif
469
470 #endif /* __KERNEL__ */
471
472 #endif /* __ALPHA_MCPCIA__H__ */
473
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