1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
3
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0x0F<<24)
15 #define GET_APIC_ID(x) (((x)>>24)&0x0F)
16 #define APIC_LVR 0x30
17 #define APIC_LVR_MASK 0xFF00FF
18 #define GET_APIC_VERSION(x) ((x)&0xFF)
19 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
20 #define APIC_INTEGRATED(x) ((x)&0xF0)
21 #define APIC_TASKPRI 0x80
22 #define APIC_TPRI_MASK 0xFF
23 #define APIC_ARBPRI 0x90
24 #define APIC_ARBPRI_MASK 0xFF
25 #define APIC_PROCPRI 0xA0
26 #define APIC_EOI 0xB0
27 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
28 #define APIC_RRR 0xC0
29 #define APIC_LDR 0xD0
30 #define APIC_LDR_MASK (0xFF<<24)
31 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
32 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
33 #define APIC_ALL_CPUS 0xFF
34 #define APIC_DFR 0xE0
35 #define APIC_SPIV 0xF0
36 #define APIC_ISR 0x100
37 #define APIC_TMR 0x180
38 #define APIC_IRR 0x200
39 #define APIC_ESR 0x280
40 #define APIC_ESR_SEND_CS 0x00001
41 #define APIC_ESR_RECV_CS 0x00002
42 #define APIC_ESR_SEND_ACC 0x00004
43 #define APIC_ESR_RECV_ACC 0x00008
44 #define APIC_ESR_SENDILL 0x00020
45 #define APIC_ESR_RECVILL 0x00040
46 #define APIC_ESR_ILLREGA 0x00080
47 #define APIC_ICR 0x300
48 #define APIC_DEST_SELF 0x40000
49 #define APIC_DEST_ALLINC 0x80000
50 #define APIC_DEST_ALLBUT 0xC0000
51 #define APIC_ICR_RR_MASK 0x30000
52 #define APIC_ICR_RR_INVALID 0x00000
53 #define APIC_ICR_RR_INPROG 0x10000
54 #define APIC_ICR_RR_VALID 0x20000
55 #define APIC_INT_LEVELTRIG 0x08000
56 #define APIC_INT_ASSERT 0x04000
57 #define APIC_ICR_BUSY 0x01000
58 #define APIC_DEST_LOGICAL 0x00800
59 #define APIC_DM_FIXED 0x00000
60 #define APIC_DM_LOWEST 0x00100
61 #define APIC_DM_SMI 0x00200
62 #define APIC_DM_REMRD 0x00300
63 #define APIC_DM_NMI 0x00400
64 #define APIC_DM_INIT 0x00500
65 #define APIC_DM_STARTUP 0x00600
66 #define APIC_DM_EXTINT 0x00700
67 #define APIC_VECTOR_MASK 0x000FF
68 #define APIC_ICR2 0x310
69 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
70 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
71 #define APIC_LVTT 0x320
72 #define APIC_LVTPC 0x340
73 #define APIC_LVT0 0x350
74 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
75 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
76 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
77 #define APIC_TIMER_BASE_CLKIN 0x0
78 #define APIC_TIMER_BASE_TMBASE 0x1
79 #define APIC_TIMER_BASE_DIV 0x2
80 #define APIC_LVT_TIMER_PERIODIC (1<<17)
81 #define APIC_LVT_MASKED (1<<16)
82 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
83 #define APIC_LVT_REMOTE_IRR (1<<14)
84 #define APIC_INPUT_POLARITY (1<<13)
85 #define APIC_SEND_PENDING (1<<12)
86 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
87 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
88 #define APIC_MODE_FIXED 0x0
89 #define APIC_MODE_NMI 0x4
90 #define APIC_MODE_EXINT 0x7
91 #define APIC_LVT1 0x360
92 #define APIC_LVTERR 0x370
93 #define APIC_TMICT 0x380
94 #define APIC_TMCCT 0x390
95 #define APIC_TDCR 0x3E0
96 #define APIC_TDR_DIV_TMBASE (1<<2)
97 #define APIC_TDR_DIV_1 0xB
98 #define APIC_TDR_DIV_2 0x0
99 #define APIC_TDR_DIV_4 0x1
100 #define APIC_TDR_DIV_8 0x2
101 #define APIC_TDR_DIV_16 0x3
102 #define APIC_TDR_DIV_32 0x8
103 #define APIC_TDR_DIV_64 0x9
104 #define APIC_TDR_DIV_128 0xA
105
106 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
107
108 #define MAX_IO_APICS 8
109
110 /*
111 * the local APIC register structure, memory mapped. Not terribly well
112 * tested, but we might eventually use this one in the future - the
113 * problem why we cannot use it right now is the P5 APIC, it has an
114 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
115 */
116 #define u32 unsigned int
117
118 #define lapic ((volatile struct local_apic *)APIC_BASE)
119
120 struct local_apic {
121
122 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
123
124 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
125
126 /*020*/ struct { /* APIC ID Register */
127 u32 __reserved_1 : 24,
128 phys_apic_id : 4,
129 __reserved_2 : 4;
130 u32 __reserved[3];
131 } id;
132
133 /*030*/ const
134 struct { /* APIC Version Register */
135 u32 version : 8,
136 __reserved_1 : 8,
137 max_lvt : 8,
138 __reserved_2 : 8;
139 u32 __reserved[3];
140 } version;
141
142 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
143
144 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
145
146 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
147
148 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
149
150 /*080*/ struct { /* Task Priority Register */
151 u32 priority : 8,
152 __reserved_1 : 24;
153 u32 __reserved_2[3];
154 } tpr;
155
156 /*090*/ const
157 struct { /* Arbitration Priority Register */
158 u32 priority : 8,
159 __reserved_1 : 24;
160 u32 __reserved_2[3];
161 } apr;
162
163 /*0A0*/ const
164 struct { /* Processor Priority Register */
165 u32 priority : 8,
166 __reserved_1 : 24;
167 u32 __reserved_2[3];
168 } ppr;
169
170 /*0B0*/ struct { /* End Of Interrupt Register */
171 u32 eoi;
172 u32 __reserved[3];
173 } eoi;
174
175 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
176
177 /*0D0*/ struct { /* Logical Destination Register */
178 u32 __reserved_1 : 24,
179 logical_dest : 8;
180 u32 __reserved_2[3];
181 } ldr;
182
183 /*0E0*/ struct { /* Destination Format Register */
184 u32 __reserved_1 : 28,
185 model : 4;
186 u32 __reserved_2[3];
187 } dfr;
188
189 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
190 u32 spurious_vector : 8,
191 apic_enabled : 1,
192 focus_cpu : 1,
193 __reserved_2 : 22;
194 u32 __reserved_3[3];
195 } svr;
196
197 /*100*/ struct { /* In Service Register */
198 /*170*/ u32 bitfield;
199 u32 __reserved[3];
200 } isr [8];
201
202 /*180*/ struct { /* Trigger Mode Register */
203 /*1F0*/ u32 bitfield;
204 u32 __reserved[3];
205 } tmr [8];
206
207 /*200*/ struct { /* Interrupt Request Register */
208 /*270*/ u32 bitfield;
209 u32 __reserved[3];
210 } irr [8];
211
212 /*280*/ union { /* Error Status Register */
213 struct {
214 u32 send_cs_error : 1,
215 receive_cs_error : 1,
216 send_accept_error : 1,
217 receive_accept_error : 1,
218 __reserved_1 : 1,
219 send_illegal_vector : 1,
220 receive_illegal_vector : 1,
221 illegal_register_address : 1,
222 __reserved_2 : 24;
223 u32 __reserved_3[3];
224 } error_bits;
225 struct {
226 u32 errors;
227 u32 __reserved_3[3];
228 } all_errors;
229 } esr;
230
231 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
232
233 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
234
235 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
236
237 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
238
239 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
240
241 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
242
243 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
244
245 /*300*/ struct { /* Interrupt Command Register 1 */
246 u32 vector : 8,
247 delivery_mode : 3,
248 destination_mode : 1,
249 delivery_status : 1,
250 __reserved_1 : 1,
251 level : 1,
252 trigger : 1,
253 __reserved_2 : 2,
254 shorthand : 2,
255 __reserved_3 : 12;
256 u32 __reserved_4[3];
257 } icr1;
258
259 /*310*/ struct { /* Interrupt Command Register 2 */
260 union {
261 u32 __reserved_1 : 24,
262 phys_dest : 4,
263 __reserved_2 : 4;
264 u32 __reserved_3 : 24,
265 logical_dest : 8;
266 } dest;
267 u32 __reserved_4[3];
268 } icr2;
269
270 /*320*/ struct { /* LVT - Timer */
271 u32 vector : 8,
272 __reserved_1 : 4,
273 delivery_status : 1,
274 __reserved_2 : 3,
275 mask : 1,
276 timer_mode : 1,
277 __reserved_3 : 14;
278 u32 __reserved_4[3];
279 } lvt_timer;
280
281 /*330*/ struct { u32 __reserved[4]; } __reserved_15;
282
283 /*340*/ struct { /* LVT - Performance Counter */
284 u32 vector : 8,
285 delivery_mode : 3,
286 __reserved_1 : 1,
287 delivery_status : 1,
288 __reserved_2 : 3,
289 mask : 1,
290 __reserved_3 : 15;
291 u32 __reserved_4[3];
292 } lvt_pc;
293
294 /*350*/ struct { /* LVT - LINT0 */
295 u32 vector : 8,
296 delivery_mode : 3,
297 __reserved_1 : 1,
298 delivery_status : 1,
299 polarity : 1,
300 remote_irr : 1,
301 trigger : 1,
302 mask : 1,
303 __reserved_2 : 15;
304 u32 __reserved_3[3];
305 } lvt_lint0;
306
307 /*360*/ struct { /* LVT - LINT1 */
308 u32 vector : 8,
309 delivery_mode : 3,
310 __reserved_1 : 1,
311 delivery_status : 1,
312 polarity : 1,
313 remote_irr : 1,
314 trigger : 1,
315 mask : 1,
316 __reserved_2 : 15;
317 u32 __reserved_3[3];
318 } lvt_lint1;
319
320 /*370*/ struct { /* LVT - Error */
321 u32 vector : 8,
322 __reserved_1 : 4,
323 delivery_status : 1,
324 __reserved_2 : 3,
325 mask : 1,
326 __reserved_3 : 15;
327 u32 __reserved_4[3];
328 } lvt_error;
329
330 /*380*/ struct { /* Timer Initial Count Register */
331 u32 initial_count;
332 u32 __reserved_2[3];
333 } timer_icr;
334
335 /*390*/ const
336 struct { /* Timer Current Count Register */
337 u32 curr_count;
338 u32 __reserved_2[3];
339 } timer_ccr;
340
341 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
342
343 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
344
345 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
346
347 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
348
349 /*3E0*/ struct { /* Timer Divide Configuration Register */
350 u32 divisor : 4,
351 __reserved_1 : 28;
352 u32 __reserved_2[3];
353 } timer_dcr;
354
355 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
356
357 } __attribute__ ((packed));
358
359 #undef u32
360
361 #endif
362
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