1 /*
2 * cpufeature.h
3 *
4 * Defines x86 CPU feature bits
5 */
6
7 #ifndef __ASM_I386_CPUFEATURE_H
8 #define __ASM_I386_CPUFEATURE_H
9
10 /* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
11 #define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE ##_BIT)
12
13 #define NCAPINTS 4 /* Currently we have 4 32-bit words worth of info */
14
15 /* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
16 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
17 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
18 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
19 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
20 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
21 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
22 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
23 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
24 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
25 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
26 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
27 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
28 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
29 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
30 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
31 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
32 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
33 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */
34 #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
35 #define X86_FEATURE_DTES (0*32+21) /* Debug Trace Store */
36 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
37 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
38 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
39 /* of FPU context), and CR4.OSFXSR available */
40 #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
41 #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
42 #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
43 #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
44 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
45
46 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
47 /* Don't duplicate feature flags which are redundant with Intel! */
48 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
49 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
50 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
51 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
52 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
53
54 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
55 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
56 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
57 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
58
59 /* Other features, Linux-defined mapping, word 3 */
60 /* This range is used for feature bits which conflict or are synthesized */
61 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
62 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
63 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
64 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
65
66 #endif /* __ASM_I386_CPUFEATURE_H */
67
68 /*
69 * Local Variables:
70 * mode:c
71 * comment-column:42
72 * End:
73 */
74
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