1 #ifndef __ASM_SMP_H
2 #define __ASM_SMP_H
3
4 /*
5 * We need the APIC definitions automatically as part of 'smp.h'
6 */
7 #ifndef ASSEMBLY
8 #include <linux/config.h>
9 #include <linux/threads.h>
10 #include <linux/ptrace.h>
11 #endif
12
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #ifndef ASSEMBLY
15 #include <asm/fixmap.h>
16 #include <asm/bitops.h>
17 #include <asm/mpspec.h>
18 #ifdef CONFIG_X86_IO_APIC
19 #include <asm/io_apic.h>
20 #endif
21 #include <asm/apic.h>
22 #endif
23 #endif
24
25 #ifdef CONFIG_SMP
26 #ifndef ASSEMBLY
27
28 /*
29 * Private routines/data
30 */
31
32 extern void smp_alloc_memory(void);
33 extern unsigned long phys_cpu_present_map;
34 extern unsigned long cpu_online_map;
35 extern volatile unsigned long smp_invalidate_needed;
36 extern int pic_mode;
37 extern void smp_flush_tlb(void);
38 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
39 extern void smp_send_reschedule(int cpu);
40 extern void smp_invalidate_rcv(void); /* Process an NMI */
41 extern void (*mtrr_hook) (void);
42 extern void zap_low_mappings (void);
43
44 /*
45 * On x86 all CPUs are mapped 1:1 to the APIC space.
46 * This simplifies scheduling and IPI sending and
47 * compresses data structures.
48 */
49 extern inline int cpu_logical_map(int cpu)
50 {
51 return cpu;
52 }
53 extern inline int cpu_number_map(int cpu)
54 {
55 return cpu;
56 }
57
58 /*
59 * Some lowlevel functions might want to know about
60 * the real APIC ID <-> CPU # mapping.
61 */
62 extern volatile int x86_apicid_to_cpu[NR_CPUS];
63 extern volatile int x86_cpu_to_apicid[NR_CPUS];
64
65 /*
66 * General functions that each host system must provide.
67 */
68
69 extern void smp_boot_cpus(void);
70 extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */
71
72 /*
73 * This function is needed by all SMP systems. It must _always_ be valid
74 * from the initial startup. We map APIC_BASE very early in page_setup(),
75 * so this is correct in the x86 case.
76 */
77
78 #define smp_processor_id() (current->processor)
79
80 extern __inline int hard_smp_processor_id(void)
81 {
82 /* we don't want to mark this access volatile - bad code generation */
83 return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID));
84 }
85
86 #endif /* !ASSEMBLY */
87
88 #define NO_PROC_ID 0xFF /* No processor magic marker */
89
90 /*
91 * This magic constant controls our willingness to transfer
92 * a process across CPUs. Such a transfer incurs misses on the L1
93 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
94 * gut feeling is this will vary by board in value. For a board
95 * with separate L2 cache it probably depends also on the RSS, and
96 * for a board with shared L2 cache it ought to decay fast as other
97 * processes are run.
98 */
99
100 #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
101
102 #endif
103 #endif
104
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