1 #ifndef _ASM_IA64_MACHVEC_SN1_h
2 #define _ASM_IA64_MACHVEC_SN1_h
3
4 extern ia64_mv_setup_t sn1_setup;
5 extern ia64_mv_irq_init_t sn1_irq_init;
6 extern ia64_mv_map_nr_t sn1_map_nr;
7 extern ia64_mv_send_ipi_t sn1_send_IPI;
8 extern ia64_mv_pci_fixup_t sn1_pci_fixup;
9 extern ia64_mv_inb_t sn1_inb;
10 extern ia64_mv_inw_t sn1_inw;
11 extern ia64_mv_inl_t sn1_inl;
12 extern ia64_mv_outb_t sn1_outb;
13 extern ia64_mv_outw_t sn1_outw;
14 extern ia64_mv_outl_t sn1_outl;
15 extern ia64_mv_pci_alloc_consistent sn1_pci_alloc_consistent;
16 extern ia64_mv_pci_free_consistent sn1_pci_free_consistent;
17 extern ia64_mv_pci_map_single sn1_pci_map_single;
18 extern ia64_mv_pci_unmap_single sn1_pci_unmap_single;
19 extern ia64_mv_pci_map_sg sn1_pci_map_sg;
20 extern ia64_mv_pci_unmap_sg sn1_pci_unmap_sg;
21 extern ia64_mv_pci_dma_sync_single sn1_pci_dma_sync_single;
22 extern ia64_mv_pci_dma_sync_sg sn1_pci_dma_sync_sg;
23 extern ia64_mv_pci_dma_address sn1_dma_address;
24
25 /*
26 * This stuff has dual use!
27 *
28 * For a generic kernel, the macros are used to initialize the
29 * platform's machvec structure. When compiling a non-generic kernel,
30 * the macros are used directly.
31 */
32 #define platform_name "sn1"
33 #define platform_setup sn1_setup
34 #define platform_irq_init sn1_irq_init
35 #define platform_map_nr sn1_map_nr
36 #define platform_send_ipi sn1_send_IPI
37 #define platform_pci_fixup sn1_pci_fixup
38 #define platform_inb sn1_inb
39 #define platform_inw sn1_inw
40 #define platform_inl sn1_inl
41 #define platform_outb sn1_outb
42 #define platform_outw sn1_outw
43 #define platform_outl sn1_outl
44 #define platform_pci_alloc_consistent sn1_pci_alloc_consistent
45 #define platform_pci_free_consistent sn1_pci_free_consistent
46 #define platform_pci_map_single sn1_pci_map_single
47 #define platform_pci_unmap_single sn1_pci_unmap_single
48 #define platform_pci_map_sg sn1_pci_map_sg
49 #define platform_pci_unmap_sg sn1_pci_unmap_sg
50 #define platform_pci_dma_sync_single sn1_pci_dma_sync_single
51 #define platform_pci_dma_sync_sg sn1_pci_dma_sync_sg
52 #define platform_pci_dma_address sn1_dma_address
53
54 #endif /* _ASM_IA64_MACHVEC_SN1_h */
55
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