1 /*
2 * File: mca_asm.h
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
7 * Copyright (C) 2000 Hewlett-Packard Co.
8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10 #ifndef _ASM_IA64_MCA_ASM_H
11 #define _ASM_IA64_MCA_ASM_H
12
13 #define PSR_IC 13
14 #define PSR_I 14
15 #define PSR_DT 17
16 #define PSR_RT 27
17 #define PSR_IT 36
18 #define PSR_BN 44
19
20 /*
21 * This macro converts a instruction virtual address to a physical address
22 * Right now for simulation purposes the virtual addresses are
23 * direct mapped to physical addresses.
24 * 1. Lop off bits 61 thru 63 in the virtual address
25 */
26 #define INST_VA_TO_PA(addr) \
27 dep addr = 0, addr, 61, 3;
28 /*
29 * This macro converts a data virtual address to a physical address
30 * Right now for simulation purposes the virtual addresses are
31 * direct mapped to physical addresses.
32 * 1. Lop off bits 61 thru 63 in the virtual address
33 */
34 #define DATA_VA_TO_PA(addr) \
35 dep addr = 0, addr, 61, 3;
36 /*
37 * This macro converts a data physical address to a virtual address
38 * Right now for simulation purposes the virtual addresses are
39 * direct mapped to physical addresses.
40 * 1. Put 0x7 in bits 61 thru 63.
41 */
42 #define DATA_PA_TO_VA(addr,temp) \
43 mov temp = 0x7 ; \
44 dep addr = temp, addr, 61, 3;
45
46 /*
47 * This macro jumps to the instruction at the given virtual address
48 * and starts execution in physical mode with all the address
49 * translations turned off.
50 * 1. Save the current psr
51 * 2. Make sure that all the upper 32 bits are off
52 *
53 * 3. Clear the interrupt enable and interrupt state collection bits
54 * in the psr before updating the ipsr and iip.
55 *
56 * 4. Turn off the instruction, data and rse translation bits of the psr
57 * and store the new value into ipsr
58 * Also make sure that the interrupts are disabled.
59 * Ensure that we are in little endian mode.
60 * [psr.{rt, it, dt, i, be} = 0]
61 *
62 * 5. Get the physical address corresponding to the virtual address
63 * of the next instruction bundle and put it in iip.
64 * (Using magic numbers 24 and 40 in the deposint instruction since
65 * the IA64_SDK code directly maps to lower 24bits as physical address
66 * from a virtual address).
67 *
68 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
69 */
70 #define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
71 mov old_psr = psr; \
72 ;; \
73 dep old_psr = 0, old_psr, 32, 32; \
74 \
75 mov ar.rsc = r0 ; \
76 ;; \
77 mov temp2 = ar.bspstore; \
78 ;; \
79 DATA_VA_TO_PA(temp2); \
80 ;; \
81 mov temp1 = ar.rnat; \
82 ;; \
83 mov ar.bspstore = temp2; \
84 ;; \
85 mov ar.rnat = temp1; \
86 mov temp1 = psr; \
87 mov temp2 = psr; \
88 ;; \
89 \
90 dep temp2 = 0, temp2, PSR_IC, 2; \
91 ;; \
92 mov psr.l = temp2; \
93 ;; \
94 srlz.d; \
95 dep temp1 = 0, temp1, 32, 32; \
96 ;; \
97 dep temp1 = 0, temp1, PSR_IT, 1; \
98 ;; \
99 dep temp1 = 0, temp1, PSR_DT, 1; \
100 ;; \
101 dep temp1 = 0, temp1, PSR_RT, 1; \
102 ;; \
103 dep temp1 = 0, temp1, PSR_I, 1; \
104 ;; \
105 movl temp2 = start_addr; \
106 mov cr.ipsr = temp1; \
107 ;; \
108 INST_VA_TO_PA(temp2); \
109 ;; \
110 mov cr.iip = temp2; \
111 mov cr.ifs = r0; \
112 DATA_VA_TO_PA(sp) \
113 DATA_VA_TO_PA(gp) \
114 ;; \
115 srlz.i; \
116 ;; \
117 nop 1; \
118 nop 2; \
119 nop 1; \
120 nop 2; \
121 rfi; \
122 ;;
123
124 /*
125 * This macro jumps to the instruction at the given virtual address
126 * and starts execution in virtual mode with all the address
127 * translations turned on.
128 * 1. Get the old saved psr
129 *
130 * 2. Clear the interrupt enable and interrupt state collection bits
131 * in the current psr.
132 *
133 * 3. Set the instruction translation bit back in the old psr
134 * Note we have to do this since we are right now saving only the
135 * lower 32-bits of old psr.(Also the old psr has the data and
136 * rse translation bits on)
137 *
138 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
139 *
140 * 5. Set iip to the virtual address of the next instruction bundle.
141 *
142 * 6. Do an rfi to move ipsr to psr and iip to ip.
143 */
144
145 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
146 mov temp2 = psr; \
147 ;; \
148 dep temp2 = 0, temp2, PSR_IC, 2; \
149 ;; \
150 mov psr.l = temp2; \
151 mov ar.rsc = r0; \
152 ;; \
153 srlz.d; \
154 mov temp2 = ar.bspstore; \
155 ;; \
156 DATA_PA_TO_VA(temp2,temp1); \
157 ;; \
158 mov temp1 = ar.rnat; \
159 ;; \
160 mov ar.bspstore = temp2; \
161 ;; \
162 mov ar.rnat = temp1; \
163 ;; \
164 mov temp1 = old_psr; \
165 ;; \
166 mov temp2 = 1 ; \
167 dep temp1 = temp2, temp1, PSR_I, 1; \
168 ;; \
169 dep temp1 = temp2, temp1, PSR_IC, 1; \
170 ;; \
171 dep temp1 = temp2, temp1, PSR_IT, 1; \
172 ;; \
173 dep temp1 = temp2, temp1, PSR_DT, 1; \
174 ;; \
175 dep temp1 = temp2, temp1, PSR_RT, 1; \
176 ;; \
177 dep temp1 = temp2, temp1, PSR_BN, 1; \
178 ;; \
179 \
180 mov cr.ipsr = temp1; \
181 movl temp2 = start_addr; \
182 ;; \
183 mov cr.iip = temp2; \
184 DATA_PA_TO_VA(sp, temp1); \
185 DATA_PA_TO_VA(gp, temp2); \
186 ;; \
187 nop 1; \
188 nop 2; \
189 nop 1; \
190 rfi; \
191 ;;
192
193 /*
194 * The following offsets capture the order in which the
195 * RSE related registers from the old context are
196 * saved onto the new stack frame.
197 *
198 * +-----------------------+
199 * |NDIRTY [BSP - BSPSTORE]|
200 * +-----------------------+
201 * | RNAT |
202 * +-----------------------+
203 * | BSPSTORE |
204 * +-----------------------+
205 * | IFS |
206 * +-----------------------+
207 * | PFS |
208 * +-----------------------+
209 * | RSC |
210 * +-----------------------+ <-------- Bottom of new stack frame
211 */
212 #define rse_rsc_offset 0
213 #define rse_pfs_offset (rse_rsc_offset+0x08)
214 #define rse_ifs_offset (rse_pfs_offset+0x08)
215 #define rse_bspstore_offset (rse_ifs_offset+0x08)
216 #define rse_rnat_offset (rse_bspstore_offset+0x08)
217 #define rse_ndirty_offset (rse_rnat_offset+0x08)
218
219 /*
220 * rse_switch_context
221 *
222 * 1. Save old RSC onto the new stack frame
223 * 2. Save PFS onto new stack frame
224 * 3. Cover the old frame and start a new frame.
225 * 4. Save IFS onto new stack frame
226 * 5. Save the old BSPSTORE on the new stack frame
227 * 6. Save the old RNAT on the new stack frame
228 * 7. Write BSPSTORE with the new backing store pointer
229 * 8. Read and save the new BSP to calculate the #dirty registers
230 * NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
231 */
232 #define rse_switch_context(temp,p_stackframe,p_bspstore) \
233 ;; \
234 mov temp=ar.rsc;; \
235 st8 [p_stackframe]=temp,8;; \
236 mov temp=ar.pfs;; \
237 st8 [p_stackframe]=temp,8; \
238 cover ;; \
239 mov temp=cr.ifs;; \
240 st8 [p_stackframe]=temp,8;; \
241 mov temp=ar.bspstore;; \
242 st8 [p_stackframe]=temp,8;; \
243 mov temp=ar.rnat;; \
244 st8 [p_stackframe]=temp,8; \
245 mov ar.bspstore=p_bspstore;; \
246 mov temp=ar.bsp;; \
247 sub temp=temp,p_bspstore;; \
248 st8 [p_stackframe]=temp,8
249
250 /*
251 * rse_return_context
252 * 1. Allocate a zero-sized frame
253 * 2. Store the number of dirty registers RSC.loadrs field
254 * 3. Issue a loadrs to insure that any registers from the interrupted
255 * context which were saved on the new stack frame have been loaded
256 * back into the stacked registers
257 * 4. Restore BSPSTORE
258 * 5. Restore RNAT
259 * 6. Restore PFS
260 * 7. Restore IFS
261 * 8. Restore RSC
262 * 9. Issue an RFI
263 */
264 #define rse_return_context(psr_mask_reg,temp,p_stackframe) \
265 ;; \
266 alloc temp=ar.pfs,0,0,0,0; \
267 add p_stackframe=rse_ndirty_offset,p_stackframe;; \
268 ld8 temp=[p_stackframe];; \
269 shl temp=temp,16;; \
270 mov ar.rsc=temp;; \
271 loadrs;; \
272 add p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
273 ld8 temp=[p_stackframe];; \
274 mov ar.bspstore=temp;; \
275 add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
276 ld8 temp=[p_stackframe];; \
277 mov ar.rnat=temp;; \
278 add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
279 ld8 temp=[p_stackframe];; \
280 mov ar.pfs=temp; \
281 add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
282 ld8 temp=[p_stackframe];; \
283 mov cr.ifs=temp; \
284 add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
285 ld8 temp=[p_stackframe];; \
286 mov ar.rsc=temp ; \
287 add p_stackframe=-rse_rsc_offset,p_stackframe; \
288 mov temp=cr.ipsr;; \
289 st8 [p_stackframe]=temp,8; \
290 mov temp=cr.iip;; \
291 st8 [p_stackframe]=temp,-8; \
292 mov temp=psr;; \
293 or temp=temp,psr_mask_reg;; \
294 mov cr.ipsr=temp;; \
295 mov temp=ip;; \
296 add temp=0x30,temp;; \
297 mov cr.iip=temp;; \
298 rfi;; \
299 ld8 temp=[p_stackframe],8;; \
300 mov cr.ipsr=temp;; \
301 ld8 temp=[p_stackframe];; \
302 mov cr.iip=temp
303
304 #endif /* _ASM_IA64_MCA_ASM_H */
305