1 #ifndef _ASM_IA64_PGTABLE_H
2 #define _ASM_IA64_PGTABLE_H
3
4 /*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h> (currently 8192).
10 *
11 * Copyright (C) 1998-2000 Hewlett-Packard Co
12 * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
13 */
14
15 #include <linux/config.h>
16 #include <asm/mman.h>
17 #include <asm/page.h>
18 #include <asm/processor.h>
19 #include <asm/types.h>
20
21 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
22
23 /*
24 * First, define the various bits in a PTE. Note that the PTE format
25 * matches the VHPT short format, the firt doubleword of the VHPD long
26 * format, and the first doubleword of the TLB insertion format.
27 */
28 #define _PAGE_P_BIT 0
29 #define _PAGE_A_BIT 5
30 #define _PAGE_D_BIT 6
31
32 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
33 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
34 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
35 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
36 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
37 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
38 #define _PAGE_MA_MASK (0x7 << 2)
39 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
40 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
41 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
42 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
43 #define _PAGE_PL_MASK (3 << 7)
44 #define _PAGE_AR_R (0 << 9) /* read only */
45 #define _PAGE_AR_RX (1 << 9) /* read & execute */
46 #define _PAGE_AR_RW (2 << 9) /* read & write */
47 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
48 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
49 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
50 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
51 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
52 #define _PAGE_AR_MASK (7 << 9)
53 #define _PAGE_AR_SHIFT 9
54 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
55 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
56 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
57 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
58 #define _PAGE_PROTNONE (__IA64_UL(1) << 63)
59
60 #define _PFN_MASK _PAGE_PPN_MASK
61 #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_A | _PAGE_D)
62
63 #define _PAGE_SIZE_4K 12
64 #define _PAGE_SIZE_8K 13
65 #define _PAGE_SIZE_16K 14
66 #define _PAGE_SIZE_64K 16
67 #define _PAGE_SIZE_256K 18
68 #define _PAGE_SIZE_1M 20
69 #define _PAGE_SIZE_4M 22
70 #define _PAGE_SIZE_16M 24
71 #define _PAGE_SIZE_64M 26
72 #define _PAGE_SIZE_256M 28
73
74 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
75 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
76 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
77
78 /*
79 * Definitions for first level:
80 *
81 * PGDIR_SHIFT determines what a first-level page table entry can map.
82 */
83 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
84 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
85 #define PGDIR_MASK (~(PGDIR_SIZE-1))
86 #define PTRS_PER_PGD (__IA64_UL(1) << (PAGE_SHIFT-3))
87 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
88 #define FIRST_USER_PGD_NR 0
89
90 /*
91 * Definitions for second level:
92 *
93 * PMD_SHIFT determines the size of the area a second-level page table
94 * can map.
95 */
96 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
97 #define PMD_SIZE (__IA64_UL(1) << PMD_SHIFT)
98 #define PMD_MASK (~(PMD_SIZE-1))
99 #define PTRS_PER_PMD (__IA64_UL(1) << (PAGE_SHIFT-3))
100
101 /*
102 * Definitions for third level:
103 */
104 #define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
105
106 # ifndef __ASSEMBLY__
107
108 #include <asm/bitops.h>
109 #include <asm/mmu_context.h>
110 #include <asm/system.h>
111
112 /*
113 * All the normal masks have the "page accessed" bits on, as any time
114 * they are used, the page is accessed. They are cleared only by the
115 * page-out routines. On the other hand, we do NOT turn on the
116 * execute bit on pages that are mapped writable. For those pages, we
117 * turn on the X bit only when the program attempts to actually
118 * execute code in such a page (it's a "lazy execute bit", if you
119 * will). This lets reduce the amount of i-cache flushing we have to
120 * do for data pages such as stack and heap pages.
121 */
122 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
123 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
124 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
125 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
126 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
127 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
128
129 /*
130 * Next come the mappings that determine how mmap() protection bits
131 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
132 * _P version gets used for a private shared memory segment, the _S
133 * version gets used for a shared memory segment with MAP_SHARED on.
134 * In a private shared memory segment, we do a copy-on-write if a task
135 * attempts to write to the page.
136 */
137 /* xwr */
138 #define __P000 PAGE_NONE
139 #define __P001 PAGE_READONLY
140 #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
141 #define __P011 PAGE_READONLY /* ditto */
142 #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
143 #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
144 #define __P110 PAGE_COPY
145 #define __P111 PAGE_COPY
146
147 #define __S000 PAGE_NONE
148 #define __S001 PAGE_READONLY
149 #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
150 #define __S011 PAGE_SHARED
151 #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
152 #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
153 #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
154 #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
155
156 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
157 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
158 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
159
160
161 /*
162 * Some definitions to translate between mem_map, PTEs, and page
163 * addresses:
164 */
165
166 /*
167 * Given a pointer to an mem_map[] entry, return the kernel virtual
168 * address corresponding to that page.
169 */
170 #define page_address(page) ((page)->virtual)
171
172 /* Quick test to see if ADDR is a (potentially) valid physical address. */
173 static inline long
174 ia64_phys_addr_valid (unsigned long addr)
175 {
176 return (addr & (my_cpu_data.unimpl_pa_mask)) == 0;
177 }
178
179 /*
180 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
181 * memory. For the return value to be meaningful, ADDR must be >=
182 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
183 * require a hash-, or multi-level tree-lookup or something of that
184 * sort) but it guarantees to return TRUE only if accessing the page
185 * at that address does not cause an error. Note that there may be
186 * addresses for which kern_addr_valid() returns FALSE even though an
187 * access would not cause an error (e.g., this is typically true for
188 * memory mapped I/O regions.
189 *
190 * XXX Need to implement this for IA-64.
191 */
192 #define kern_addr_valid(addr) (1)
193
194 /*
195 * Now come the defines and routines to manage and access the three-level
196 * page table.
197 */
198
199 /*
200 * On some architectures, special things need to be done when setting
201 * the PTE in a page table. Nothing special needs to be on IA-64.
202 */
203 #define set_pte(ptep, pteval) (*(ptep) = (pteval))
204
205 #define RGN_SIZE (1UL << 61)
206 #define RGN_MAP_LIMIT (1UL << (4*PAGE_SHIFT - 12)) /* limit of mappable area in region */
207 #define RGN_KERNEL 7
208
209 #define VMALLOC_START (0xa000000000000000 + 2*PAGE_SIZE)
210 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
211 #define VMALLOC_END (0xa000000000000000 + RGN_MAP_LIMIT)
212
213 /*
214 * BAD_PAGETABLE is used when we need a bogus page-table, while
215 * BAD_PAGE is used for a bogus page.
216 *
217 * ZERO_PAGE is a global shared page that is always zero: used
218 * for zero-mapped memory areas etc..
219 */
220 extern pte_t ia64_bad_page (void);
221 extern pmd_t *ia64_bad_pagetable (void);
222
223 #define BAD_PAGETABLE ia64_bad_pagetable()
224 #define BAD_PAGE ia64_bad_page()
225
226 /*
227 * Conversion functions: convert a page and protection to a page entry,
228 * and a page entry and page directory to the page they refer to.
229 */
230 #define mk_pte(page,pgprot) \
231 ({ \
232 pte_t __pte; \
233 \
234 pte_val(__pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \
235 __pte; \
236 })
237
238 /* This takes a physical page address that is used by the remapping functions */
239 #define mk_pte_phys(physpage, pgprot) \
240 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
241
242 #define pte_modify(_pte, newprot) \
243 (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
244
245 #define page_pte_prot(page,prot) mk_pte(page, prot)
246 #define page_pte(page) page_pte_prot(page, __pgprot(0))
247
248 #define pte_none(pte) (!pte_val(pte))
249 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
250 #define pte_clear(pte) (pte_val(*(pte)) = 0UL)
251 /* pte_page() returns the "struct page *" corresponding to the PTE: */
252 #define pte_page(pte) (mem_map + (unsigned long) ((pte_val(pte) & _PFN_MASK) >> PAGE_SHIFT))
253
254 #define pmd_set(pmdp, ptep) (pmd_val(*(pmdp)) = __pa(ptep))
255 #define pmd_none(pmd) (!pmd_val(pmd))
256 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
257 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
258 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
259 #define pmd_page(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
260
261 #define pgd_set(pgdp, pmdp) (pgd_val(*(pgdp)) = __pa(pmdp))
262 #define pgd_none(pgd) (!pgd_val(pgd))
263 #define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
264 #define pgd_present(pgd) (pgd_val(pgd) != 0UL)
265 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
266 #define pgd_page(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
267
268 /*
269 * The following have defined behavior only work if pte_present() is true.
270 */
271 #define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
272 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
273 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
274 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
275 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
276 /*
277 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
278 * access rights:
279 */
280 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
281 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
282 #define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX))
283 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
284 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
285 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
286 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
287
288 /*
289 * Macro to make mark a page protection value as "uncacheable". Note
290 * that "protection" is really a misnomer here as the protection value
291 * contains the memory attribute bits, dirty bits, and various other
292 * bits as well.
293 */
294 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
295
296 /*
297 * Macro to make mark a page protection value as "write-combining".
298 * Note that "protection" is really a misnomer here as the protection
299 * value contains the memory attribute bits, dirty bits, and various
300 * other bits as well. Accesses through a write-combining translation
301 * works bypasses the caches, but does allow for consecutive writes to
302 * be combined into single (but larger) write transactions.
303 */
304 #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
305
306 /*
307 * Return the region index for virtual address ADDRESS.
308 */
309 static inline unsigned long
310 rgn_index (unsigned long address)
311 {
312 ia64_va a;
313
314 a.l = address;
315 return a.f.reg;
316 }
317
318 /*
319 * Return the region offset for virtual address ADDRESS.
320 */
321 static inline unsigned long
322 rgn_offset (unsigned long address)
323 {
324 ia64_va a;
325
326 a.l = address;
327 return a.f.off;
328 }
329
330 static inline unsigned long
331 pgd_index (unsigned long address)
332 {
333 unsigned long region = address >> 61;
334 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
335
336 return (region << (PAGE_SHIFT - 6)) | l1index;
337 }
338
339 /* The offset in the 1-level directory is given by the 3 region bits
340 (61..63) and the seven level-1 bits (33-39). */
341 static inline pgd_t*
342 pgd_offset (struct mm_struct *mm, unsigned long address)
343 {
344 return mm->pgd + pgd_index(address);
345 }
346
347 /* In the kernel's mapped region we have a full 43 bit space available and completely
348 ignore the region number (since we know its in region number 5). */
349 #define pgd_offset_k(addr) \
350 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
351
352 /* Find an entry in the second-level page table.. */
353 #define pmd_offset(dir,addr) \
354 ((pmd_t *) pgd_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
355
356 /* Find an entry in the third-level page table.. */
357 #define pte_offset(dir,addr) \
358 ((pte_t *) pmd_page(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
359
360 /* atomic versions of the some PTE manipulations: */
361
362 static inline int
363 ptep_test_and_clear_young (pte_t *ptep)
364 {
365 #ifdef CONFIG_SMP
366 return test_and_clear_bit(_PAGE_A_BIT, ptep);
367 #else
368 pte_t pte = *ptep;
369 if (!pte_young(pte))
370 return 0;
371 set_pte(ptep, pte_mkold(pte));
372 return 1;
373 #endif
374 }
375
376 static inline int
377 ptep_test_and_clear_dirty (pte_t *ptep)
378 {
379 #ifdef CONFIG_SMP
380 return test_and_clear_bit(_PAGE_D_BIT, ptep);
381 #else
382 pte_t pte = *ptep;
383 if (!pte_dirty(pte))
384 return 0;
385 set_pte(ptep, pte_mkclean(pte));
386 return 1;
387 #endif
388 }
389
390 static inline pte_t
391 ptep_get_and_clear (pte_t *ptep)
392 {
393 #ifdef CONFIG_SMP
394 return __pte(xchg((long *) ptep, 0));
395 #else
396 pte_t pte = *ptep;
397 pte_clear(ptep);
398 return pte;
399 #endif
400 }
401
402 static inline void
403 ptep_set_wrprotect (pte_t *ptep)
404 {
405 #ifdef CONFIG_SMP
406 unsigned long new, old;
407
408 do {
409 old = pte_val(*ptep);
410 new = pte_val(pte_wrprotect(__pte (old)));
411 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
412 #else
413 pte_t old_pte = *ptep;
414 set_pte(ptep, pte_wrprotect(old_pte));
415 #endif
416 }
417
418 static inline void
419 ptep_mkdirty (pte_t *ptep)
420 {
421 #ifdef CONFIG_SMP
422 set_bit(_PAGE_D_BIT, ptep);
423 #else
424 pte_t old_pte = *ptep;
425 set_pte(ptep, pte_mkdirty(old_pte));
426 #endif
427 }
428
429 static inline int
430 pte_same (pte_t a, pte_t b)
431 {
432 return pte_val(a) == pte_val(b);
433 }
434
435 /*
436 * Macros to check the type of access that triggered a page fault.
437 */
438
439 static inline int
440 is_write_access (int access_type)
441 {
442 return (access_type & 0x2);
443 }
444
445 static inline int
446 is_exec_access (int access_type)
447 {
448 return (access_type & 0x4);
449 }
450
451 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
452 extern void paging_init (void);
453
454 #define SWP_TYPE(entry) (((entry).val >> 1) & 0xff)
455 #define SWP_OFFSET(entry) (((entry).val << 1) >> 10)
456 #define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 9) })
457 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
458 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
459
460 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
461 #define PageSkip(page) (0)
462
463 #define io_remap_page_range remap_page_range /* XXX is this right? */
464
465 /*
466 * ZERO_PAGE is a global shared page that is always zero: used
467 * for zero-mapped memory areas etc..
468 */
469 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
470 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
471
472 /* We provide our own get_unmapped_area to cope with VA holes for userland */
473 #define HAVE_ARCH_UNMAPPED_AREA
474
475 # endif /* !__ASSEMBLY__ */
476
477 #endif /* _ASM_IA64_PGTABLE_H */
478
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