1 #ifndef _ASM_IA64_PROCESSOR_H
2 #define _ASM_IA64_PROCESSOR_H
3
4 /*
5 * Copyright (C) 1998-2000 Hewlett-Packard Co
6 * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1998-2000 Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
15
16 #include <linux/config.h>
17
18 #include <asm/ptrace.h>
19 #include <asm/types.h>
20
21 #define IA64_NUM_DBG_REGS 8
22 /*
23 * Limits for PMC and PMD are set to less than maximum architected values
24 * but should be sufficient for a while
25 */
26 #define IA64_NUM_PMC_REGS 32
27 #define IA64_NUM_PMD_REGS 32
28 #define IA64_NUM_PMD_COUNTERS 4
29
30 /*
31 * TASK_SIZE really is a mis-named. It really is the maximum user
32 * space address (plus one). On IA-64, there are five regions of 2TB
33 * each (assuming 8KB page size), for a total of 8TB of user virtual
34 * address space.
35 */
36 #define TASK_SIZE (current->thread.task_size)
37
38 /*
39 * This decides where the kernel will search for a free chunk of vm
40 * space during mmap's.
41 */
42 #define TASK_UNMAPPED_BASE (current->thread.map_base)
43
44 /*
45 * Bus types
46 */
47 #define EISA_bus 0
48 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
49 #define MCA_bus 0
50 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
51
52 /* Processor status register bits: */
53 #define IA64_PSR_BE_BIT 1
54 #define IA64_PSR_UP_BIT 2
55 #define IA64_PSR_AC_BIT 3
56 #define IA64_PSR_MFL_BIT 4
57 #define IA64_PSR_MFH_BIT 5
58 #define IA64_PSR_IC_BIT 13
59 #define IA64_PSR_I_BIT 14
60 #define IA64_PSR_PK_BIT 15
61 #define IA64_PSR_DT_BIT 17
62 #define IA64_PSR_DFL_BIT 18
63 #define IA64_PSR_DFH_BIT 19
64 #define IA64_PSR_SP_BIT 20
65 #define IA64_PSR_PP_BIT 21
66 #define IA64_PSR_DI_BIT 22
67 #define IA64_PSR_SI_BIT 23
68 #define IA64_PSR_DB_BIT 24
69 #define IA64_PSR_LP_BIT 25
70 #define IA64_PSR_TB_BIT 26
71 #define IA64_PSR_RT_BIT 27
72 /* The following are not affected by save_flags()/restore_flags(): */
73 #define IA64_PSR_CPL0_BIT 32
74 #define IA64_PSR_CPL1_BIT 33
75 #define IA64_PSR_IS_BIT 34
76 #define IA64_PSR_MC_BIT 35
77 #define IA64_PSR_IT_BIT 36
78 #define IA64_PSR_ID_BIT 37
79 #define IA64_PSR_DA_BIT 38
80 #define IA64_PSR_DD_BIT 39
81 #define IA64_PSR_SS_BIT 40
82 #define IA64_PSR_RI_BIT 41
83 #define IA64_PSR_ED_BIT 43
84 #define IA64_PSR_BN_BIT 44
85
86 #define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
87 #define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
88 #define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
89 #define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
90 #define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
91 #define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
92 #define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
93 #define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
94 #define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
95 #define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
96 #define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
97 #define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
98 #define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
99 #define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
100 #define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
101 #define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
102 #define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
103 #define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
104 #define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
105 /* The following are not affected by save_flags()/restore_flags(): */
106 #define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
107 #define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
108 #define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
109 #define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
110 #define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
111 #define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
112 #define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
113 #define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
114 #define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
115 #define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
116
117 /* User mask bits: */
118 #define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
119
120 /* Default Control Register */
121 #define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
122 #define IA64_DCR_BE_BIT 1 /* big-endian default */
123 #define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
124 #define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
125 #define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
126 #define IA64_DCR_DK_BIT 10 /* defer key miss faults */
127 #define IA64_DCR_DX_BIT 11 /* defer key permission faults */
128 #define IA64_DCR_DR_BIT 12 /* defer access right faults */
129 #define IA64_DCR_DA_BIT 13 /* defer access bit faults */
130 #define IA64_DCR_DD_BIT 14 /* defer debug faults */
131
132 #define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
133 #define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
134 #define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
135 #define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
136 #define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
137 #define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
138 #define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
139 #define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
140 #define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
141 #define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
142
143 /* Interrupt Status Register */
144 #define IA64_ISR_X_BIT 32 /* execute access */
145 #define IA64_ISR_W_BIT 33 /* write access */
146 #define IA64_ISR_R_BIT 34 /* read access */
147 #define IA64_ISR_NA_BIT 35 /* non-access */
148 #define IA64_ISR_SP_BIT 36 /* speculative load exception */
149 #define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
150 #define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
151
152 #define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
153 #define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
154 #define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
155 #define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
156 #define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
157 #define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
158 #define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
159
160 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
161 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
162 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
163 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
164 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
165 #define IA64_THREAD_KRBS_SYNCED (__IA64_UL(1) << 5) /* krbs synced with process vm? */
166 #define IA64_THREAD_MAP_SHARED (__IA64_UL(1) << 6) /* ugly: just a tmp flag for mmap() */
167 #define IA64_KERNEL_DEATH (__IA64_UL(1) << 63) /* see die_if_kernel()... */
168
169 #define IA64_THREAD_UAC_SHIFT 3
170 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
171
172 #ifndef __ASSEMBLY__
173
174 #include <linux/smp.h>
175 #include <linux/threads.h>
176
177 #include <asm/fpu.h>
178 #include <asm/offsets.h>
179 #include <asm/page.h>
180 #include <asm/rse.h>
181 #include <asm/unwind.h>
182
183 /* like above but expressed as bitfields for more efficient access: */
184 struct ia64_psr {
185 __u64 reserved0 : 1;
186 __u64 be : 1;
187 __u64 up : 1;
188 __u64 ac : 1;
189 __u64 mfl : 1;
190 __u64 mfh : 1;
191 __u64 reserved1 : 7;
192 __u64 ic : 1;
193 __u64 i : 1;
194 __u64 pk : 1;
195 __u64 reserved2 : 1;
196 __u64 dt : 1;
197 __u64 dfl : 1;
198 __u64 dfh : 1;
199 __u64 sp : 1;
200 __u64 pp : 1;
201 __u64 di : 1;
202 __u64 si : 1;
203 __u64 db : 1;
204 __u64 lp : 1;
205 __u64 tb : 1;
206 __u64 rt : 1;
207 __u64 reserved3 : 4;
208 __u64 cpl : 2;
209 __u64 is : 1;
210 __u64 mc : 1;
211 __u64 it : 1;
212 __u64 id : 1;
213 __u64 da : 1;
214 __u64 dd : 1;
215 __u64 ss : 1;
216 __u64 ri : 2;
217 __u64 ed : 1;
218 __u64 bn : 1;
219 __u64 reserved4 : 19;
220 };
221
222 /*
223 * This shift should be large enough to be able to represent
224 * 1000000/itc_freq with good accuracy while being small enough to fit
225 * 1000000<<IA64_USEC_PER_CYC_SHIFT in 64 bits.
226 */
227 #define IA64_USEC_PER_CYC_SHIFT 41
228
229 /*
230 * CPU type, hardware bug flags, and per-CPU state.
231 */
232 struct cpuinfo_ia64 {
233 __u64 *pgd_quick;
234 __u64 *pmd_quick;
235 __u64 *pte_quick;
236 __u64 pgtable_cache_sz;
237 /* CPUID-derived information: */
238 __u64 ppn;
239 __u64 features;
240 __u8 number;
241 __u8 revision;
242 __u8 model;
243 __u8 family;
244 __u8 archrev;
245 char vendor[16];
246 __u64 itc_freq; /* frequency of ITC counter */
247 __u64 proc_freq; /* frequency of processor */
248 __u64 cyc_per_usec; /* itc_freq/1000000 */
249 __u64 usec_per_cyc; /* 2^IA64_USEC_PER_CYC_SHIFT*1000000/itc_freq */
250 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
251 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
252 __u64 ptce_base;
253 __u32 ptce_count[2];
254 __u32 ptce_stride[2];
255 #ifdef CONFIG_SMP
256 __u64 loops_per_jiffy;
257 __u64 ipi_count;
258 __u64 prof_counter;
259 __u64 prof_multiplier;
260 #endif
261 };
262
263 #define my_cpu_data cpu_data[smp_processor_id()]
264
265 extern struct cpuinfo_ia64 cpu_data[NR_CPUS];
266
267 extern void identify_cpu (struct cpuinfo_ia64 *);
268 extern void print_cpu_info (struct cpuinfo_ia64 *);
269
270 typedef struct {
271 unsigned long seg;
272 } mm_segment_t;
273
274 #define SET_UNALIGN_CTL(task,value) \
275 ({ \
276 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
277 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
278 0; \
279 })
280 #define GET_UNALIGN_CTL(task,addr) \
281 ({ \
282 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
283 (int *) (addr)); \
284 })
285
286 struct siginfo;
287
288 struct thread_struct {
289 __u64 ksp; /* kernel stack pointer */
290 unsigned long flags; /* various flags */
291 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
292 __u64 dbr[IA64_NUM_DBG_REGS];
293 __u64 ibr[IA64_NUM_DBG_REGS];
294 #ifdef CONFIG_PERFMON
295 __u64 pmc[IA64_NUM_PMC_REGS];
296 __u64 pmd[IA64_NUM_PMD_REGS];
297 struct {
298 __u64 val; /* virtual 64bit counter */
299 __u64 rval; /* reset value on overflow */
300 int sig; /* signal used to notify */
301 int pid; /* process to notify */
302 } pmu_counters[IA64_NUM_PMD_COUNTERS];
303 # define INIT_THREAD_PM {0, }, {0, }, {{ 0, 0, 0, 0}, },
304 #else
305 # define INIT_THREAD_PM
306 #endif
307 __u64 map_base; /* base address for get_unmapped_area() */
308 __u64 task_size; /* limit for task size */
309 #ifdef CONFIG_IA32_SUPPORT
310 __u64 eflag; /* IA32 EFLAGS reg */
311 __u64 fsr; /* IA32 floating pt status reg */
312 __u64 fcr; /* IA32 floating pt control reg */
313 __u64 fir; /* IA32 fp except. instr. reg */
314 __u64 fdr; /* IA32 fp except. data reg */
315 __u64 csd; /* IA32 code selector descriptor */
316 __u64 ssd; /* IA32 stack selector descriptor */
317 __u64 tssd; /* IA32 TSS descriptor */
318 __u64 old_iob; /* old IOBase value */
319 union {
320 __u64 sigmask; /* aligned mask for sigsuspend scall */
321 } un;
322 # define INIT_THREAD_IA32 0, 0, 0x17800000037fULL, 0, 0, 0, 0, 0, 0, {0},
323 #else
324 # define INIT_THREAD_IA32
325 #endif /* CONFIG_IA32_SUPPORT */
326 struct siginfo *siginfo; /* current siginfo struct for ptrace() */
327 };
328
329 #define INIT_MMAP { \
330 &init_mm, PAGE_OFFSET, PAGE_OFFSET + 0x10000000, NULL, PAGE_SHARED, \
331 VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL \
332 }
333
334 #define INIT_THREAD { \
335 0, /* ksp */ \
336 0, /* flags */ \
337 {{{{0}}}, }, /* fph */ \
338 {0, }, /* dbr */ \
339 {0, }, /* ibr */ \
340 INIT_THREAD_PM \
341 0x2000000000000000, /* map_base */ \
342 0xa000000000000000, /* task_size */ \
343 INIT_THREAD_IA32 \
344 0 /* siginfo */ \
345 }
346
347 #define start_thread(regs,new_ip,new_sp) do { \
348 set_fs(USER_DS); \
349 ia64_psr(regs)->dfh = 1; /* disable fph */ \
350 ia64_psr(regs)->mfh = 0; /* clear mfh */ \
351 ia64_psr(regs)->cpl = 3; /* set user mode */ \
352 ia64_psr(regs)->ri = 0; /* clear return slot number */ \
353 ia64_psr(regs)->is = 0; /* IA-64 instruction set */ \
354 regs->cr_iip = new_ip; \
355 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
356 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
357 regs->ar_bspstore = IA64_RBS_BOT; \
358 regs->ar_rnat = 0; \
359 regs->loadrs = 0; \
360 } while (0)
361
362 /* Forward declarations, a strange C thing... */
363 struct mm_struct;
364 struct task_struct;
365
366 /*
367 * Free all resources held by a thread. This is called after the
368 * parent of DEAD_TASK has collected the exist status of the task via
369 * wait(). This is a no-op on IA-64.
370 */
371 #define release_thread(dead_task)
372
373 /*
374 * This is the mechanism for creating a new kernel thread.
375 *
376 * NOTE 1: Only a kernel-only process (ie the swapper or direct
377 * descendants who haven't done an "execve()") should use this: it
378 * will work within a system call from a "real" process, but the
379 * process memory space will not be free'd until both the parent and
380 * the child have exited.
381 *
382 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
383 * into trouble in init/main.c when the child thread returns to
384 * do_basic_setup() and the timing is such that free_initmem() has
385 * been called already.
386 */
387 extern int kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
388
389 /* Copy and release all segment info associated with a VM */
390 #define copy_segments(tsk, mm) do { } while (0)
391 #define release_segments(mm) do { } while (0)
392
393 /* Get wait channel for task P. */
394 extern unsigned long get_wchan (struct task_struct *p);
395
396 /* Return instruction pointer of blocked task TSK. */
397 #define KSTK_EIP(tsk) \
398 ({ \
399 struct pt_regs *_regs = ia64_task_regs(tsk); \
400 _regs->cr_iip + ia64_psr(_regs)->ri; \
401 })
402
403 /* Return stack pointer of blocked task TSK. */
404 #define KSTK_ESP(tsk) ((tsk)->thread.ksp)
405
406 #ifndef CONFIG_SMP
407
408 static inline struct task_struct *
409 ia64_get_fpu_owner (void)
410 {
411 struct task_struct *t;
412 __asm__ ("mov %0=ar.k5" : "=r"(t));
413 return t;
414 }
415
416 static inline void
417 ia64_set_fpu_owner (struct task_struct *t)
418 {
419 __asm__ __volatile__ ("mov ar.k5=%0" :: "r"(t));
420 }
421
422 #endif /* !CONFIG_SMP */
423
424 extern void __ia64_init_fpu (void);
425 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
426 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
427 extern void ia64_save_debug_regs (unsigned long *save_area);
428 extern void ia64_load_debug_regs (unsigned long *save_area);
429
430 #ifdef CONFIG_IA32_SUPPORT
431 extern void ia32_save_state (struct thread_struct *thread);
432 extern void ia32_load_state (struct thread_struct *thread);
433 #endif
434
435 #ifdef CONFIG_PERFMON
436 extern void ia64_save_pm_regs (struct task_struct *task);
437 extern void ia64_load_pm_regs (struct task_struct *task);
438 #endif
439
440 #define ia64_fph_enable() __asm__ __volatile__ (";; rsm psr.dfh;; srlz.d;;" ::: "memory");
441 #define ia64_fph_disable() __asm__ __volatile__ (";; ssm psr.dfh;; srlz.d;;" ::: "memory");
442
443 /* load fp 0.0 into fph */
444 static inline void
445 ia64_init_fpu (void) {
446 ia64_fph_enable();
447 __ia64_init_fpu();
448 ia64_fph_disable();
449 }
450
451 /* save f32-f127 at FPH */
452 static inline void
453 ia64_save_fpu (struct ia64_fpreg *fph) {
454 ia64_fph_enable();
455 __ia64_save_fpu(fph);
456 ia64_fph_disable();
457 }
458
459 /* load f32-f127 from FPH */
460 static inline void
461 ia64_load_fpu (struct ia64_fpreg *fph) {
462 ia64_fph_enable();
463 __ia64_load_fpu(fph);
464 ia64_fph_disable();
465 }
466
467 static inline void
468 ia64_fc (void *addr)
469 {
470 __asm__ __volatile__ ("fc %0" :: "r"(addr) : "memory");
471 }
472
473 static inline void
474 ia64_sync_i (void)
475 {
476 __asm__ __volatile__ (";; sync.i" ::: "memory");
477 }
478
479 static inline void
480 ia64_srlz_i (void)
481 {
482 __asm__ __volatile__ (";; srlz.i ;;" ::: "memory");
483 }
484
485 static inline void
486 ia64_srlz_d (void)
487 {
488 __asm__ __volatile__ (";; srlz.d" ::: "memory");
489 }
490
491 static inline __u64
492 ia64_get_rr (__u64 reg_bits)
493 {
494 __u64 r;
495 __asm__ __volatile__ ("mov %0=rr[%1]" : "=r"(r) : "r"(reg_bits) : "memory");
496 return r;
497 }
498
499 static inline void
500 ia64_set_rr (__u64 reg_bits, __u64 rr_val)
501 {
502 __asm__ __volatile__ ("mov rr[%0]=%1" :: "r"(reg_bits), "r"(rr_val) : "memory");
503 }
504
505 static inline __u64
506 ia64_get_dcr (void)
507 {
508 __u64 r;
509 __asm__ ("mov %0=cr.dcr" : "=r"(r));
510 return r;
511 }
512
513 static inline void
514 ia64_set_dcr (__u64 val)
515 {
516 __asm__ __volatile__ ("mov cr.dcr=%0;;" :: "r"(val) : "memory");
517 ia64_srlz_d();
518 }
519
520 static inline __u64
521 ia64_get_lid (void)
522 {
523 __u64 r;
524 __asm__ ("mov %0=cr.lid" : "=r"(r));
525 return r;
526 }
527
528 static inline void
529 ia64_invala (void)
530 {
531 __asm__ __volatile__ ("invala" ::: "memory");
532 }
533
534 /*
535 * Save the processor status flags in FLAGS and then clear the
536 * interrupt collection and interrupt enable bits.
537 */
538 #define ia64_clear_ic(flags) \
539 __asm__ __volatile__ ("mov %0=psr;; rsm psr.i | psr.ic;; srlz.i;;" \
540 : "=r"(flags) :: "memory");
541
542 /*
543 * Insert a translation into an instruction and/or data translation
544 * register.
545 */
546 static inline void
547 ia64_itr (__u64 target_mask, __u64 tr_num,
548 __u64 vmaddr, __u64 pte,
549 __u64 log_page_size)
550 {
551 __asm__ __volatile__ ("mov cr.itir=%0" :: "r"(log_page_size << 2) : "memory");
552 __asm__ __volatile__ ("mov cr.ifa=%0;;" :: "r"(vmaddr) : "memory");
553 if (target_mask & 0x1)
554 __asm__ __volatile__ ("itr.i itr[%0]=%1"
555 :: "r"(tr_num), "r"(pte) : "memory");
556 if (target_mask & 0x2)
557 __asm__ __volatile__ (";;itr.d dtr[%0]=%1"
558 :: "r"(tr_num), "r"(pte) : "memory");
559 }
560
561 /*
562 * Insert a translation into the instruction and/or data translation
563 * cache.
564 */
565 static inline void
566 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
567 __u64 log_page_size)
568 {
569 __asm__ __volatile__ ("mov cr.itir=%0" :: "r"(log_page_size << 2) : "memory");
570 __asm__ __volatile__ ("mov cr.ifa=%0;;" :: "r"(vmaddr) : "memory");
571 /* as per EAS2.6, itc must be the last instruction in an instruction group */
572 if (target_mask & 0x1)
573 __asm__ __volatile__ ("itc.i %0;;" :: "r"(pte) : "memory");
574 if (target_mask & 0x2)
575 __asm__ __volatile__ (";;itc.d %0;;" :: "r"(pte) : "memory");
576 }
577
578 /*
579 * Purge a range of addresses from instruction and/or data translation
580 * register(s).
581 */
582 static inline void
583 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
584 {
585 if (target_mask & 0x1)
586 __asm__ __volatile__ ("ptr.i %0,%1" :: "r"(vmaddr), "r"(log_size << 2));
587 if (target_mask & 0x2)
588 __asm__ __volatile__ ("ptr.d %0,%1" :: "r"(vmaddr), "r"(log_size << 2));
589 }
590
591 /* Set the interrupt vector address. The address must be suitably aligned (32KB). */
592 static inline void
593 ia64_set_iva (void *ivt_addr)
594 {
595 __asm__ __volatile__ ("mov cr.iva=%0;; srlz.i;;" :: "r"(ivt_addr) : "memory");
596 }
597
598 /* Set the page table address and control bits. */
599 static inline void
600 ia64_set_pta (__u64 pta)
601 {
602 /* Note: srlz.i implies srlz.d */
603 __asm__ __volatile__ ("mov cr.pta=%0;; srlz.i;;" :: "r"(pta) : "memory");
604 }
605
606 static inline __u64
607 ia64_get_cpuid (__u64 regnum)
608 {
609 __u64 r;
610
611 __asm__ ("mov %0=cpuid[%r1]" : "=r"(r) : "rO"(regnum));
612 return r;
613 }
614
615 static inline void
616 ia64_eoi (void)
617 {
618 __asm__ ("mov cr.eoi=r0;; srlz.d;;" ::: "memory");
619 }
620
621 static inline void
622 ia64_set_lrr0 (__u8 vector, __u8 masked)
623 {
624 if (masked > 1)
625 masked = 1;
626
627 __asm__ __volatile__ ("mov cr.lrr0=%0;; srlz.d"
628 :: "r"((masked << 16) | vector) : "memory");
629 }
630
631
632 static inline void
633 ia64_set_lrr1 (__u8 vector, __u8 masked)
634 {
635 if (masked > 1)
636 masked = 1;
637
638 __asm__ __volatile__ ("mov cr.lrr1=%0;; srlz.d"
639 :: "r"((masked << 16) | vector) : "memory");
640 }
641
642 static inline void
643 ia64_set_pmv (__u64 val)
644 {
645 __asm__ __volatile__ ("mov cr.pmv=%0" :: "r"(val) : "memory");
646 }
647
648 static inline __u64
649 ia64_get_pmc (__u64 regnum)
650 {
651 __u64 retval;
652
653 __asm__ __volatile__ ("mov %0=pmc[%1]" : "=r"(retval) : "r"(regnum));
654 return retval;
655 }
656
657 static inline void
658 ia64_set_pmc (__u64 regnum, __u64 value)
659 {
660 __asm__ __volatile__ ("mov pmc[%0]=%1" :: "r"(regnum), "r"(value));
661 }
662
663 static inline __u64
664 ia64_get_pmd (__u64 regnum)
665 {
666 __u64 retval;
667
668 __asm__ __volatile__ ("mov %0=pmd[%1]" : "=r"(retval) : "r"(regnum));
669 return retval;
670 }
671
672 static inline void
673 ia64_set_pmd (__u64 regnum, __u64 value)
674 {
675 __asm__ __volatile__ ("mov pmd[%0]=%1" :: "r"(regnum), "r"(value));
676 }
677
678 /*
679 * Given the address to which a spill occurred, return the unat bit
680 * number that corresponds to this address.
681 */
682 static inline __u64
683 ia64_unat_pos (void *spill_addr)
684 {
685 return ((__u64) spill_addr >> 3) & 0x3f;
686 }
687
688 /*
689 * Set the NaT bit of an integer register which was spilled at address
690 * SPILL_ADDR. UNAT is the mask to be updated.
691 */
692 static inline void
693 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
694 {
695 __u64 bit = ia64_unat_pos(spill_addr);
696 __u64 mask = 1UL << bit;
697
698 *unat = (*unat & ~mask) | (nat << bit);
699 }
700
701 /*
702 * Return saved PC of a blocked thread.
703 * Note that the only way T can block is through a call to schedule() -> switch_to().
704 */
705 static inline unsigned long
706 thread_saved_pc (struct thread_struct *t)
707 {
708 struct unw_frame_info info;
709 unsigned long ip;
710
711 /* XXX ouch: Linus, please pass the task pointer to thread_saved_pc() instead! */
712 struct task_struct *p = (void *) ((unsigned long) t - IA64_TASK_THREAD_OFFSET);
713
714 unw_init_from_blocked_task(&info, p);
715 if (unw_unwind(&info) < 0)
716 return 0;
717 unw_get_ip(&info, &ip);
718 return ip;
719 }
720
721 /*
722 * Get the current instruction/program counter value.
723 */
724 #define current_text_addr() \
725 ({ void *_pc; __asm__ ("mov %0=ip" : "=r" (_pc)); _pc; })
726
727 #define THREAD_SIZE IA64_STK_OFFSET
728 /* NOTE: The task struct and the stacks are allocated together. */
729 #define alloc_task_struct() \
730 ((struct task_struct *) __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES))
731 #define free_task_struct(p) free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES)
732 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
733
734 #define init_task (init_task_union.task)
735 #define init_stack (init_task_union.stack)
736
737 /*
738 * Set the correctable machine check vector register
739 */
740 static inline void
741 ia64_set_cmcv (__u64 val)
742 {
743 __asm__ __volatile__ ("mov cr.cmcv=%0" :: "r"(val) : "memory");
744 }
745
746 /*
747 * Read the correctable machine check vector register
748 */
749 static inline __u64
750 ia64_get_cmcv (void)
751 {
752 __u64 val;
753
754 __asm__ ("mov %0=cr.cmcv" : "=r"(val) :: "memory");
755 return val;
756 }
757
758 static inline __u64
759 ia64_get_ivr (void)
760 {
761 __u64 r;
762 __asm__ __volatile__ ("srlz.d;; mov %0=cr.ivr;; srlz.d;;" : "=r"(r));
763 return r;
764 }
765
766 static inline void
767 ia64_set_tpr (__u64 val)
768 {
769 __asm__ __volatile__ ("mov cr.tpr=%0" :: "r"(val));
770 }
771
772 static inline __u64
773 ia64_get_tpr (void)
774 {
775 __u64 r;
776 __asm__ ("mov %0=cr.tpr" : "=r"(r));
777 return r;
778 }
779
780 static inline void
781 ia64_set_irr0 (__u64 val)
782 {
783 __asm__ __volatile__("mov cr.irr0=%0;;" :: "r"(val) : "memory");
784 ia64_srlz_d();
785 }
786
787 static inline __u64
788 ia64_get_irr0 (void)
789 {
790 __u64 val;
791
792 /* this is volatile because irr may change unbeknownst to gcc... */
793 __asm__ __volatile__("mov %0=cr.irr0" : "=r"(val));
794 return val;
795 }
796
797 static inline void
798 ia64_set_irr1 (__u64 val)
799 {
800 __asm__ __volatile__("mov cr.irr1=%0;;" :: "r"(val) : "memory");
801 ia64_srlz_d();
802 }
803
804 static inline __u64
805 ia64_get_irr1 (void)
806 {
807 __u64 val;
808
809 /* this is volatile because irr may change unbeknownst to gcc... */
810 __asm__ __volatile__("mov %0=cr.irr1" : "=r"(val));
811 return val;
812 }
813
814 static inline void
815 ia64_set_irr2 (__u64 val)
816 {
817 __asm__ __volatile__("mov cr.irr2=%0;;" :: "r"(val) : "memory");
818 ia64_srlz_d();
819 }
820
821 static inline __u64
822 ia64_get_irr2 (void)
823 {
824 __u64 val;
825
826 /* this is volatile because irr may change unbeknownst to gcc... */
827 __asm__ __volatile__("mov %0=cr.irr2" : "=r"(val));
828 return val;
829 }
830
831 static inline void
832 ia64_set_irr3 (__u64 val)
833 {
834 __asm__ __volatile__("mov cr.irr3=%0;;" :: "r"(val) : "memory");
835 ia64_srlz_d();
836 }
837
838 static inline __u64
839 ia64_get_irr3 (void)
840 {
841 __u64 val;
842
843 /* this is volatile because irr may change unbeknownst to gcc... */
844 __asm__ __volatile__("mov %0=cr.irr3" : "=r"(val));
845 return val;
846 }
847
848 static inline __u64
849 ia64_get_gp(void)
850 {
851 __u64 val;
852
853 __asm__ ("mov %0=gp" : "=r"(val));
854 return val;
855 }
856
857 /* XXX remove the handcoded version once we have a sufficiently clever compiler... */
858 #ifdef SMART_COMPILER
859 # define ia64_rotr(w,n) \
860 ({ \
861 __u64 _w = (w), _n = (n); \
862 \
863 (_w >> _n) | (_w << (64 - _n)); \
864 })
865 #else
866 # define ia64_rotr(w,n) \
867 ({ \
868 __u64 result; \
869 asm ("shrp %0=%1,%1,%2" : "=r"(result) : "r"(w), "i"(n)); \
870 result; \
871 })
872 #endif
873
874 #define ia64_rotl(w,n) ia64_rotr((w),(64)-(n))
875
876 static inline __u64
877 ia64_thash (__u64 addr)
878 {
879 __u64 result;
880 asm ("thash %0=%1" : "=r"(result) : "r" (addr));
881 return result;
882 }
883
884 #endif /* !__ASSEMBLY__ */
885
886 #endif /* _ASM_IA64_PROCESSOR_H */
887
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