1 #ifndef _ASM_IA64_SAL_H
2 #define _ASM_IA64_SAL_H
3
4 /*
5 * System Abstraction Layer definitions.
6 *
7 * This is based on version 2.5 of the manual "IA-64 System
8 * Abstraction Layer".
9 *
10 * Copyright (C) 1998, 1999 Hewlett-Packard Co
11 * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
12 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
13 *
14 * 99/09/29 davidm Updated for SAL 2.6.
15 * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
16 * (plus examples of platform error info structures from smariset @ Intel)
17 */
18
19 #include <linux/config.h>
20 #include <linux/spinlock.h>
21
22 #include <asm/pal.h>
23 #include <asm/system.h>
24
25 extern spinlock_t sal_lock;
26
27 /* SAL spec _requires_ eight args for each call. */
28 #define __SAL_CALL(result,a0,a1,a2,a3,a4,a5,a6,a7) \
29 result = (*ia64_sal)(a0,a1,a2,a3,a4,a5,a6,a7)
30
31 #ifdef CONFIG_SMP
32 # define SAL_CALL(result,args...) do { \
33 spin_lock(&sal_lock); \
34 __SAL_CALL(result,args); \
35 spin_unlock(&sal_lock); \
36 } while (0)
37 #else
38 # define SAL_CALL(result,args...) __SAL_CALL(result,args)
39 #endif
40
41 #define SAL_SET_VECTORS 0x01000000
42 #define SAL_GET_STATE_INFO 0x01000001
43 #define SAL_GET_STATE_INFO_SIZE 0x01000002
44 #define SAL_CLEAR_STATE_INFO 0x01000003
45 #define SAL_MC_RENDEZ 0x01000004
46 #define SAL_MC_SET_PARAMS 0x01000005
47 #define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
48
49 #define SAL_CACHE_FLUSH 0x01000008
50 #define SAL_CACHE_INIT 0x01000009
51 #define SAL_PCI_CONFIG_READ 0x01000010
52 #define SAL_PCI_CONFIG_WRITE 0x01000011
53 #define SAL_FREQ_BASE 0x01000012
54
55 #define SAL_UPDATE_PAL 0x01000020
56
57 struct ia64_sal_retval {
58 /*
59 * A zero status value indicates call completed without error.
60 * A negative status value indicates reason of call failure.
61 * A positive status value indicates success but an
62 * informational value should be printed (e.g., "reboot for
63 * change to take effect").
64 */
65 s64 status;
66 u64 v0;
67 u64 v1;
68 u64 v2;
69 };
70
71 typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
72
73 enum {
74 SAL_FREQ_BASE_PLATFORM = 0,
75 SAL_FREQ_BASE_INTERVAL_TIMER = 1,
76 SAL_FREQ_BASE_REALTIME_CLOCK = 2
77 };
78
79 /*
80 * The SAL system table is followed by a variable number of variable
81 * length descriptors. The structure of these descriptors follows
82 * below.
83 * The defininition follows SAL specs from July 2000
84 */
85 struct ia64_sal_systab {
86 u8 signature[4]; /* should be "SST_" */
87 u32 size; /* size of this table in bytes */
88 u8 sal_rev_minor;
89 u8 sal_rev_major;
90 u16 entry_count; /* # of entries in variable portion */
91 u8 checksum;
92 u8 reserved1[7];
93 u8 sal_a_rev_minor;
94 u8 sal_a_rev_major;
95 u8 sal_b_rev_minor;
96 u8 sal_b_rev_major;
97 /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
98 u8 oem_id[32];
99 u8 product_id[32]; /* ASCII product id */
100 u8 reserved2[8];
101 };
102
103 enum sal_systab_entry_type {
104 SAL_DESC_ENTRY_POINT = 0,
105 SAL_DESC_MEMORY = 1,
106 SAL_DESC_PLATFORM_FEATURE = 2,
107 SAL_DESC_TR = 3,
108 SAL_DESC_PTC = 4,
109 SAL_DESC_AP_WAKEUP = 5
110 };
111
112 /*
113 * Entry type: Size:
114 * 0 48
115 * 1 32
116 * 2 16
117 * 3 32
118 * 4 16
119 * 5 16
120 */
121 #define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
122
123 typedef struct ia64_sal_desc_entry_point {
124 u8 type;
125 u8 reserved1[7];
126 u64 pal_proc;
127 u64 sal_proc;
128 u64 gp;
129 u8 reserved2[16];
130 }ia64_sal_desc_entry_point_t;
131
132 typedef struct ia64_sal_desc_memory {
133 u8 type;
134 u8 used_by_sal; /* needs to be mapped for SAL? */
135 u8 mem_attr; /* current memory attribute setting */
136 u8 access_rights; /* access rights set up by SAL */
137 u8 mem_attr_mask; /* mask of supported memory attributes */
138 u8 reserved1;
139 u8 mem_type; /* memory type */
140 u8 mem_usage; /* memory usage */
141 u64 addr; /* physical address of memory */
142 u32 length; /* length (multiple of 4KB pages) */
143 u32 reserved2;
144 u8 oem_reserved[8];
145 } ia64_sal_desc_memory_t;
146
147 #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1 << 0)
148 #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1 << 1)
149 #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1 << 2)
150
151 typedef struct ia64_sal_desc_platform_feature {
152 u8 type;
153 u8 feature_mask;
154 u8 reserved1[14];
155 } ia64_sal_desc_platform_feature_t;
156
157 typedef struct ia64_sal_desc_tr {
158 u8 type;
159 u8 tr_type; /* 0 == instruction, 1 == data */
160 u8 regnum; /* translation register number */
161 u8 reserved1[5];
162 u64 addr; /* virtual address of area covered */
163 u64 page_size; /* encoded page size */
164 u8 reserved2[8];
165 } ia64_sal_desc_tr_t;
166
167 typedef struct ia64_sal_desc_ptc {
168 u8 type;
169 u8 reserved1[3];
170 u32 num_domains; /* # of coherence domains */
171 u64 domain_info; /* physical address of domain info table */
172 } ia64_sal_desc_ptc_t;
173
174 typedef struct ia64_sal_ptc_domain_info {
175 u64 proc_count; /* number of processors in domain */
176 u64 proc_list; /* physical address of LID array */
177 } ia64_sal_ptc_domain_info_t;
178
179 typedef struct ia64_sal_ptc_domain_proc_entry {
180 u64 reserved : 16;
181 u64 eid : 8; /* eid of processor */
182 u64 id : 8; /* id of processor */
183 u64 ignored : 32;
184 } ia64_sal_ptc_domain_proc_entry_t;
185
186
187 #define IA64_SAL_AP_EXTERNAL_INT 0
188
189 typedef struct ia64_sal_desc_ap_wakeup {
190 u8 type;
191 u8 mechanism; /* 0 == external interrupt */
192 u8 reserved1[6];
193 u64 vector; /* interrupt vector in range 0x10-0xff */
194 } ia64_sal_desc_ap_wakeup_t ;
195
196 extern ia64_sal_handler ia64_sal;
197 extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
198
199 extern const char *ia64_sal_strerror (long status);
200 extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
201
202 /* SAL information type encodings */
203 enum {
204 SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
205 SAL_INFO_TYPE_INIT = 1, /* Init information */
206 SAL_INFO_TYPE_CMC = 2 /* Corrected machine check information */
207 };
208
209 /* Sub information type encodings */
210 enum {
211 SAL_SUB_INFO_TYPE_PROCESSOR = 0, /* Processor information */
212 SAL_SUB_INFO_TYPE_PLATFORM = 1 /* Platform information */
213 };
214
215 /* Encodings for machine check parameter types */
216 enum {
217 SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezevous interrupt */
218 SAL_MC_PARAM_RENDEZ_WAKEUP = 2 /* Wakeup */
219 };
220
221 /* Encodings for rendezvous mechanisms */
222 enum {
223 SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
224 SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
225 };
226
227 /* Encodings for vectors which can be registered by the OS with SAL */
228 enum {
229 SAL_VECTOR_OS_MCA = 0,
230 SAL_VECTOR_OS_INIT = 1,
231 SAL_VECTOR_OS_BOOT_RENDEZ = 2
232 };
233
234 /* Definition of the SAL Error Log from the SAL spec */
235
236 /* Definition of timestamp according to SAL spec for logging purposes */
237
238 typedef struct sal_log_timestamp {
239 u8 slh_century; /* Century (19, 20, 21, ...) */
240 u8 slh_year; /* Year (00..99) */
241 u8 slh_month; /* Month (1..12) */
242 u8 slh_day; /* Day (1..31) */
243 u8 slh_reserved;
244 u8 slh_hour; /* Hour (0..23) */
245 u8 slh_minute; /* Minute (0..59) */
246 u8 slh_second; /* Second (0..59) */
247 } sal_log_timestamp_t;
248
249
250 #define MAX_CACHE_ERRORS 6
251 #define MAX_TLB_ERRORS 6
252 #define MAX_BUS_ERRORS 1
253
254 typedef struct sal_log_processor_info {
255 struct {
256 u64 slpi_psi : 1,
257 slpi_cache_check: MAX_CACHE_ERRORS,
258 slpi_tlb_check : MAX_TLB_ERRORS,
259 slpi_bus_check : MAX_BUS_ERRORS,
260 slpi_reserved2 : (31 - (MAX_TLB_ERRORS + MAX_CACHE_ERRORS
261 + MAX_BUS_ERRORS)),
262 slpi_minstate : 1,
263 slpi_bank1_gr : 1,
264 slpi_br : 1,
265 slpi_cr : 1,
266 slpi_ar : 1,
267 slpi_rr : 1,
268 slpi_fr : 1,
269 slpi_reserved1 : 25;
270 } slpi_valid;
271
272 pal_processor_state_info_t slpi_processor_state_info;
273
274 struct {
275 pal_cache_check_info_t slpi_cache_check;
276 u64 slpi_target_address;
277 } slpi_cache_check_info[MAX_CACHE_ERRORS];
278
279 pal_tlb_check_info_t slpi_tlb_check_info[MAX_TLB_ERRORS];
280
281 struct {
282 pal_bus_check_info_t slpi_bus_check;
283 u64 slpi_requestor_addr;
284 u64 slpi_responder_addr;
285 u64 slpi_target_addr;
286 } slpi_bus_check_info[MAX_BUS_ERRORS];
287
288 pal_min_state_area_t slpi_min_state_area;
289 u64 slpi_br[8];
290 u64 slpi_cr[128];
291 u64 slpi_ar[128];
292 u64 slpi_rr[8];
293 u64 slpi_fr[128];
294 } sal_log_processor_info_t;
295
296 /* platform error log structures */
297 typedef struct platerr_logheader {
298 u64 nextlog; /* next log offset if present */
299 u64 loglength; /* log length */
300 u64 logsubtype; /* log subtype memory/bus/component */
301 u64 eseverity; /* error severity */
302 } ehdr_t;
303
304 typedef struct sysmem_errlog {
305 ehdr_t lhdr; /* header */
306 u64 vflag; /* valid bits for each field in the log */
307 u64 addr; /* memory address */
308 u64 data; /* memory data */
309 u64 cmd; /* command bus value if any */
310 u64 ctrl; /* control bus value if any */
311 u64 addrsyndrome; /* memory address ecc/parity syndrome bits */
312 u64 datasyndrome; /* data ecc/parity syndrome */
313 u64 cacheinfo; /* platform cache info as defined in pal spec. table 7-34 */
314 } merrlog_t;
315
316 typedef struct sysbus_errlog {
317 ehdr_t lhdr; /* linkded list header */
318 u64 vflag; /* valid bits for each field in the log */
319 u64 busnum; /* bus number in error */
320 u64 reqaddr; /* requestor address */
321 u64 resaddr; /* responder address */
322 u64 taraddr; /* target address */
323 u64 data; /* requester r/w data */
324 u64 cmd; /* bus commands */
325 u64 ctrl; /* bus controls (be# &-0) */
326 u64 addrsyndrome; /* addr bus ecc/parity bits */
327 u64 datasyndrome; /* data bus ecc/parity bits */
328 u64 cmdsyndrome; /* command bus ecc/parity bits */
329 u64 ctrlsyndrome; /* control bus ecc/parity bits */
330 } berrlog_t;
331
332 /* platform error log structures */
333 typedef struct syserr_chdr { /* one header per component */
334 u64 busnum; /* bus number on which the component resides */
335 u64 devnum; /* same as device select */
336 u64 funcid; /* function id of the device */
337 u64 devid; /* pci device id */
338 u64 classcode; /* pci class code for the device */
339 u64 cmdreg; /* pci command reg value */
340 u64 statreg; /* pci status reg value */
341 } chdr_t;
342
343 typedef struct cfginfo {
344 u64 cfgaddr;
345 u64 cfgval;
346 } cfginfo_t;
347
348 typedef struct sys_comperr { /* per component */
349 ehdr_t lhdr; /* linked list header */
350 u64 vflag; /* valid bits for each field in the log */
351 chdr_t scomphdr;
352 u64 numregpair; /* number of reg addr/value pairs */
353 cfginfo_t cfginfo;
354 } cerrlog_t;
355
356 typedef struct sel_records {
357 ehdr_t lhdr;
358 u64 seldata;
359 } isel_t;
360
361 typedef struct plat_errlog {
362 u64 mbcsvalid; /* valid bits for each type of log */
363 merrlog_t smemerrlog; /* platform memory error logs */
364 berrlog_t sbuserrlog; /* platform bus error logs */
365 cerrlog_t scomperrlog; /* platform chipset error logs */
366 isel_t selrecord; /* ipmi sel record */
367 } platforminfo_t;
368
369 /* over all log structure (processor+platform) */
370
371 typedef union udev_specific_log {
372 sal_log_processor_info_t proclog;
373 platforminfo_t platlog;
374 } devicelog_t;
375
376
377 #define sal_log_processor_info_psi_valid slpi_valid.spli_psi
378 #define sal_log_processor_info_cache_check_valid slpi_valid.spli_cache_check
379 #define sal_log_processor_info_tlb_check_valid slpi_valid.spli_tlb_check
380 #define sal_log_processor_info_bus_check_valid slpi_valid.spli_bus_check
381 #define sal_log_processor_info_minstate_valid slpi_valid.spli_minstate
382 #define sal_log_processor_info_bank1_gr_valid slpi_valid.slpi_bank1_gr
383 #define sal_log_processor_info_br_valid slpi_valid.slpi_br
384 #define sal_log_processor_info_cr_valid slpi_valid.slpi_cr
385 #define sal_log_processor_info_ar_valid slpi_valid.slpi_ar
386 #define sal_log_processor_info_rr_valid slpi_valid.slpi_rr
387 #define sal_log_processor_info_fr_valid slpi_valid.slpi_fr
388
389 typedef struct sal_log_header {
390 u64 slh_next_log; /* Offset of the next log from the beginning of this structure */
391 u32 slh_log_len; /* Length of this error log in bytes */
392 u16 slh_log_type; /* Type of log (0 - cpu ,1 - platform) */
393 u16 slh_log_sub_type; /* SGI specific sub type */
394 sal_log_timestamp_t slh_log_timestamp; /* Timestamp */
395 } sal_log_header_t;
396
397 /* SAL PSI log structure */
398 typedef struct psilog {
399 sal_log_header_t sal_elog_header;
400 devicelog_t devlog;
401 } ia64_psilog_t;
402
403 /*
404 * Now define a couple of inline functions for improved type checking
405 * and convenience.
406 */
407 static inline long
408 ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
409 unsigned long *drift_info)
410 {
411 struct ia64_sal_retval isrv;
412
413 SAL_CALL(isrv, SAL_FREQ_BASE, which, 0, 0, 0, 0, 0, 0);
414 *ticks_per_second = isrv.v0;
415 *drift_info = isrv.v1;
416 return isrv.status;
417 }
418
419 /* Flush all the processor and platform level instruction and/or data caches */
420 static inline s64
421 ia64_sal_cache_flush (u64 cache_type)
422 {
423 struct ia64_sal_retval isrv;
424 SAL_CALL(isrv, SAL_CACHE_FLUSH, cache_type, 0, 0, 0, 0, 0, 0);
425 return isrv.status;
426 }
427
428
429
430 /* Initialize all the processor and platform level instruction and data caches */
431 static inline s64
432 ia64_sal_cache_init (void)
433 {
434 struct ia64_sal_retval isrv;
435 SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
436 return isrv.status;
437 }
438
439 /* Clear the processor and platform information logged by SAL with respect to the
440 * machine state at the time of MCA's, INITs or CMCs
441 */
442 static inline s64
443 ia64_sal_clear_state_info (u64 sal_info_type, u64 sal_info_sub_type)
444 {
445 struct ia64_sal_retval isrv;
446 SAL_CALL(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, sal_info_sub_type,
447 0, 0, 0, 0, 0);
448 return isrv.status;
449 }
450
451
452 /* Get the processor and platform information logged by SAL with respect to the machine
453 * state at the time of the MCAs, INITs or CMCs.
454 */
455 static inline u64
456 ia64_sal_get_state_info (u64 sal_info_type, u64 sal_info_sub_type, u64 *sal_info)
457 {
458 struct ia64_sal_retval isrv;
459 SAL_CALL(isrv, SAL_GET_STATE_INFO, sal_info_type, sal_info_sub_type,
460 sal_info, 0, 0, 0, 0);
461 if (isrv.status)
462 return 0;
463 return isrv.v0;
464 }
465 /* Get the maximum size of the information logged by SAL with respect to the machine
466 * state at the time of MCAs, INITs or CMCs
467 */
468 static inline u64
469 ia64_sal_get_state_info_size (u64 sal_info_type, u64 sal_info_sub_type)
470 {
471 struct ia64_sal_retval isrv;
472 SAL_CALL(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, sal_info_sub_type,
473 0, 0, 0, 0, 0);
474 if (isrv.status)
475 return 0;
476 return isrv.v0;
477 }
478
479 /* Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup
480 * from the monarch processor.
481 */
482 static inline s64
483 ia64_sal_mc_rendez (void)
484 {
485 struct ia64_sal_retval isrv;
486 SAL_CALL(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
487 return isrv.status;
488 }
489
490 /* Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
491 * the machine check rendezvous sequence as well as the mechanism to wake up the
492 * non-monarch processor at the end of machine check processing.
493 */
494 static inline s64
495 ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout)
496 {
497 struct ia64_sal_retval isrv;
498 SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, timeout,
499 0, 0, 0);
500 return isrv.status;
501 }
502
503 /* Read from PCI configuration space */
504 static inline s64
505 ia64_sal_pci_config_read (u64 pci_config_addr, u64 size, u64 *value)
506 {
507 struct ia64_sal_retval isrv;
508 SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, 0, 0, 0, 0, 0);
509 if (value)
510 *value = isrv.v0;
511 return isrv.status;
512 }
513
514 /* Write to PCI configuration space */
515 static inline s64
516 ia64_sal_pci_config_write (u64 pci_config_addr, u64 size, u64 value)
517 {
518 struct ia64_sal_retval isrv;
519 SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
520 0, 0, 0, 0);
521 return isrv.status;
522 }
523
524 /*
525 * Register physical addresses of locations needed by SAL when SAL
526 * procedures are invoked in virtual mode.
527 */
528 static inline s64
529 ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
530 {
531 struct ia64_sal_retval isrv;
532 SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
533 0, 0, 0, 0, 0);
534 return isrv.status;
535 }
536
537 /* Register software dependent code locations within SAL. These locations are handlers
538 * or entry points where SAL will pass control for the specified event. These event
539 * handlers are for the bott rendezvous, MCAs and INIT scenarios.
540 */
541 static inline s64
542 ia64_sal_set_vectors (u64 vector_type,
543 u64 handler_addr1, u64 gp1, u64 handler_len1,
544 u64 handler_addr2, u64 gp2, u64 handler_len2)
545 {
546 struct ia64_sal_retval isrv;
547 SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
548 handler_addr1, gp1, handler_len1,
549 handler_addr2, gp2, handler_len2);
550
551 return isrv.status;
552 }
553 /* Update the contents of PAL block in the non-volatile storage device */
554 static inline s64
555 ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
556 u64 *error_code, u64 *scratch_buf_size_needed)
557 {
558 struct ia64_sal_retval isrv;
559 SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
560 0, 0, 0, 0);
561 if (error_code)
562 *error_code = isrv.v0;
563 if (scratch_buf_size_needed)
564 *scratch_buf_size_needed = isrv.v1;
565 return isrv.status;
566 }
567
568 #endif /* _ASM_IA64_PAL_H */
569
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